SU1153398A1 - Multichannel redundant synchronizing signal generator - Google Patents

Abstract

A MULTI-CHANNEL-RESERVED SYNCHROGENERATOR, containing in each channel a master pulse generator, is connected via a subtraction element to the input of the n-bit pulse distributor, whose outputs are the outputs of a synchro-generator, characterized in that it accelerates phasing and increases reliability. It includes the first and second element OR, and according to the number of channels, the elements EXCLUDE ORTING OR and the shift registers, the information inputs of which are the sync generator inputs, and the synchronization inputs are connected to the output of the first OR element, which inputs are connected to the second and fourth the outputs of the pulse distributor, the first output of which is the exchange output, and one of the outputs, where 5 is connected to the gate input of the subtraction element, the control input of which is connected to the output of the second KPI element, The terminals of which are connected to the outputs of the EXCLUSIVE OR elements, whose inputs are connected to the outputs of the shift registers. ExchangeByoZ SP OS with so oo

Description

2, The clock generator of claim 1, wherein the / n-bit pulse distributor comprises a binary counter and a decoder, the outputs of which are the outputs of the pulse distributor, and its inputs are connected to the outputs of the binary a counter whose input is the input of the bi nynbsoh distributor.

The invention relates to computing and can be used in the design of redundant digital computing devices and multi-machine complexes with the highest requirements for reliability and speed.

The purpose of the invention is to accelerate phasing and increase reliability.

Fig. 1 shows a block diagram of one channel of a mi channel channel reserved synchronizer; on . 2 is a diagram of the connection of the channels of the redundantly synchronized generator}. in fig. 3 - timing charts of signals at the characteristic points of the multichannel cHHXporeHepafopia, which show its operation.

A multichannel redundant sync generator channel contains a spool generator J, connected via subtraction element 2, to the input of the n-bit pulse distributor 3, first 4 and second: HM elements according to the number of channels. EXTRA 6 or shift registers 7. Distributor outputs pulses 3 YAUTH are the outputs of the sync generator. The information inputs 8 and 9 of the shift registers 7 are output and the sync generator. The sync inputs .poHtfsaiptH of the shift registers 7 are connected to the output of the first element OR 4, the inputs of which are connected to the second and fourth outputs of the pulse distributor 3, the first output is the exchange output, and one of the K outputs, where, is connected to the gate (element input subtraction 2, the control input of which is connected to the output of the second element OR 5, whose inputs are connected to outputs 10 and 11 of elements EXCEPTED SHSh 6. The inputs of the TRIP elements are connected to outputs 12, 13 and 14, 15 of the shift registers 7. In addition, -distributive distribution line number 1 pulsov 3 contains a binary counter 16 and a decoder 17,

S outputs of which are outputs of pulse distributor 3, and, its inputs are connected to outputs of binary counter 16, the input of which is the input of pulse distributor 3.

10 The connection diagram shows the n channels of the redundant sync generator. The exchange output of each phased synchronous generator is connected with its sequence number corresponding to the inputs of each of the phased synchronous generators, except its own.

Timing diagrams at the characteristic points of the multichannel sync generator 20 are depicted for the case when 1 and ill kaNal work in phase, and channel II is 1 beat behind. Plot numbers correspond to the numerals in FIG. one.

25 Consider the operation of a multichannel redundant sync generator for the case when the number of phased) Ps channels is three.

30 On a Start signal, the device returns to its original state. At the same time, the output of the pulse distributor 3 is set to the state O, the pulses from the master oscillator 1

35 through subtraction element 2 begin to arrive at the input of the pulse distributor 3. Binary counter 16 starts counting the pulses. At the same time, at the first output of the decoder 17, the pulse 40 is pulsed, which is fed to the information inputs 8 and 9 of the shift registers 7 of the second and third channels. In turn, the information inputs 8 and 9 of the shift registers 7 of the first channel receive m 3 similar pulses from the second and third channels. To make it possible to distinguish the pulse from the exchange output from the level signals that may occur on it as a result of faults in the phased channels, the distance between the gate pulses arriving at the synchronization inputs of the shift registers; Increasing the pulse duration from the exchange output, which is provided by the gating impulses, for example, from the second and fourth outputs of the distributor 3. At that, three working situations occur at the information inputs 8 and 9 of the shift registers 7. In the case when all channels are corrected. After the start signal, the system began to work in phase or phased, not exceeding the repetition period of the master oscillator 1, a shift 00 will be recorded on the 00. The outputs t and 11 elements EXCEPT OR / 6 also generate a signal t) and. Therefore, the control signal to the subtraction element 2 will not be received. All sync generators will continue to operate at their own frequency. The case when the phase mismatch between the channels reaches a value equal to one pulse repetition period of the master oscillator 1 is illustrated in FIG. 3. In this case, information 01 is written on the shift register 7. At output 10 of the EXCLUSIVE OR element 6, a signal 1 is generated, which After passing through the second element OR 5, it goes to the control input of the subtraction element 2. When the input of the subtraction element 2 is received from the K-th output of the distributor 1 4pulses 3, the subtraction element 2 and from the last About the efficiency of the pulses coming in 984 from the master oscillator 1, one pulse will be cut out (Fig. 3.2). This will lead to the suspension of the corresponding phased synchronous generator for one cycle, due to the fact that the synchronizing generator of all three channels will be phased out. The value of K is chosen from the condition, since the complete information of the shift registers 7 occurs only after the fourth clock cycle of the clock generator. It is preferable to take the signal for gating from the p-th output of the distributor, pulses 3, since this does not distort the timing diagram generated by the synchro-generator. Consider the case when two adjacent channels failed. Failure type: at the exchange output of the pulse distributor 3 or steady-state O, or steady-state with 1 or (in case of decreasing the frequency of the master oscillator 1) the pulse duration from the first output of the pulse-distributor 3 exceeded two repetition periods of the back generator 1. In each of the listed cases in shear the registers 7 will record a combination of either 11 or 00. Both the first and second combinations at output 10 and 11 of the EXCLUSIVE or 6 elements will be O. Consequently, the control signal to subtraction element 2 will not be received and a good sync trainer of will continue to work on their own frequency of the master oscillator 1, ie, the system maintains operability. For the phasing of channel ha to increase reliability, sync generators should be turned on as shown in FIG. 2. The number of inputs of the synchronous generators and the second element OR is determined by the number of phased channels and less by one. With this inclusion of sync generators, any combination of failures does not lead to the failure of the remaining healthy channels.

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Claims (2)

MULTI-CHANNEL RESERVED SYNCHRONORATOR, containing in each channel a master pulse generator, connected through a subtraction element to the input of an n-bit pulse distributor, the outputs of which are outputs of a clock generator, characterized in that, in order to accelerate phasing and increase reliability, the first and the second OR element and, in terms of the number of channels, the EXCLUSIVE OR elements and shift registers, the information inputs of which are the inputs of the sync generator, and the synchronization inputs are connected to the output ohm of the first OR element, the inputs of which are connected to the second and fourth outputs of the pulse distributor, the first output of which is an exchange output, and one of the K outputs, where .5 K-in, is connected to the gate input of the subtraction element, the control input of which is connected to the output of the second an OR element whose inputs are connected to the outputs of the EXCLUSIVE OR elements whose inputs are connected to the outputs of the shift registers. sl oo c s © 00 2. The sync generator according to π.1, is different in that the η "-bit pulse distributor contains a binary counter and a decoder, the outputs of which are the outputs of the pulse distributor, and its inputs are connected to the outputs of the binary counter, whose input is the input of the pulse distributor.