JP3042084B2 - Interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit, and more particularly, to an interface circuit of a TDMA satellite communication earth station apparatus which receives control information from various terrestrial systems via transmission lines.

[0002]

2. Description of the Related Art In a conventional TDMA satellite communication earth station, as shown in FIG. 3, in order to interface with various terrestrial systems (switches, signal multiplexing converters, etc.) via transmission lines 31, 32, Interface circuits 21 and 22 are provided, respectively.

The interface circuits 21 and 22 receive control information S1 and S2 via transmission lines 31 and 32, respectively.
After performing processes such as data phase matching and frame synchronization, the data is once written in the storage circuit 23. Here, the control information is, for example, a subscriber connection command, a subscriber start command, a subscriber stop command, loop test information at the time of a device failure, transmission path abnormality alarm information, and the like.

The line setting circuit 24 reads out and decodes the terrestrial control information held in the storage circuit 23 at a predetermined timing and decodes the control information based on the line setting designation information J1 sent from the reference station via the satellite line. After setting the line, line setting information J2 is generated and sent to a TDMA control circuit (not shown).

[0005]

In the above-described conventional interface circuit, the received control information from the terrestrial system is temporarily written into the storage circuit. Therefore, when the number of interface circuits increases, the capacity of the storage circuit must also be increased, and the circuit scale increases. Further, the line setting circuit has a problem in that real-time processing cannot be performed in accordance with the control information because the line setting circuit reads out and processes the control information once written in the storage circuit at a predetermined timing.

An object of the present invention is to provide an interface circuit capable of simplifying the circuit scale even if the number of interface circuits increases, and capable of real-time processing according to control information.

[0007]

An interface circuit according to the present invention is an interface circuit of a TDMA satellite communication earth station apparatus for receiving control information from various terrestrial systems via respective transmission lines. Input processing means provided for a path to perform processing such as data phase alignment and frame synchronization on the received control information; and a timing pulse within a frame period in synchronization with a frame used in TDMA satellite communication. Generating means, receiving a timing pulse within the frame cycle, setting a plurality of areas within the cycle of the timing pulse, and generating an area designating signal for designating the area for each of the control information; and the input processing means Means for multiplexing by allocating the control information output from within the frame period according to the area designation signal.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Control information S11 to S1N arriving from various terrestrial devices (exchanges, signal multiplexing converters, etc.) via transmission lines 101 to 10N are shown in FIG. , To the interface circuits 1 to N, respectively.

The interface circuits 1 to N have input processing units 11 to 1N and data multiplexing units 21 to 2N, respectively. The input processing units 11 to 1N are connected to each transmission path 101
After receiving the control information S11 to S1N via the control signals S11 to S1N and performing processes such as data phase adjustment and frame synchronization, the control information S11 to S1N are transmitted to the data multiplexing units 21 to 2N as control information S21 to S2N.

The data multiplexing units 12 to 2N transmit control information S2
1 to S2N, and decodes data such as subscriber connection, start and stop commands, loop test information at the time of device failure, and transmission line abnormality alarm information, and sends the decoded control information to the line setting circuit 50. Transfer via the bus 110. In this case, in order to efficiently transfer control information that requires real-time processing time, a frame having a predetermined cycle is configured and transferred via the 8-bit data bus 110. In order to perform such a transfer, a timing pulse generation circuit 30 and an area designation circuit 40 are provided.

The timing pulse generation circuit 30 has a TDM
In synchronization with a frame having a period of 20 ms used in the satellite A communication, a timing pulse Ft having a frame period of, for example, 5 ms is generated.

An area designating circuit 40 receives a timing pulse Ft, sets a plurality of areas within a timing pulse cycle, and designates area designating signals Fe1 to F1 for designating an area.
The eN is generated and transmitted to the data multiplexing units 21 to 2N. As shown in FIG. 2, the area designation signals Fe1 to FeN are signals for designating positions (areas) for the data multiplexing units 21 to 2N to allocate and multiplex their respective pieces of control information within a frame period of 5 ms. . The area designating circuit 40 generates an area designating signal for each interface circuit, and arbitrarily designates a position (area) in a frame according to the number of interface circuits.

The data multiplexing units 12 to 2N store data in areas 1 to N corresponding to the area designation signals Fe1 to FeN, respectively.
The control information S21 to S2N are multiplexed and transmitted in real time as 8-bit parallel data.

The line setting circuit 50 is connected to each data multiplexing unit 21
Ｎ2N, receives the control information transferred via the data bus 110, receives the line setting instruction information J1 transmitted from the reference station via the satellite line, sets the line, and creates the line setting information J2. To a TDMA control unit (not shown). At the time of line setting, processing is performed according to the control information, for example, when a transmission line abnormality alarm is detected in the control information, the line setting for the corresponding channel is not performed.

[0016]

As described above, according to the present invention, the TDMA
A timing pulse within a frame period is generated in synchronization with a frame used in satellite communication, a plurality of areas are set within the period of the timing pulse, and each piece of control information transmitted from various terrestrial devices is stored in each area. By allocating, multiplexing, and efficiently transmitting to the line setting circuit in real time, control information is once written to the storage circuit and not processed as in the past, so even if the number of interface circuits increases, the circuit scale can be simplified. And real-time processing according to the control information becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of a data multiplexing unit shown in FIG.

FIG. 3 is a block diagram for explaining a conventional interface circuit.

[Explanation of symbols]

 1 to N interface circuit 11 to 1N input processing circuit 21 to 2N data multiplexing unit 30 timing pulse generating circuit 40 area designating circuit 50 line setting circuit 101 to 10N transmission path 110 data bus Ft timing pulse Fe1 to FeN area designating signal S11 to S1N , S21 to S2N control information

Claims (1)

(57) [Claims] 1. An interface circuit of a TDMA satellite communication earth station device for receiving control information from various terrestrial devices via transmission lines, wherein said interface circuit is provided for each of said transmission lines and receives said control information. Data phase alignment for information,
Input processing means for performing processing such as frame synchronization;
Means for generating a timing pulse within a frame period in synchronization with a frame used in satellite communication; and receiving a timing pulse within the frame period, setting a plurality of areas within the period of the timing pulse, and An interface circuit comprising: means for generating an area designating signal for designating the area; and means for multiplexing by assigning control information output from the input processing means within a frame period according to the area designating signal. .