JP2630117B2 - ISDN interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ISDN interface circuit, and more particularly to an ISDN interface circuit for real-time signal transmission / reception between an ISDN terminal and a TDMA satellite communication device.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration around a terrestrial interface circuit of a conventional TDMA satellite communication apparatus. Input signals 201 and 20 for certain terrestrial data
3. The data output signals 202 and 204 are interfaced with the terrestrial interface circuits 21 and 22 of the TDMA device. Certain types of terrestrial data include, for example, a 1.5 MBPS transmission line on which subscriber data is multiplexed and an 8 MBPS interface with a terrestrial M20 multiplex converter.
A transmission path. Ground data 201, 20 input
3 is subjected to appropriate processing such as data phase matching and frame synchronization by a terrestrial interface circuit 21 and a terrestrial interface circuit 22, and a terrestrial control signal 205,
206 is sent to the storage circuit 23. In the storage circuit 23, the control signals 205 and 206 are written into appropriate memories at addresses, and the CPU in the line setting decoding circuit 24 reads the data via the CPU bus 207 at appropriate timing. In the line setting decoding circuit 24, the TDM of the reference station is used.
The CPU fetches the line setting instruction information 208 sent from the A control unit (not shown) via the satellite line, decodes the control signals 205 and 206 from the terrestrial system, and creates the line setting information 209 of the own station. To the TDMA control unit.

In the conventional circuit as described above, if the terrestrial interface circuit has three to four ports, the amount of data to be written to the storage circuit 23 is not so large.
At the 0-port level, the data amount also increases dramatically, the memory capacity increases, and the scale of the hardware increases.
This one port means one ground system interface circuit. In a conventional TDMA satellite communication system,
Since subscribers (terminals and the like) in the ISDN were not accommodated, real-time transmission of control signals between the line setting decoding circuit 24 and the terrestrial interface circuit of the TDMA control unit 3 was not required.

[0004]

The above-mentioned conventional circuit configuration has a drawback that as the number of terminal interface ports mounted on the device increases, the memory capacity increases and the hardware scale increases. is there. Further, since the configuration is such that data is once written in the memory and data is read out according to an instruction from the external CPU, there is a disadvantage that the real-time response to a control signal required in the subscriber maker system is lacking.

[0005]

SUMMARY OF THE INVENTION An ISDN interface circuit according to the present invention includes an N (N is an integer) terminal interface circuit having an interface between an ISDN terminal and a control unit of a TDMA satellite communication apparatus, and a reference station of a TDMA satellite communication system. A line setting decoding circuit for inputting the line setting instruction information transmitted from the satellite communication from the base station and transmitting the line setting information to the control unit of the TDMA satellite communication apparatus of the own station, and the own terminal input from the line setting decoding circuit. A frame generation circuit for time-multiplexing response signals of N terminal interface circuits corresponding to corresponding terminal control signals to generate a time reference signal to be transmitted to the line setting decoding circuit; and a frame generated by the frame generation circuit. A timing instructing circuit for instructing where to multiplex, and output from N terminal interface circuits. And a demultiplexer for outputting respectively to the terminal interface circuit that data by separating the data input from the TDMA controller sends out the multiplexed to TDMA control unit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. FIG.
, Terminal signals 103, 1 arriving at the TDMA device
05, 107 are terminal interface circuits 13, 14, 1
5 is input. Appropriate processing (level conversion, cable delay equalization, frame synchronization, etc.) for these terminal signal data
And transmitted to the demultiplexing circuit 17 as transmission data 115, 117, and 119. The demultiplexing circuit 17 multiplexes the data of the terminal interface circuits 13 to 15 and
The multiplexed data 123 is output to the DMA control unit. On the other hand, the multiplexed data 124 input from the TDMA control unit
Are demultiplexed by the terminal interface circuit 13,
Received data 116,1 separated into data for 14 and 15
18 and 120 as terminal interface circuits 13 and 1
4 and 15. The above description is a description of the flow of data (B, D channels) between an ISDN terminal or the like and the TDMA control unit.
It is necessary to establish a layer 1 link defined in the DN. Layer 1 means a physical interface, and is limited here to an electrical interface with a terminal. Incidentally, there are two types of methods for establishing Layer 1. One is when the terminal originates a call, and the other is when the terminal is activated on the network side. Here, it is assumed that the terminal is started from the network side (exchange).

[0007] A terminal control signal is transmitted by a certain transmission line from the ISDN exchange to a reference station that creates a time reference in the TDMA system. In the reference station, the control signal is time-multiplexed on a satellite line together with other data, and TD
Send to slave station in MA system. Each slave station separates the line setting instruction information 121 from the received signal and sends it to the line setting decoding circuit 16. The control signal 11 for each terminal
4 is included in the line setting instruction information 121. Further, the control signal 114 for the terminal means start-up instruction, start-up stop, and test return instruction information of each terminal transmitted from the ISDN exchange.

The line setting decoding circuit 16 separates the line setting information 122 for the own station from the line setting instruction information 121 and transfers it to the TDMA control unit. And the control signal 114 of each terminal is transmitted to each terminal interface circuit 13,
14 and 15. Terminal interface circuit 13,
At 14 and 15, the control signal 114 is received, the control is executed, and a response signal 1 to the control signal 114 is received.
13 is sent back to the line setting decoding circuit 16. Further, the line setting decoding circuit 16 sends a response signal 113 onto the satellite line, and upon receiving the response signal 113, a reference station (not shown) of the satellite line
A response signal will be returned to the exchange. By the way, in the line setting decoding circuit 16, in order to decode the line setting instruction information 121, it is indispensable to perform processing using a normal CPU. However, when the line setting decoding circuit 16 and the terminal interface circuits 13, 14, 15 are to be interfaced with a CPU bus, it is necessary to determine a communication procedure between the two circuits. It is better to use. Here, the restriction on the processing time means a restriction on returning a response signal to the control signal from the exchange in the terminal interface circuits 13, 14, 15 in real time. The time until the response signal is returned is specified. But,
CP as the number of terminal interface circuits increases
Since the processing time of U becomes a problem, various control signals and response signals that require real-time processing time are transmitted to the line setting decoding circuit 16 and the terminal interface circuits 13, 14,.
In order to easily transfer the control signal and the response signal, the control signal and the response signal are multiplexed within a certain time reference. As this configuration, a frame generation circuit 11 and a timing generation circuit 12 are used. The frame generation circuit 11 receives a frame pulse 101 (for example, a period of 20 msec) used in satellite communication from the TDMA control circuit, and generates a timing within a frame period within a desired time reference synchronized with the frame pulse. In this case, the desired frame period is a 5 msec period as shown in FIG. 2, and the timing within the frame period means the counter output signal 109 within the 5 msec period. The counter output signal 109 is input to the timing instruction circuit 12, where the terminal interface circuit 13,
In-frame area signals 110 and 11 to be given to 14 and 15
1, 112 are created. This intra-frame area signal 11
0, 111, and 112 are terminal interface circuits 13,
The response signal 113 detected at 14 and 15 is converted into the above-mentioned 5 ms
Position designation information for multiplexing within the ec cycle. That is, as one example, the in-frame area signal 110 assigns the response signal 113 of the terminal interface circuit 13 to the area 1 as shown in FIG. That is, the signals assigned to the area N are the in-frame area signals 111 and 112.

Although these area signals are required for the number of terminal interface circuits, the timing instruction circuit 12 inputs the identification signal 102 to which area (position) in the frame the signals of each terminal interface circuit are to be transmitted. Will be determined. That is, the timing instruction circuit 12 decodes the value of the identification signal 102 and designates an arbitrary area.

As described above, the terminal interface circuit 1
The use of the hardware 8-bit bus 113 shown in FIG. 2 multiplexes the control signal 3 response signal between the circuits 3, 14, 15 and the line setting decoding circuit 16 so that the interface can be performed without using the CPU bus. Become.

[0011]

As described above, according to the present invention, by providing the frame generation circuit and the timing instruction circuit,
Since the response signals sent from the N terminal interface circuits can be multiplexed in a certain frame and data can be transferred in real time, it is possible to interface the N terminal interface circuits and the line setting decoding circuit with the CPU bus. This also has the effect that the activation time of layer 1 is reduced. In other words, there is an effect that the time required for transmitting the response signal to the control signal instructed from the exchange to the line setting decoding circuit is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a frame configuration diagram illustrating the embodiment.

FIG. 3 is a block diagram of a conventional ISDN interface circuit.

[Explanation of symbols]

Reference Signs List 11 frame generation circuit 12 timing instruction circuit 13, 14, 15 terminal interface circuit 16 line setting decoding circuit 17 demultiplexing circuit 101 timing pulse 102 identification signal 103, 105, 107 input terminal interface signal 104, 106, 108 output terminal interface signal 109 Counter output signal 110, 111, 112 Area instruction signal 113 Response signal 114 Control signal 115, 117, 119 Transmission data 116, 118, 120 Reception data 121 Line setting instruction information 122 Own station line setting information 123 Multiplexed transmission data 124 Multiplexed reception data

Claims (2)

(57) [Claims] 1. An N (N is an integer) terminal interface circuit having an interface between an ISDN terminal and a control unit of a TDMA satellite communication apparatus, and a line setting transmitted from a reference station of the TDMA satellite communication system by satellite communication. A line setting decoding circuit for inputting the instruction information and sending the line setting information to the TDMA satellite communication apparatus control unit of the own station, and N terminals corresponding to the terminal control signal corresponding to the own terminal input from the line setting decoding circuit A frame generating circuit for generating a time reference signal to be time-multiplexed by sending the response signal of the terminal interface circuit of the above to the line setting decoding circuit, and indicating at which position in the frame generated by the frame generating circuit And multiplexes the data output from the N terminal interface circuits and sends the multiplexed data to the TDMA control unit. And a demultiplexing circuit for separating data input from the TDMA control unit and outputting the data to the terminal interface circuit, respectively.
Interface circuit. 2. The N area signals in one frame generated by the frame generation circuit correspond to the area information of the N terminal interface circuits, and the time interval in frame units is at least required in TDMA satellite communication. 2. The ISDN interface circuit according to claim 1, wherein the setting is made within 5 msec for one frame.