KR950005020B1 - Buffer initialized pulse generating device - Google Patents

Abstract

The generator for reducing a buffer size comprises: (a) a clock generator that generating a clock after receiving a clock signal, a clock gapping signal, a comparison permitting signal, a comparison result reverse signal and a V5 start signal; (b) a V5 generator supplying a V5EN signal; (c) a V5 comparator timing generator supplying a comparison time indication signal, a clock gapping signal, and a comparison permitting signal; (d) a 5V comparator supplying a comparison result signal and a comparison result reverse signal; (e) a 5V decision part supplying a V5 start signal and a reset formation indication signal; and (f) an initialization pulse generator generating a reset pulse signal.

Description

Buffer initialization pulse generator

1 is a frame structure diagram of TU11 and VC11.

2 is an illustration of a timing diagram in accordance with the present invention.

3 is a circuit diagram according to the present invention.

4 is a schematic diagram of a 208K clock generator.

5 is a schematic diagram of a V5 comparator timing generator.

6 is a block diagram of a V5 comparator.

7 is a configuration diagram of the V5 determinator.

8 is a schematic diagram of a V5 generator.

9 is a block diagram of an initialization pulse generator.

* Explanation of symbols for main parts of the drawings

100: 208K clock generator 200: V5 generator

300: V5 Comparator Timing Generator 400: V5 Comparator

500: V5 determiner 600: initialization pulse generator

The present invention initializes buffers and counters used to form a TU (Tributary Unit) 11 by mapping a DS1 (1.544 Mbps) signal to a VC (Virtual Container) 11 among low-speed multiple processing units applied to a synchronous multiplexer of a digital synchronous transmission system. It relates to a pulse generator for.

In FIFO (First In First Out), which has been applied to the conventional transmission technology, the two signals are asynchronous in order to multiplex the DS1 signal to the DS2 signal (6.312 Mbps) according to the characteristics of the digital phase (PHD) of the asynchronous transmission signals. Based on the positive stuffing (Positive Stuffing) technique. Therefore, even when the DS1 signals are temporarily stored and read out before multiple times, the phase comparator according to the multiple system is used so that the write and read times are automatically adjusted.

However, all signals applied to SDH (Synchronous Digital Hierarchy) basic synchronous multiplex devices that are currently accepted around the world are synchronized, so that when the write and read points are overlapped once in using FIFO, they are repeatedly There was a problem that the input data of the FIFO was not output properly because it was overlapped at the same time.

In order to solve the above problems, the present invention provides a buffer in which a 1.544 Mbps DS1 signal, a V5 byte corresponding to a path overhead (POH), a fixed bit, and a VC11 signal composed of bits used for stuffing are formed. The purpose of the present invention is to provide a buffer initialization pulse generation device capable of reducing the size of a buffer required by specifying a write / read point of a buffer in advance in reading by a gapped clock to be multiplexed to TU11 after being written to TU11. have.

In order to achieve the above object, the present invention provides a buffer initialization pulse generator of a low speed multi-layer processing unit applied to a synchronous multiplexer of a digital synchronous transmission system, wherein a clock signal is input from an external timing supply unit, and a comparison is possible with a clock gapping signal. Clock generation means for generating a clock by receiving an inverted signal and a V5 start signal as a result of comparison with the signal; V5 generation means for receiving a T208K signal from the clock generation means and supplying a V5EN signal; V5 comparator timing generating means for receiving a clock signal from an external timing supply part and a V5EN signal from the V5 generating means, receiving a comparison result signal, and providing a comparison time indication signal, a clock gapping signal, and a comparison allowable signal; 5V comparison which receives a clock signal, a TG216K signal, a V5EN signal from the V5 generation means, a comparison time indication signal from the V5 comparison timing generating means and a comparison allowable signal, and generates and supplies a comparison result signal and a comparison result inversion signal. Means from a V5 confirming means and an external timing supply for receiving and supplying a clock signal from an external timing supply and a V5EN signal from the V5 generating means and a comparison result signal from the V5 comparing means to generate and supply a V5 start signal and a reset formation indication signal; Clock signal and the V5 generating means Receiving the comparison signal and the enable signal from the V5EN V5 reset instruction signal formed with the V5 Comparator timing generation means from the fixed means characterized in that it comprises a set-up pulse generating means for generating a reset pulse signal.

In synchronous multiplexing, the DS1 signal is once mapped to the VC11 signal and then multiplexed to TU11. The pointer of TU11 indicates the position of V5, the starting point of VC11.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

FIG. 1 is a frame structure diagram of TU11 and VC11, FIG. 2 is a diagram illustrating a timing diagram according to the present invention, FIG. 3 is a circuit diagram of the present invention, FIG. 4 is a block diagram of a 208K clock generator, and FIG. 5 is a V5 comparator timing. Schematic diagram of the generator.

6 is a configuration diagram of the V5 comparator, FIG. 7 is a configuration diagram of the V5 determinator, FIG. 8 is a configuration diagram of the V5 generator, and FIG. 9 is a configuration diagram of the initialization pulse generator.

TU11 composed of multiple frames is shown in FIG. 1 and V1 and V2 indicate the position of V5 bytes of VC11.

The V3 byte is a pointer adjustment byte, and the purpose of the V4 byte is still unknown. The DSl signal is mapped to the VC11 frame shown in FIG. 1 and read by a gapped clock (one pulse-gap clock at 216 KHz) supplied by a functional unit that writes to a buffer to form TU11. The instantaneous frequency of the gapped clock is faster than the instantaneous frequency of VC11 (208KHz), so the VC11 data must be written to and read from the buffer, and the point should be at least as far apart as the gapped portion.

Because of this, the capacity of the buffer must be large and the buffer capacity can be minimized by adjusting the initial value of the write / read control signals. The phase relationship between the pulse (reset pulse) for initializing the write / read control signals formed by the present invention and the external gapping clock is shown in FIG.

3 is a configuration diagram according to the present invention, where 100 is a 208K clock generator, 200 is a V5 generator, 300 is a V5 comparator timing generator, 400 is a V5 comparator, 500 is a V5 determinator, and 600 is an initialization pulse generator.

The operation of the 208K clock generator 100 will be described with reference to FIG.

The 208K clock generator 100 receives a 1.664KHz transmission clock 1 supplied from an external timing supply unit and generates a T208K clock 2 of 208KHz using an internal eight-division counter. When the comparison result inverted (5) signal supplied from the V5 comparator 400 and the comparison allowable (6) signal supplied from the V5 comparator timing generator 300 are both high, the clock gapping supplied from the V5 comparator timing generator 300 ( 7) The two clocks of the 1.664 KHz T1.6M (1) signal belonging to the high state of the signal fail to drive the counter, causing the instantaneous period of the T208K (2) signal to increase, resulting in the V5EN (3) generated by the V5 generator 200. Causes the signal to be delayed.

The 208K clock generator 100 is a circuit that can be implemented using a commercially available counter circuit, which is generally widely used. In the present invention, the present invention uses signals (4), (5), (6), and (7). In order to output the T208K with the phase required by the circuit, the combination of commercially negative AND gates, AND gates, and flip-flops were adjusted to adjust the counter's repetition period.

When the inverted signal 5 and the comparison allowable signal 6 supplied from the V5 start signal 4 and the V5 comparator timing generator 300 supplied from the V5 determinator 500 are low, the clock gapping signal 7 ) Is ignored and the T208K (2) signal is delayed by the V5 start signal 4 generated by the V5 determinator 500, and the V5 start signal 4 ends with only one pulse. The V5 generator 200 receives the T208K (2) signal supplied from the 208K clock generator 100 and continuously generates a V5EN (3) signal of 2KHz. The detailed configuration is shown in FIG.

The V5 comparator timing generator 300 transmits a 1.664 kHz T1.6M (1) signal and a V5 comparator from an external timing supply before a pulse of the V5 start (4) signal generated by the V5 determinator 500 is generated. A comparison result 8 signal generated at 400 and a V5EN (3) signal generated from the V5 generator 200 are received. As shown in FIG. 5, the T1.6M (1) signal and the V5EN (3) signal generate timings for the comparison signal generator 520 and the clock enabler 530 to operate in the internal timing generator 510.

The comparison signal generator 520 and the clock enabler 530 generate a comparison allowance 6 signal and a clock gapping signal 7, respectively, and supply the signal to the 208K clock generator 100 to the V5 comparator 400. Supply the time signal for comparison indication (9).

The timing generator receives the 1.664M1Bz T1.6M signal 1 from the external timing driver and the V5EN signal 3 from the V5 generating means 200, and outputs a timing signal and a comparison time indication signal 9, The comparison signal generator receives the comparison start signal 9 of the timing generator 9 and the comparison result signal 8 of the V5 comparator 400, and outputs a comparison allowable signal 6. The clock enable unit is configured to match the timing signal of the timing generator. The clock gapping signal 7 is outputted by receiving the comparison time start signal 9.

Referring to the V5 comparator 400 using the configuration shown in Figure 6 as follows.

The V5 comparator 400 is a V5EN (3) signal supplied from the V5 generator 200, a 1.644 MHz T16M (1) signal and an 208K TG216K (10) signal from an external timing supply unit, and the V5 comparator timing generator 300. Receive the supplied comparison time indication (9) signal and comparison allowance (6) signal.

The V5 signal / TG216K-end 610 receives the V5EN (3) signal and the TG216K (10) signal and inverts and multiplies the TG216K (10) signal. The ANDed output is supplied to the buffer 620 and latched by the comparison time indication (9) signal and the T1.6M (1) clock.

This process is repeated until the comparison allowance (6) signal becomes low and when the comparison allowance (6) signal becomes low, the comparison result (8) signal becomes high and the comparison result is reversed. (5) The signal goes high.

As shown in FIG. 7, the V5 determiner 500 includes a V5EN (3) signal generated by the V5 generator 200 and a comparison result 8 signal generated by the V5 comparator 400 and an external timing supply unit. It receives the 1.664MHz T1.6M (1) clock provided. The gating unit 710 generates a reset formation instruction 11 signal when the pulse of the V5EN (3) signal is input while the comparison result 8 signal is low, and the internal delay unit 720 generates the gating unit ( The recess forming instruction 11 signal supplied from 710 is delayed by the T1.6M (1) clock provided from an external timing supply unit to form a V5 start (4) signal, and is supplied to the 208K clock generator 100.

As shown in FIG. 9, the initialization pulse generator 600 generates a V5EN (3) signal generated by the V5 generator 200, a comparison allowable 6 signal generated by the V5 comparator timing generator 300, and V5. When the reset forming instruction 11 signal generated by the determiner 500 is received and the V5EN (3) signal is input when the reset forming instruction 11 signal and the comparison allowable 6 signal are both low, the reset pulse 14 is received. ) Signal is generated only once.

In the present invention configured and operated as described above, the DSI signal is connected to a low speed multiplexing unit applied to a synchronous multiplexer of a digital synchronous transmission system, mapped to a VC11 signal, and then written to a buffer to be multiplexed into a TU11 signal, and then gapped. By using the reset TU11 signal generation clock that is read, the reset pulse 14 signal generated as described above can indicate the write and read start points to minimize the buffer capacity. To make it possible.

Claims (5)

In the buffer initialization pulse generator of the low speed multilayer processing unit applied to the synchronous multiplexer of the digital synchronous transmission system, the clock signal 1 is input from an external timing supply unit, and the clock gapping signal 7 and the comparison allowable signal 6 Clock generation means 100 for generating a clock by receiving the inverted signal 5 and the V5 start signal 4 as a result of the comparison; V5 generating means (200) for receiving the T208K signal (2) from the clock generating means (100) and supplying a V5EN signal (3), a clock signal (1) from the external timing supply unit and the V5 generating means (200). A V5 comparator timing generating means for receiving a V5EN signal 3 from the V5EN signal 3 and receiving a comparison result signal 8 and providing a comparison time indication signal 9, a clock gapping signal 7, and a comparison allowable signal 6; 300); The clock signal 1 and the TG216K signal 10 from the external timing supply unit, the V5EN signal 3 from the V5 generating means 200 and the comparison time indicating signal 9 from the V5 comparing timing generating means 300; 5V comparison means 400 for receiving the comparison allowable new article 6 and generating and supplying a comparison result signal 8 and a comparison result inversion signal 5; The V5 start signal 4 receives the clock signal 1 from the external timing supply unit, the V5EN signal 3 from the V5 generating means 200 and the comparison result signal 8 from the V5 comparing means 400. And V5 deciding means 500 for generating and supplying a reset formation instruction signal 11; And a clock signal 1 from an external timing supply unit, a V5EN signal 3 from the V5 generating means 200, a reset formation instruction signal 11 from the V5 determining means 500, and the V5 comparator timing generating means. And an initialization pulse generating means (600) for receiving the comparison allowable signal (6) from the (300) and generating a reset pulse signal (14). The counter enable means according to claim 1, wherein the clock generating means (100) receives a clock gapping signal (7), a comparison allowable signal (6), and a comparison result inversion signal (5) and outputs a counter enable signal. ; And a dispensing means for receiving a counter enable signal from the counter enable means, operating the clock enable signal, receiving a clock signal 1 from an external timing supply unit, and receiving the V5 start signal 4 to generate a clock. Buffer initialization pulse generator. The V5 comparator timing generator 300 receives a clock signal 1 from an external timing driver and a V5EN signal 3 from the V5 generator 200, and compares the timing signal with the timing signal. Timing generating means for outputting an instruction signal (9): A comparison start signal (9) of the timing generating means and the comparison result signal (8) of the V5 comparing means (400) are input to output a comparison allowable signal (6). Comparison signal generation means; And clock enable means for receiving a timing signal of the timing generating means and a comparison time start signal (9) and outputting a clock gapping signal (7). According to claim 1, wherein the V5 comparison means 400 receives the TG216K signal 10 from the outside and the V5EN signal (3) from the V5 generating means 200 inverts the TG216K signal 10 to logic V5 signal / TG216K logical product calculating means for multiplication and outputting, output and comparison allowable signal 6 of the V5 signal / TG216K logical product calculating means, comparison time indicating signal 9 and clock signal 1 from outside Buffering means for receiving a comparison result signal (8) and a comparison result inversion signal (5). The method of claim 1, wherein the V5 determination means 500 is configured to receive the comparison result signal 8 from the V5 comparison means 400 and the V5EN signal 3 from the V5 generation means 200 to form a reset. A gating means for outputting an instruction signal 11, and a delay means for receiving a reset instruction signal 11 from the gating means and a clock signal 1 from an external timing driver and outputting a V5 start signal 4; And a buffer initialization pulse generating device.