KR0165054B1 - Data stuffing device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data stuffing apparatus for stuffing various types of data formats received using a digital signal processor to fit a bit-rate to be transmitted.

The present invention provides multiple / demultiplexing means for multiplexing or demultiplexing data received in various data formats according to the HDSL frame format, and stuffing corresponding to variable HDSL frame length due to a difference between a bit rate of input data and a bit rate of output data. Clock control means for generating a clock and generating data reading and reading signals, a central processing unit for generating a data format control signal and a digital signal processing means reset signal according to the speed and format of the received data; Data format selection means for selecting a data format according to a data format control signal generated from the central processing unit, and underwriting or over-processing the data write and read signals obtained by the clock control means periodically according to the signal obtained from the address decoder. Request signal processing means for monitoring the flow; And retrieving the data format from the data format selection means in accordance with the data recording and reading signals obtained by the clock means, processing the received digital data corresponding to the format, and transmitting the received data in a loop, and transmitting data in the reverse direction. Digital signal processing means for transmitting to the outside through the multiplexing means.

Description

Data Stuffing Device

1 is a block diagram of a conventional data stuffing device.

2 is a block diagram of a data stuffing apparatus of the present invention.

* Explanation of symbols for main parts of the drawings

102: phase comparison unit 104: digital signal processing unit

105: clock control unit 106: central processing unit

107: data format selector 109: address decoder

110: request signal processing unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data stuffing, and in particular, a stuffing apparatus for stuffing data to be bit-rate to transmit various types of data formats received using a digital signal processor. It is about.

In general, the stuffing technique uses a first-in-first-out buffer (fifo) as an elastic store to control the stuffing by controlling the data as the speed of the data input to the elastic reservoir and the speed of the output data.

As shown in FIG. 1, the conventional data stuffing device to which the stuffing technique is applied, the demultiplexer 1 demultiplexes the received serial data and divides the data into half of a Dsx-1 frame and outputs the demultiplexer 1. ), A phase comparator for comparing a phase of the clock LCK and the received clock RCLK obtained from the oscillator 2 and outputting a value corresponding to the phase difference. 3) a first clock control unit which outputs the synchronous clocks ICK1 and ICK2 of the received clock RCLK and generates the stuffing clocks LCLK1 and LCLK2 according to the output of the phase comparator 3; 4) and LOOP1 data and LOOP2 data divided in half of the Dsx-1 frame obtained from the demultiplexer 1 in synchronization with the stuffing clocks LCK1 and LCK2 generated by the first clock control unit 4, respectively. First, second, first-in, first-out (5), 6, first-in, first-out, loop (RLOOP # 1, Third and fourth first-in, first-outs (8) (9) for first-in first-out in synchronization with the reverse stuffing clocks (ICK3, ICK4) generated by the second clock control unit (7) respectively from the RLOOP # 2; The third and third phases in synchronization with the phase-locked loop circuit 10 that generates the transmission clock TCLK by phase-locking the stepping clock LCLK and the transmission clock TCLK obtained by the phase-locked loop circuit 10. It consists of a multiplexing section 11 for multiplexing the data (LOOP1 Data, LOOP2 Data) obtained in each of the four first-in first-out sections 8 and 9 as serial data.

The operation of the conventional data stuffing device configured as described above will be described in detail as follows.

First, the deserialization unit 1 divides the received serial data into loops 1 and 2 (LOOP1 and LOOP2) by 1/2 of a Dsx-1 frame, and thereby the first and second first-in first-out units 5. Input each to (6).

At this time, clocks ICK1 and ICK2 synchronized with the reception clock RCLK obtained by the first clock controller 4 are input to the first and second first-in, first-out units 5 and 6.

On the other hand, the phase comparator 3 compares the phase of the oscillation clock LCLK obtained from the oscillator 2 and the reception clock RCLK and inputs the difference value to the first clock controller 4 described above.

Accordingly, the first clock controller 4 generates the stuffing clocks LCLK1 and LCLK2 according to the phase difference values and inputs the stuffed clocks LCLK1 and LCLK2 to the first and second first-in, first-out units 5 and 6, respectively.

Therefore, the first and second first-in, first-out units 5 and 6 first input and output the input data LOOP1 Data and LOOP2 Data in synchronization with the stuffing clocks LCLK1 and LCLK2 described above, so that the loops (TLOOP # 1, TLOOP #) are first-in-first-out. 2).

Meanwhile, the data received from the loops RLOOP # 1 and RLOOP # 2 is input to the third and fourth first-in, first-outs 8 and 9, wherein the second clock control unit 7 receives the clock received from the loop ( The reverse stuffing clocks ICK3 and ICK4 are generated using LCLK 3 and input to the third and fourth first-in, first-out parts 8 and 9, respectively.

Accordingly, the third and fourth first-in-first-out units 8 and 9 synchronize the data (data obtained from the RLOOP # 1 and the RLOOP # 2) input to the above-mentioned reverse surfping clocks ICK3 and ICK4, and the multiplexer 11 ) Respectively.

Accordingly, the multiplexer 11 synchronizes with the transmission clock TCLK obtained from the phase locked loop circuit 10, that is, the data LOOP1 obtained from the third and fourth first-in-first-out units 8 and 9, respectively. Data, LOOP2 Data) is multiplexed to make a complete Dsx-1 frame for transmission.

However, such a conventional data stuffing device does not adequately cope with underflow or overflow of data, and also supports a variety of received data formats due to complicated hardware configuration and difficult periodic clock control of the first-in, first-out. There was a problem that was difficult to do.

Accordingly, an object of the present invention is to solve the above-mentioned problems of the prior art, and an object of the present invention is to fit a bit-rate to transmit various types of data formats received using a digital signal processor (DSP). The present invention provides a stuffing device for stuffing data.

Means for achieving the object of the present invention is a multiplex / demultiplexing means for multiplexing or demultiplexing the data received in various data formats according to the HDSL frame format, and HDSL by the difference between the bit rate of the input data and the bit rate of the output data Clock control means for generating a stuffing clock corresponding to a variable frame length, and generating a write and read signal of data;

A central processing unit for generating a data format control signal and a digital signal processing means reset signal in accordance with the speed and format of the data; data format selecting means for selecting a data format in accordance with the data format control signal generated from the central processing unit; And request signal processing means for periodically monitoring the underflow or overflow by processing the data write and read signals obtained by the clock control means according to the signal obtained from the address decoder, and according to the data write and read signals obtained by the clock means. A digital signal processing means for extracting a data format from the data format selecting means, processing the received digital data corresponding to the corresponding format, transmitting the received data in a loop, and transmitting the transmitted data to the outside through the demultiplexing means. Is done.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

FIG. 2 is a block diagram of a data stuffing apparatus of the present invention, which is generated from the demultiplexer 100 for demultiplexing the received serial data as shown, and the received clock RCLK and the oscillator 101. A phase comparator 102 for comparing the phase with the internal clock and providing a stuffing clock, and a phase for fixing the phase of the internal clock and the transmission clock RLCLK generated from the oscillator 101. A synchronous loop circuit 103, the reception clock RCLK, the transmission clock RLCLK, the stuffing clock, the phase synchronization clock RLCLK-PLL, and a transmission clock TCLK suitable for the bit rate to be transmitted and A clock control unit 105 for generating a stuffing clock (TLCLK) corresponding to the bit rate to be received, applying a write and read signal of the digital signal processing unit 104, and generating request signals (Requests 1 to 4), and a transmission and reception unit. The format control signal of the data is generated and the digital A central processing unit 106 for resetting the signal processing unit 104, a data format selecting unit 107 for selecting a data format according to a data format control signal obtained from the central processing unit 106, and the clock control unit ( A digital signal processing unit 104 for processing digital signals by appropriately adjusting the format of the transmission and reception data according to the write and read signals INT1 and INT2 obtained from 105 and the data format obtained from the data format selector 107; A multiplexer 108 for multiplexing the transmitted data processed by the digital signal processor 104 and transmitting the serial data; an extended data memory selection address (DMS) obtained from the digital signal processor 104, and a write / read address. An address decoder 109 which decodes (RD, WR) and outputs 4-bit CLK-RESET and CLX-POLL signals, and request signals Request 1 to 4 obtained by the clock control section 105; The request signal processor 110 is configured to compare the CLK-POLL signal obtained from the address decoder 109 and feed back a signal for turning on and off the flag to the digital signal processor 104.

Referring to the operation and effects of the data stuffing device of the present invention configured as described above in detail.

First, the received serial data is demultiplexed by the demultiplexer 100.

The demultiplexed data is processed by the digital signal processor 104 according to the HDSL data format and transmitted to the loops (TLOOP # 1 and TLOOP # 2).

That is, the central processing unit 106 outputs a data format control signal in accordance with the speed and format of the received data and resets the digital signal processing unit 104.

The data format selector 107 selects the corresponding data format by the data format control signal output from the CPU 106, and the digital signal processor 104 is reset to reset the data format selector. The data format selected in step 107 is read to set an internal buffer type.

On the other hand, the phase comparator 102 compares the received clock RCLK and an internal clock generated from the oscillator 101 to generate a stuffing clock to be input to the clock controller 105. .

Accordingly, the clock controller 105 generates a clock TLCLK synchronized with the stuffing clock and transmits it to a subsequent loop to enable processing of the received data.

In addition, according to the clock RLCLK received from the loop and the internal clock generated from the oscillator 101, the phase locked loop circuit 103 selects a clock (PLCLK-PLL) corresponding to the bit rate to be transmitted. Is generated and applied to the clock control section 105 described above.

Accordingly, the clock control unit 10f generates and transmits a transmission clock TCLK at a clock corresponding to the bit rate to be transmitted, and inputs the multiplexing unit 108 to select the cycle of multiplexing.

On the other hand, data should be input (In) or output (out) from the buffer in the digital signal processing unit 140 in accordance with the clock (RCLK, TCLK, TLCLK, PLCLK) rate, the input and output of the data corresponding to the clock The request can be made by outputting the request signals Request 1 to 4 from the clock control section 105.

In addition, the clock controller 105 periodically applies signals INT1 and INT2 to the digital signal processor 104 to prevent a pointer malfunction of a buffer in the digital signal processor 104.

The request signals Request 1 to 4 generated by the clock control unit 105 are transmitted to the request signal processing unit 110. Accordingly, the request signal processing unit 110 transmits the four request signals Request 1 to 4. Search for the presence or absence of the request signal in the order of the clocks CLK-POLL 1 to 4 decoded from the address decoder 109, and if there is a request, turn on the flag with flag in (F1). The signal is turned off from the address decoder 109 to the decoded clocks CLK RESET 1 to 4.

If the request signal is not ON when the request signal is searched with the CLK-POLL, the next request signal is searched.

In this series of operations, the digital signal processing unit 104 processes the received data corresponding to the corresponding format and transmits 1 of the Dsx-1 frame to the loop (TLOOP # 1, TLOOP # 2) through the demultiplexer 100. Transmit by dividing into 2 frames.

In addition, the transmission data is processed and applied to the multiplexer 100 as data in a form corresponding to the transmission format. Accordingly, the multiplexer 108 transmits the data to the transmission clock TCLK obtained by the clock control unit 10f. In synchronization, the transmission data are multiplexed into Dsx-1 frames and transmitted on the transmission path.

As described in detail above, the present invention has the effect of reducing a large amount of hardware by using an elastic store for the digital signal processing unit, and also can not only completely control the flow of data but also various There is an effect that can be applied to the frame format of the data.

Claims (1)

Generating multiple / demultiplexing means for multiplexing or demultiplexing data received in various data formats according to the HDSL frame format, and generating a stuffing clock corresponding to a variable HDSL frame length due to a difference between the bit rate of the input data and the bit rate of the output data. Clock control means for generating data writing and reading signals, a central processing unit for generating a data format control signal and a digital signal processing means reset signal in accordance with the speed and format of the received data; Data format selecting means for selecting a data format according to the generated data format control signal, and periodically processing the data write and read signals obtained by the clock control means according to the signal obtained from the address decoder to monitor for underflow or overflow. Request signal processing means and the clock means. According to the obtained data recording and reading signal, the data format is extracted from the data format selecting means, the received digital data is processed corresponding to the format, and the received data is transmitted to the loop, and the transmitted data is externally transmitted through the demultiplexing means. And a digital signal processing means for transmitting the data.