JP2968781B1 - ATM cell multiplexing circuit - Google Patents

Abstract

The present invention multiplexes ATM cells of various input lines without being limited by the line speed and bit width of input ATM cells, and supplies the same circuit speed and bit width to a subsequent circuit. Outputs ATM cells. SOLUTION: Serial-parallel conversion circuits 14 to 19, multiplexing circuits 20 to 21 and a selection circuit 22 are provided with input AT.
According to the bit width of the M cell, for example, when the input bit width is 8 bits, four lines are multiplexed and the output bit width 32
When the input bit width is 16 bits, two lines are multiplexed and output with an output bit width of 32 bits. When the input bit width is 32 bits, only one line has an output bit width of 32 bits. Output in bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an input AT
AT without being restricted by the line speed and bit width of M cells
The present invention relates to an ATM cell multiplexing circuit that can accommodate M cells.

[0002]

2. Description of the Related Art Generally, an ATM cell multiplexing circuit has a single ATM cell line speed and bit width of a single ATM cell.
Although the cell is multiplexed, in recent years the line speed has been
0Mbps OC3 or 600Mbps line speed O3
As in C12, it is required that data converted into AM cells for various line speeds and bit widths be multiplexed and accommodated in an ATM exchange.

In order to meet this demand, for example, as disclosed in Japanese Patent Application Laid-Open No. 06-053989, the line speed and bit width of an input ATM cell are set to a single AT.
It has been proposed to multiplex M cells.

[0004]

The technique disclosed in this prior art document is shown in FIG. 15, which multiplexes ATM cells having a single line speed and bit width of input ATM cells. Therefore, A for various line speeds and bit widths
Cannot accommodate TM cells. For this reason, in the case of ATM cells having different line speeds and bit widths, the operation becomes impossible to connect. As a result, in order to connect ATM cells having different line speeds and bit widths, there is a disadvantage that the circuit speed must be changed or added to match the line speed and the bit width.

[0005] Further, in order to change or add a circuit, a development period, a development cost, and man-hours are indispensable, so that a delivery time and cost, which are important factors in developing a replacement system, increase. There are also problems.

[0006] The main object of the present invention is to provide the line speed of ATM cells input from various line processing circuits and the like in one development,
An object of the present invention is to provide an ATM cell multiplexing circuit capable of accommodating ATM cells of various line speeds and bit widths only by switching a select signal without being limited by a bit width.

[0007]

According to the present invention, there is provided a cell buffer for storing input ATM cell data and switching clock speeds, and an A buffer output from the cell buffer.
A serial / parallel conversion circuit for adjusting the bit width of the TM cell to the output bit width, and a multiplexing circuit for multiplexing the data of the serial / parallel-converted ATM cell are limited to the line speed and bit width of the input ATM cell. ATM cells of various lines input are multiplexed, and AT circuits having the same line speed and bit width
An ATM cell multiplexing circuit for outputting M cells , wherein
The real-parallel conversion circuit is an 8-bit → 32-bit serial
All-parallel conversion circuit and 16-bit → 32-bit serial
And the multiplexing circuit has two cells.
→ 1 cell multiplexing circuit and 4 cells → 1 cell multiplexing circuit,
When the bit width of the input ATM cell is 8 bits
Four lines are multiplexed and output with an output bit width of 32 bits.
If the bit width is 16 bits, multiplex two lines
Output with an output bit width of 32 bits and input bit width
Is 32 bits, the output bit width is 32 bits for only one line.
It is characterized in that the data is output in a unit.

The present invention can accommodate ATM cells without being limited by the line speed and bit width of input ATM cells, so that existing line processing circuits or new line processing can be performed without circuit modification, circuit addition, etc. It can be connected to a circuit or the like.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 to FIG. 3 are block diagrams from the line processing unit to the ATM switch unit of the ATM exchange. This A
The TM exchange includes an ATM switch according to the ATM cell multiplexing circuit of the present invention.
A TM multiplexing unit 7 is provided. The serial data from the optical line is supplied to a line processing unit and converted into a full ATM cell. The output is provided to an ATM cell multiplexing unit 7 provided in accordance with the present invention to interface with an ATM cell processing unit 8 located at a subsequent stage in consideration of the number of lines, various line speeds, and bit widths.

[0011] The data obtained in this manner is stored in an ATM.
The data is supplied to the cell processing unit 8, and is output to the ATM switch unit 9 after various processing of the ATM cell.

FIG. 1 shows an example in which four 150 Mbps optical lines are accommodated.
The processing contents per line are as follows: optical data of 150 Mbps serial data is input, and 18.8 MHz × 8 bits × 5
A 3-byte ATM cell is configured and output. This A
Four TM cell lines are input to the ATM cell multiplexing unit 7 and
Performs line multiplexing processing, 18.8 MHz x 32 per line
An ATM cell of bits × 14 bytes is formed and output to an ATM cell processing unit 8 located at a subsequent stage.

FIG. 2 shows an example in which two 150 Mbps optical lines are accommodated.
The processing content per line is as follows: optical data of 150 Mbps is input, and 9.9 MHz × 16 bits × 2
A 7-byte ATM cell is configured and output. This A
Two TM cell lines are input to the ATM cell multiplexer 7 and
Performs line multiplexing processing, 18.8 MHz x 32 per line
An ATM cell of bits × 14 bytes is formed and output to an ATM cell processing unit 8 located at a subsequent stage.

FIG. 3 shows an example in which one line of a 600 Mbps optical line is accommodated.
The processing content per line is as follows: serial data of optical line 600 Mbps is input, and 18.8 MHz × 32 bits × 14
A byte ATM cell is configured and output. This AT
One M cell line is input to the ATM cell multiplexing unit 7 and outputs a through-cell ATM cell of 18.8 MHz × 32 bits × 14 bytes to the ATM cell processing unit 8 located at the subsequent stage without performing multiplexing processing. .

Next, an embodiment of the ATM cell multiplexing unit of the present invention will be described. FIG. 4 is a circuit diagram showing an embodiment of an ATM cell multiplexing unit according to the present invention. The ATM cell multiplexing unit 7 shown in FIG.
3 and the cell buffers 10 to 13 for storing
Serial / parallel conversion circuits 14 to 19 for adjusting the bit width of the TM cell to the output bit width, multiplexing circuits 20 and 21 for multiplexing data of the serial / parallel-converted ATM cells, and multiplexing by a select signal. A selection circuit 22 is provided for selecting how many ATM cells are multiplexed.

The ATM cell data 30 to 33 input from the line processing units 0 to 6 are stored in the cell buffers 10 to 13, and are used for switching clock speeds and transmitting empty cells when no cells are stored. Then, the ATM cell data 50-53 after the clock change is output, and the bit width conversion for adjusting the bit width of the ATM cell data 50-53 input by the serial / parallel conversion circuits 14-19 to the output bit width is performed. The multiplexing circuit 20 performs two-line multiplexing, and the multiplexing circuit 21 performs four-line multiplexing to output serial / parallel converted data 54 to 59 and multiplex the serial / parallel-converted ATM cell data 54 to 59. The selected cell multiplexed data 60 to 61 are output, and the selection circuit 22 multiplexes the ATM cell data multiplexed by the select signal 46. There outputs the output data 42 by selecting whether they are anything multiplexed.

According to the above processing, for example, when the input bit width is 8 bits, four lines are multiplexed and output with an output bit width of 32 bits according to the bit width of the input ATM cell, and then input. When the bit width is 16 bits, two lines are multiplexed and output with an output bit width of 32 bits, and when the input bit width is 32 bits, only one line is output with an output bit width of 32 bits. I do.

Therefore, various lines can be accommodated by the select signal 46 without being limited by the line speed and bit width of the input ATM cell.

Note that the line processing units 0 to 6 in FIGS.
Since the M cell processing unit 8 and the ATM switch unit 9 are not directly related to the present invention, their detailed configurations are omitted.

Next, the operation of the ATM cell multiplexing unit will be described. First, as shown in FIG. 1, when a line accommodates a line speed of 150 Mbps corresponding to OC3, one line
The operation when an ATM cell is input at 8.8 MHz × 8 bits × 53 words will be described with reference to the circuit configuration diagram of FIG. 4 and the timing diagrams of FIGS.

In FIG. 1, the input data of the ATM cell multiplexing section 7 is 32 bits, and 8 bits × 5 per line.
Since four lines of ATM cells of three words can be accommodated, the input synchronization signal 34, the input clock 38 and the input ATM cell data 30 of the line 1 are input to the line 1, and the input synchronization signal 35, the input clock 39 and line 2
The input ATM cell data 31 is input, and an input synchronization signal 36, an input clock 40, and an input A
The TM cell data 32 is input, and an input synchronization signal 37, an input clock 41 and ATM cell data 33 input to the line 4 are input to the line 4.

At this time, the select signal 46 performs the following operation by setting "00" in the diagram showing the operation content of the select signal shown in FIG.

Cell buffer 10 composed of FIFO
The ATM cell data 30 to 33 of the lines 1 to 4 are written into the cell buffer 13, respectively, and the cell buffer is synchronized with the output clock 44 and the synchronizing signal 62 selected from the select signal 46 by the cell synchronizing signal generator 23. From 10-13,
ATM cell data 50 to 53 of lines 1 to 4 are 8
It is read by bits × 53 words.

At this time, if one cell data is not stored in each of the cell buffers 10 to 13, an empty cell is generated and output to the ATM cell data 50 to 53.

The ATM cell data 50 to 53 read from the cell buffers 10 to 13 are converted into 8-bit to 32-bit serial / parallel conversion circuits 16 to 19 by converting the ATM cell data 50 to 53 of the lines 1 to 4 into 8 bits. × 53
The word is converted into 32 bits × 14 words and output as 8-bit → 32 serial / parallel converted data 56 to 59.

The 8-bit → 32 serial / parallel conversion data 56 to 59 are respectively converted into 4 cells → 1 cell multiplexing circuit 21
And an output side clock 44 and an output side synchronization signal 45
8 bits → 32 serial / parallel converted data 56 to 59 are sequentially multiplexed and output as 4-cell → 1 cell multiplexed data 61.

The 4-cell to 1-cell multiplexed data 61 is input to the selection circuit 22 and passed through the path selected by the select signal 46 to provide the output synchronization signal 43 and the output ATM cell data 42 with 18.8 MHz × 32 bits × 14 words. Are multiplexed and output at a line speed of 600 Mbps.

On the other hand, when an ATM cell is input at 9.9 MHz × 16 bits × 27 words per line when the line accommodates a line speed of 150 Mbps corresponding to OC3 as shown in FIG. And in accordance with the timing diagram of FIG.

At this time, the following operation is executed by setting the select signal 46 to "01" in the diagram showing the operation content of the select signal shown in FIG.

The input data of the ATM cell multiplexing unit 7 is 32 bits, and an AT of 16 bits × 27 words per line is used.
Since two M cells can be accommodated, the same input synchronization signals 34 and 35 are input to the line 1, the same input clocks 38 and 39 are input, and the input ATM cell data 30 and 31 are 16 bits wide. The same input synchronization signals 36 and 37 are input to the line 2, the same input clocks 40 and 41 are input, and the input ATM cell data 32 and 3 are input.
3 is input with a 16-bit width.

The cell buffer 10 composed of a FIFO,
AT of lines 1 and 2 for 11 and 12 and 13 respectively
M cell data 30, 31 and 32, 33 are written,
18. Double speed at 9.9 MHz input clock
The ATM cell data 50 of the lines 1 and 2 are output from the cell buffers 10, 11, 12 and 13 in synchronization with the 8 MHz output clock 44 and the synchronizing signal 62 selected from the select signal 46 by the cell synchronizing signal generator 23, respectively. , 51 and 5
2, 53 are read with 16 bits × 27 words.

At this time, the cell buffers 10, 11, and 12,
13 does not store cell data for one cell, an empty cell is generated and the ATM cell data 50,
Output to 51, 52 and 53.

ATM cell data 50, 51, 52, 53 read from cell buffers 10, 11, 12, 13
Is a 16-bit → 32-bit serial / parallel conversion circuit 14 and 15 which converts ATM cell data 50, 51, 52 and 53 of lines 1 and 2 from 16 bits × 27 words to 32 bits × 14 words, respectively, → Output to 32 serial / parallel conversion data 54 and 55.

The 16-bit → 32 serial / parallel conversion data 54 and 55 are respectively converted into 2 cells → 1 cell multiplexing circuit 2
0, the output clock 44 and the output synchronization signal 4
In synchronism with 5, the 16-bit → 32 serial / parallel converted data 54 to 55 are sequentially multiplexed and output as 2-cell → 1-cell multiplexed data 60.

The 2 cell → 1 cell multiplexed data 60 is input to the selection circuit 22, and the output synchronization signal 43 and the output ATM cell data 42 are 18.8 MHz × 32 bits × 14 words through the path selected by the select signal 46. Are multiplexed and output at a line speed of 600 Mbps.

Further, when the line accommodates a line speed of 600 Mbps corresponding to OC12 as shown in FIG. 3, the operation when an ATM cell is input at 18.8 MHz × 32 bits × 14 words per line is described in FIG. Is executed according to the timing chart of FIG.

At this time, the following operation is executed by setting the select signal 46 to "10" in the diagram showing the operation content of the select signal shown in FIG.

The input data of the ATM cell multiplexing unit 7 is 32 bits, and an AT of 32 bits × 14 words per line is used.
Since M cells can be accommodated for one line, the same input synchronization signals 34 to 37, the same input clocks 38 to 41 are input to the line 1, and the input ATM cell data 30 to
33 is input with a 32-bit width.

A cell buffer 10 composed of FIFO
13, the input ATM cell data 30 to 33 of the line 1 are written to the cell buffer 10, respectively, in synchronization with the output clock 44 and the synchronizing signal 62 selected from the select signal 46 by the cell synchronizing signal generator 23. From ~ 13,
ATM cell data 50 to 53 of line 1 are 32 bits x 1
Read in 4 words.

At this time, if cell data for one cell is not stored in each of the cell buffers 10 to 13,
An empty cell is generated and output to ATM cell data 50 to 53.

The ATM cell data 50 to 53 read from the cell buffers 10 to 13 are input to the selection circuit 22 and output to the output synchronizing signal 43 and the output ATM cell data 42 via the path selected by the select signal 46.
8.8 MHz x 32 bits x 14 word line speed 60
At 0 Mbps, the clock phase is changed and output.

In this embodiment, the ATM cell multiplexing unit is arranged at the subsequent stage of the line processing circuit. However, the ATM cell multiplexing unit is not limited to this position, but may be arranged at a position where ATM cells are to be multiplexed.

In this embodiment, the input data width is described as 32 bits. However, the input data width may be 128 bits so that four lines of OC12 having a line speed of 600 Mbps can be multiplexed. Further, the output data width is not limited to 32 bits.
It can be configured with a bit width most suitable for a TM switching system.

Further, in order to reduce power consumption, a selection circuit may be provided before the serial-to-parallel conversion circuit so that a path is selected by a selection signal and circuits other than the selected path are not operated. it can.

Next, another embodiment of the present invention will be described.

The basic configuration is as described above.
The input data of the TM cell multiplexing unit 7 is changed from 32 bits to 128
Line speed of 600 equivalent to OC12
18.8 MHz x 32 bits x 1 per line at Mbps
4 words are multiplexed into 4 lines and output line speed is 2.4Gbps
It is further devised so that it can be output with. FIG. 5 is a circuit diagram showing another embodiment of the ATM cell multiplexing circuit of the present invention.

In FIG. 5, line 1 receives input synchronization signals 34-37, input clocks 38-41 and line 1 input ATM cell data 30-33.
Input synchronization signals 34A-37A, input clocks 38A-4
1A and line 2 input ATM cell data 30A-33A
Are input to the line 3, and the input synchronization signals 34B to 37B
B, input clocks 38B-41B and line 3 input AT
M cell data 30B to 33B are input, and
Input synchronization signals 34C to 37C, input clocks 38C to 4
1C and line 4 input ATM cell data 30C-33C
Is entered.

Cell buffers 10 to 10 composed of FIFOs
13, 10A to 13A, 10B to 13B, 10C to 13
C, ATM cell data 3 for lines 1-4 respectively
0-33, 30A-33A, 30B-33B, 30C-
33C is written, and the cell buffers 10 to 13 and 10A to 1 are synchronized with the output clock 44 and the synchronizing signal 62 selected by the cell synchronizing signal generator 23 from the select signal 46.
From 3A, 10B to 13B, and 10C to 13C, ATM cell data 50 to 53 and 50A to 5 for lines 1 to 4, respectively.
32 bits for 3A, 50B to 53B and 50C to 53C
Read in 14 words.

At this time, the cell buffers 10 to 13, 10
When cell data for one cell is not stored in each of A to 13A, 10B to 13B, and 10C to 13C,
Generates empty cells and outputs ATM cell data 50 to 53, 50A
To 53A, 50B to 53B, and 50C to 53C.

ATM cell data 50-53, 50A-53A, 50B read from cell buffers 10-13.
To 53B, 50C to 53C are input to the 4-cell to 1-cell multiplexing circuit 2A, and are synchronized with the output clock 44 and the output synchronization signal 45, respectively.
The cells are multiplexed in the order of 50B to 53B and 50C to 53C, and are output as 4-cell to 1-cell multiplexed data 6A.

The 4-cell to 1-cell multiplexed data 6A is input to the selection circuit 22, and is multiplexed by 4 lines to the output synchronization signal 43 and the output ATM cell data 42 through the path selected by the select signal 46 to 75.2 MHz.times. It is output at a line speed of 2.4 Gbps of 32 bits × 14 words.

Accordingly, FIGS. 13 and 14 show timing charts of the operation of the ATM cell multiplexing section 7 for multiplexing the line at a line speed of 600 Mbps. That is, when input data is an ATM cell having a line speed of 600 Mbps, four lines are multiplexed, and output data is output at a line speed of 2.4 Gbps.
s.

As described above, in this embodiment, when input data is an ATM cell of 150 Mbps, 16 lines are multiplexed, and output data is transmitted at a line speed of 2.4 Gb.
ps, and the effect of improving the multiplexing efficiency is obtained.

Next, still another embodiment of the present invention will be described.

In each of the above embodiments, the line processing unit 0
6 are accommodated without being limited by the line speed and bit width of the input ATM cell.
The function and effect of accommodating ATM cells of various line speeds and bit widths can be obtained by simply using the interface function of the ATM cell data of various line speeds and bit widths as well as the interface with the line processing units 0 to 6. , Old A
It can be used as an interface with a TM system, an interface with a new ATM system, or an interface with an ATM system of another company.

FIG. 6 is a circuit diagram showing a further embodiment of the ATM cell multiplexing circuit according to the present invention. In this embodiment, when accommodating the old ATM system, the current ATM system is accommodated by multiplexing the ATM cells without any change.

Therefore, the select signal 46 is not limited by the line speed and bit width of the input ATM cell.
Thus, an operation of accommodating ATM cells of various line speeds and bit widths can be obtained by simply switching the mode, and the object of the present invention is achieved.

In this embodiment, the current AT
The ATM system input from the old ATM system is multiplexed and accommodated without any change in the M system. Therefore, any ATM system can be accommodated by a single development, so there is no need to develop each time. This has a synergistic effect that the development period, development cost and man-hour can be reduced.

[0059]

As described above, the ATM of the present invention is
Since the cell multiplexing circuit selects the input condition by the selection signal when inputting data converted into full ATM cells, the cell multiplexing circuit can input the data without being limited by the bit width and the line speed of the input ATM cell data. .

Therefore, the AT of various line speeds to be input
The M cells are multiplexed in the ATM cell multiplexing unit in accordance with the selection signal, and the same circuit speed and bit width A
A TM cell can be output.

According to the present invention, data can be input without being limited by the bit width and the line speed of the input ATM cell data. Therefore, the interface with the old ATM system, the interface with the new ATM system, and the A
It also has the effect that it can be used as an interface with the TM system.

[Brief description of the drawings]

FIG. 1 is a block diagram from a line processing unit to an ATM switch unit of an ATM exchange, showing an example in which four 150 Mbps optical lines are accommodated.

FIG. 2 is a block diagram showing an example of a case where two optical lines of 150 Mbps are accommodated from a line processing unit to an ATM switch unit of an ATM exchange;

FIG. 3 is a block diagram illustrating an example of a case where an optical line of 600 Mbps is accommodated for one line, from a line processing unit to an ATM switch unit of an ATM exchange;

FIG. 4 is a circuit diagram showing an embodiment of an ATM cell multiplexing circuit according to the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the ATM cell multiplexing circuit of the present invention.

FIG. 6 is a block diagram showing still another embodiment of the ATM cell multiplexing circuit of the present invention.

FIG. 7 is a diagram illustrating an operation content of a select signal.

FIG. 8 is a timing chart for explaining the operation of the embodiment shown in FIG. 4;

FIG. 9 is a timing chart for explaining the operation of the embodiment shown in FIG. 4;

FIG. 10 is a timing chart for explaining the operation of the embodiment shown in FIG. 4;

FIG. 11 is a timing chart for explaining the operation of the embodiment shown in FIG. 4;

FIG. 12 is a timing chart for explaining the operation of the embodiment shown in FIG. 4;

FIG. 13 is a timing chart for explaining the operation of the embodiment shown in FIG. 5;

FIG. 14 is a timing chart for explaining the operation of the embodiment shown in FIG. 5;

FIG. 15 is a block diagram showing a conventional cell multiplexing circuit.

[Explanation of symbols]

0-6 Line processing unit 7 ATM cell multiplexing unit 8 ATM cell processing unit 9 ATM switch unit 10-13, 10A-13A, 10B-13B, 10C
１３13C Cell buffer 14, 15 16 bit → 32 bit serial / parallel conversion circuit 16 回路 198 bit → 32 bit serial / parallel conversion circuit 20 2 cell → 1 cell multiplexing circuit 21,2A 4 cell → 1 cell multiplexing circuit 22 Selection circuit 23 Cell synchronization signal generator 2B 16 cells → 1 cell multiplexing circuit 30-33, 30A-33A, 30B-33B, 30C
~ 33C Input ATM cell data 34 ~ 37, 34A ~ 37A, 34B ~ 37B, 34C
~ 37C Input synchronization signal 38 ~ 41, 38A ~ 41A, 38B ~ 41B, 38C
To 41C input clock 42 output ATM cell data 43 output synchronization signal 44 output side clock 45 output side synchronization signal 46 select signal 50 to 53, 50A to 53A, 50B to 53B, 50C
５３53C ATM cell data 54,55 16-bit → 32-bit serial / parallel converted data 56-598 8 bit → 32-bit serial / parallel converted data 60 2-cell → 1-cell multiplexed data 61,6A 4-cell → 1-cell multiplexed data 62 Synchronization signal 6B 16 cells → 1 cell multiplexed data

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 12/56 H04L 12/28 H04J 3/04 H04J 3/22

Claims (3)

(57) [Claims] 1. A cell buffer for accumulating data of an input ATM cell and switching clock speeds, and a bit width of an ATM cell output from the cell buffer.
A serial-to-parallel conversion circuit that matches the output bit width, and a multiplexing circuit that multiplexes the data of the serial-to-parallel-converted ATM cells, are input without being limited by the line speed and bit width of the input ATM cells. An ATM cell multiplexing circuit for multiplexing ATM cells of various lines to output ATM cells having the same line speed and the same bit width to a subsequent circuit, wherein the serial / parallel conversion circuit comprises an 8-bit to 32-bit serial circuit. The multiplexing circuit comprises a parallel conversion circuit and a 16-bit → 32-bit serial / parallel conversion circuit, wherein the multiplexing circuit is a 2-cell → 1-cell multiplexing circuit and 4-cell → 1
If the input ATM cell has a bit width of 8 bits, it multiplexes 4 lines and outputs it with an output bit width of 32 bits, and if the input bit width is 16 bits, it multiplexes 2 lines. An ATM cell multiplexing circuit characterized in that an output bit width is 32 bits, and when the input bit width is 32 bits, only one line is output with an output bit width of 32 bits. 2. The ATM cell multiplexing circuit according to claim 1, wherein said cell buffer outputs an empty cell when no ATM cell data is stored. 3. An ATM switch comprising the ATM cell multiplexing circuit according to claim 1.