JP2876747B2 - Frame synchronization circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly, to a frame synchronization circuit for achieving frame synchronization of digital communication.

[Conventional technology]

In digital communication, a technique of frame synchronization for identifying the position of a frame is required.

FIG. 3 shows a frame configuration in an ISDN primary rate interface as an example of digital communication.

In the ISDN primary rate interface, one frame is composed of 193 bits. The first bit is called an F bit, and its role will be described later. The second bit to the 193rd bit are data, each of which is composed of 24 time slots of 8 bits.

One frame is transmitted and received at a cycle of 125 μs. A multi-frame is composed of 24 frames as one unit. Of the 24 F bits of the multiframe, the fourth,
Each F bit of the eighth, twelfth, sixteenth, twentieth, and twenty-fourth frames is a frame synchronization bit of “001011”. Also,
Each F bit of the second, sixth, tenth, fourteenth, eighteenth, and twenty-second frames is a CRC code (Cyclic Redundancy Check code) for monitoring errors on the interface and preventing pseudo-synchronization.
The F bit of the odd-numbered frame is called m bit, which is a bit for maintenance operation information.

Therefore, in the ISDN primary group interface, the synchronizing bit of "001011" is inserted one by one every 772 bits out of the 4632 bits, and it is necessary to detect this synchronizing bit to achieve frame synchronization.

As the frame synchronization method, a 1-bit shift method, a multipoint monitoring method, and the like are well known. However, the multipoint monitoring method is generally used because of its excellent recovery characteristics.

In the following, a conventional technique relating to a frame synchronization circuit for an ISDN primary group interface using a multipoint monitoring method will be described.

FIG. 4 is a block diagram showing an example of a conventional frame synchronization circuit.

In FIG. 4, a conventional frame synchronization circuit includes an AND circuit 1, a counter 2, a synchronization pattern generation circuit 3,
A shift register 4 and a match / mismatch determination circuit 5 are provided.

The AND circuit 1 is a gate that performs on / off control of a clock CK input to the counter 2.

The counter 2 is a counter that divides the frequency of the clock CK by 1/772.

The synchronization pattern generation circuit 3 generates a synchronization pattern in synchronization with the output of the counter 2.

The synchronization pattern generation circuit 3 can be configured, for example, as shown in FIG.

In FIG. 6, SR31 is a 6-bit shift register, and has output terminals T1 to T6 for each bit and preset terminals TP1 to TP6.

As an initial state, for example, preset terminals TP1 to TP6
Assuming that the synchronization pattern of “110010” is preset, the state of the shift register changes to “100101”, “110010”, “011001”,... In synchronization with the clock. A synchronization pattern can be obtained.

The shift register 4 is a 3860-bit shift register that receives the reception data D from the reception data input terminal TD and uses the reception clock CK from the reception clock terminal TCK as a clock.

 FIG. 5 shows the details of the shift register 4.

In FIG. 5, SR1 to SR5 are shift registers of 772 bits, respectively.

The coincidence / non-coincidence determination circuit 5 is a circuit for determining the coincidence / non-coincidence between the output of the shift register 4 and the output of the synchronous pattern generation circuit 3.

Next, the operation of the conventional frame synchronization circuit will be described.

In FIG. 4, the thick arrow indicates parallel data, and the number in the arrow indicates the bit length of the data.

Initially, it is assumed that the received data is out of synchronization.

The match / mismatch determination circuit 5 outputs an out-of-sync signal UL of the terminal TUL.
Is turned on, and the counter 2 is
A signal for turning off the reception clock CK supplied to the power supply.

Therefore, the counter 2 stops, and the synchronous pattern generation circuit 3 keeps outputting the same periodic pattern.

On the other hand, the shift register 4 sequentially shifts the received signal one bit at a time, and sequentially outputs the 6-bit parallel signals extracted from the intermediate taps every 772 bits to the match / mismatch determination circuit 5.
Send to

When the output of the shift register 4 and the output of the synchronization pattern generation circuit 3 match, the match / mismatch determination circuit 5 turns on the synchronization signal L at the terminal TL, turns off the out-of-sync signal UL, and turns on the AND circuit 1 to turn on the counter. Operate 2

The counter 2 outputs a clock to the synchronization pattern generation circuit 3 after counting the reception clock CK 772, and generates the next synchronization pattern. On the other hand, the shift register 4
Since the received signal shift is continued, the match / mismatch determination circuit 5
After the output of the shift register 4 and the output of the synchronous pattern generating circuit 3 match, the determination of the mismatch is stopped during the next 771 clocks.

Then, at the 772th clock, that is, at the timing when the output of the synchronization pattern generation circuit 3 changes to the next synchronization pattern, the determination of the mismatch is made again.

Hereinafter, the same operation is repeated while the frame synchronization is lost.

If it is determined that there is no match at the time of the match / mismatch determination in the synchronous state, the match / mismatch determination circuit 5
Turns off the synchronizing signal 3 and turns on the out-of-assimilation signal 4 and again outputs a signal to the AND circuit 1 to turn off the receiving clock CK supplied to the counter 2 to stop the change of the synchronizing pattern. The determination of match / mismatch is performed for each bit.

[Problems to be solved by the invention]

In the conventional frame synchronization circuit using the multipoint monitoring method, a shift register is used as a storage circuit that is essential for extracting a bit string periodically arranged in a received data string.

However, since the shift register has a relatively large number of transistors, the shift register has a disadvantage that the chip area is likely to increase when implementing an LSI.

In particular, in the case of the ISDN primary group interface, a shift register as large as 3860 bits is required, which has a disadvantage that a large chip area is required.

In addition, in order to avoid malfunction of the shift register, it is necessary to pay attention to minimizing the skew between clocks of clocks supplied to respective bits. However, in the case of a long bit shift register, it is necessary to minimize the skew between clocks. However, there is a disadvantage that the circuit design and the layout design become difficult.

[Means for solving the problem]

The frame synchronization circuit according to the present invention detects the synchronization pattern composed of frame synchronization bits periodically inserted into reception data constituting one multi-frame with a predetermined number of frames composed of a plurality of bits, thereby performing the reception. A frame synchronization circuit for generating the timing of the frame of data and the timing of the multi-frame; a random access memory for storing the received data for one multi-frame; and a synchronization pattern for storing the received data stored in the random access memory. A reception data read circuit that reads out at the same period as the synchronization pattern candidate data of the parallel data, a reception clock source that supplies a reception clock serving as a reference for the timing of the processing of the reception data, and controls input of the reception clock. Perform receive clock game A reception clock counter circuit that counts the reception clock in response to the activation of the clock signal and divides the frequency of the reception clock by 1 / the number of frame bits for one cycle of the synchronization pattern; A synchronization pattern generation circuit for generating a reception synchronization pattern having the same cycle as the synchronization pattern; and determining a match between the synchronization pattern candidate data output from the reception data reading circuit and the reception synchronization pattern, and responding to the match. And a coincidence determination circuit for outputting a synchronization signal, activating the reception clock gate signal, outputting an out-of-synchronization signal in response to the mismatch, and deactivating the reception clock gate signal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a frame synchronization circuit according to the present invention includes a random access memory 6, a An X address decoder 7,
Y address decoder 8 and serial / parallel converter 9
, An address register 10, a subtraction circuit 11, and a selector 12
And a counter 13.

The random access memory 6 is a memory for storing 4632 bits, that is, received data for one multi-frame.

The X address decoder 7 is an address decoder that generates an address of the lower 7 bits of the address.

The Y address decoder 8 is an address decoder that generates an upper 6-bit address of the address.

The serial / parallel converter 9 converts data output serially from the random access memory 6 into 6-bit parallel data.

The address register 10 is a register that stores an address of the random access memory 6.

The subtraction circuit 11 has a function of subtracting 772 from the address of the random access memory 6.

The selector 12 selects either the output of the subtraction circuit 11 or the output of the counter 13.

The counter 13 receives the reception clock C input from the terminal TCK.
This is a counter that divides K by 1/4632.

 Next, the operation of this embodiment will be described.

In FIG. 1, thick arrows indicate parallel data, and numbers in arrows indicate bit lengths of the data.

Initially, it is assumed that the received data is out of synchronization.

The match / mismatch determination circuit 5 outputs an out-of-sync signal UL of the terminal TUL.
Is turned on, the synchronization signal L at the terminal TL is turned off, and the reception clock CK supplied to the counter 2 for the AND circuit 1 is output.
Signal to turn off.

Therefore, the counter 2 stops, and the synchronization pattern generation circuit 3 keeps outputting the same synchronization pattern.

On the other hand, the random access memory 6 stores 4632 bits, that is, past received data corresponding to one multiframe.

When the receiving clock CK arrives at the terminal TCK, the counter 13
Is incremented by one, and the value is loaded into the address register 10 through the selector 12. Subsequently, the address of the random access memory 6 is switched, and the received data 7 of the terminal TD is written to a new address.

Next, the data is read and written to the serial / parallel converter 9.

Next, a value obtained by subtracting 772 from the value of the address register 10 is output by the subtraction circuit 11, and loaded into the address register 10 again through the selector 12.

The data at this address is read from the random access memory 6 and written to the serial / parallel converter 9.

When the same operation is repeated four more times, the serial-parallel converter 9 stores 6-bit data every 772 bits older than the current received data.

This data is sent to the match / mismatch determination circuit 5 before the next reception data arrives, and the determination is performed.

When the next received data and clock arrive, the counter
13 is counted up, and the same operation is repeated for the data at the next address.

Serial / parallel converter 9 and synchronous pattern generation circuit 3
Are matched, the match / mismatch determination circuit 5 turns on the synchronization signal L at the terminal TL, turns off the out-of-sync signal UL at the terminal TUL, turns on the AND circuit 1, and operates the counter 2.

On the other hand, since the serial / parallel converter 9 continues to output a pattern based on the latest received data, the match / mismatch determination circuit 5 outputs the next 771 clocks after the output of the serial / parallel converter 9 and the synchronization pattern generation circuit 3 match. The determination of a mismatch between the two is stopped.

Then, at the 772th clock, that is, at the timing when the output of the synchronization pattern generation circuit 3 changes to the next synchronization pattern, it is determined again whether or not the pattern matches.

Hereinafter, the same operation is repeated while the frame is synchronized.

Further, when it is determined that there is no match at the time of the match / mismatch determination in the synchronized state, the match / mismatch determination circuit 5
While turning off the synchronization signal L and turning on the out-of-synchronization signal UL,
Again, a signal to turn off the reception clock CK supplied to the counter 2 is output to the AND circuit 1 to stop the change of the synchronization pattern, and the determination of the match or non-match is performed for each bit.

In the frame synchronization circuit according to the present invention, a random access memory is used as a storage circuit that is essential for extracting a bit string periodically arranged in a received data string.

The random access memory has a maximum of only six 1-bit storage elements even if a static memory is used.
It can be composed of one transistor.

On the other hand, a shift register requires at least two inverters and two switches, that is, eight transistors.

Therefore, when using a random access memory,
A frame synchronization circuit can be configured with a smaller number of elements than in the case where a shift register is used.

Further, since the random access memory has a regular structure, the degree of integration per unit area can be improved.

As a result, a frame synchronization circuit can be configured with a much smaller chip area than when using a shift register.

In the case of the random access memory, unlike the case of the shift register, the data is effectively shifted by changing the address, so that it is not necessary to pay attention to the problem of the skew between clocks as in the case of the shift register.

 Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

The difference from the first embodiment is that the address register
The difference is that an address register 14 is used instead of 10, a subtraction circuit 15 is used instead of the subtraction circuit 11, and a counter 16 is used instead of the counter 13.

The address register 14 is divided into an address register (U) for storing upper 5 bits and an address register (L) for storing lower 8 bits.

The subtraction circuit 15 subtracts -4 from the upper 5 bits of address data.

The counter 16 is a counter that divides the reception clock CK input from the terminal TCK into 1/4632, as in the first embodiment. However, the counter 16 divides the reception clock CK by 1/193 and divides it by 1/24. The counter is configured separately.

 Other parts are the same as in the first embodiment.

The operation of this embodiment is basically the same as that of the first embodiment, but differs in the following points.

That is, since the counter for generating the address of the random access memory 6 is divided into the upper 5 bits and the lower 8 bits, the first embodiment uses -77.
Although the subtraction circuit of 2 is used, in the present embodiment, it is only necessary to subtract -4 from the upper 5 bits of the register. Therefore, there is an advantage that the circuit configuration is simplified.

〔The invention's effect〕

As described above, the present invention has an effect that a frame synchronization circuit can be configured with a smaller chip area by using a random access memory as a storage circuit for storing a received data string.

Further, unlike the shift register, there is an effect that it is not necessary to consider the influence of the skew between clocks.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing a second embodiment of the present invention, and FIG.
A diagram showing a frame configuration in the primary group interface,
FIG. 4 is a block diagram showing an example of a conventional frame synchronization circuit, FIG. 5 is a block diagram showing details of a shift register,
FIG. 6 is a block diagram showing an example of a synchronization pattern generation circuit. 1 AND circuit, 2 counter, 3 synchronous pattern generation circuit, 4 shift register, 5 match / mismatch determination circuit, 6 random access memory, 7 X address decoder, 8 Y address decoder, 9 serial-parallel converter, 10 address register, 11
… Subtraction circuit, 12… Selector, 13… Counter, 14…
Address register, 15: Subtraction circuit, 16: Counter.

Claims (3)

(57) [Claims] 1. A method for detecting a synchronization pattern consisting of frame synchronization bits periodically inserted into reception data constituting one multi-frame by a predetermined number of frames consisting of a plurality of bits, thereby detecting the synchronization pattern of the reception data. In a frame synchronization circuit for generating a frame timing and the multi-frame timing, a random access memory for storing the reception data for one multi-frame, and the reception data stored in the random access memory having the same period as the synchronization pattern A reception data read circuit for outputting as a synchronization pattern candidate data of the read parallel data; a reception clock source for supplying a reception clock serving as a reference for processing timing of the reception data; and a reception clock for controlling the input of the reception clock. For activation of gate signal A receiving clock counter circuit that counts the receiving clock in response and divides the frequency of the receiving clock counter circuit by one of the number of frame bits for one cycle of the synchronous pattern; and the synchronous pattern in synchronization with the output of the receiving clock counter circuit. A synchronization pattern generation circuit that generates a reception synchronization pattern having the same period; a synchronization pattern candidate data output from the reception data read circuit; and a determination of a match between the reception synchronization pattern and a synchronization signal output in response to the determination. A frame synchronization circuit for activating the reception clock gate signal, outputting an out-of-sync signal in response to the mismatch, and inactivating the reception clock gate signal. 2. A counter circuit for dividing the reception clock by 1 / bit of one multi-frame and outputting an address value of the random access memory; and an address for storing the address value. A register; an X address decoder for decoding a lower address of a predetermined first number of bits of the address value to generate an X address of the random access memory; and a second predetermined address of the address value. A Y address decoder that decodes an upper address of the number of bits to generate a Y address of the random access memory; and a frame for one cycle of the synchronization pattern for each cycle of the frame bits that form the synchronization pattern from the address value. A subtraction circuit for subtracting the number of bits; and Frame synchronization circuit according to claim 1, characterized in that it comprises a serial-parallel conversion circuit to transmit data by serial-parallel conversion to output the synchronization pattern candidate data. 3. A first counter for dividing the reception clock by a first division number and outputting a first address value of the random access memory, the reception data reading circuit comprising: a first multi-frame bit; A second counter that divides the number by a second frequency division number obtained by dividing the number by the first frequency division number and outputs a second address value of the random access memory; and stores the first address value. A first address register; a second address register that stores the second address value; and X that decodes a lower address that is the first address value and generates an X address of the random access memory.
An address decoder; and a Y decoder for decoding an upper address which is the second address value to generate a Y address of the random access memory.
An address decoder, and subtracting a value obtained by dividing the number of frame bits for one cycle of the synchronization pattern by the first frequency division number for each cycle of the frame bits forming the synchronization pattern from the first address value. 2. The frame synchronization circuit according to claim 1, further comprising: a subtraction circuit that performs the following processing; and a serial-parallel conversion circuit that performs serial-parallel conversion on the received data of the read serial data and outputs the synchronization pattern candidate data.