JPS6232854B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reception timing device used for receiving a digital code string such as PCM, and particularly to a reception timing device including a frame synchronization function.

In order to correctly decode or decipher a digital code string on the receiving side, it is necessary to know the time reference point in the digital code string. Therefore, by inserting a frame synchronization pattern on the transmitting side and monitoring this pattern on the receiving side, the time reference point is known, and the timing counters of the transmitting and receiving sections are always synchronized. Regarding this kind of frame synchronization technology, various proposals and theoretical analyzes of its characteristics have been actively conducted. Chapter 5 of ``PCM Communication Technology'' provides detailed examples of various methods and theoretical analysis results.

By the way, in conventional frame synchronization circuits, operations such as detection of frame synchronization patterns, synchronization protection by observing the temporal transition of detection results, and hunting to restore synchronization when synchronization is lost are performed using gate circuits and flip-flops for each individual function. This is done using a configuration using small-scale integrated circuits (SSI) and medium-scale integrated circuits (MSI) such as circuits. For this reason, the circuit scale of the reception timing device including such a frame synchronization function has become considerably large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital code reception timing device with a frame synchronization function that has a significantly simplified circuit configuration.

An object of the present invention is to provide a small and inexpensive digital code reception timing device that contributes to downsizing, economy, and cost reduction of digital communication devices.

Still another object of the present invention is to provide a highly flexible digital code reception timing device in which the characteristics of the frame synchronization function can be changed without changing the wiring.

The reception timing device of the present invention includes a reception timing counter that divides a clock pulse synchronized with a received digital code string by a frequency division ratio determined by the frame structure of the received digital code string, and a reception timing counter that divides a clock pulse synchronized with a received digital code string by a frequency division ratio determined by the frame structure of the received digital code string; a data delay circuit that parallelizes the frame synchronization pulses of the data delay circuit, a counting state signal indicating that the reception timing counter has reached a predetermined count value, and a signal obtained by delaying the output of the data delay circuit and the internal state signal by one bit. a read-only memory that outputs a new internal state signal and an increment control signal to the reception timing counter based on the input timing counter; It periodically monitors whether or not the frame phase of the reception timing counter matches the frame phase of the reception digital code string, and when an out-of-synchronization is detected, a register that feeds back the data to the read-only memory. The present invention is characterized in that synchronization is re-established by repeating the operation of sequentially shifting the frame phase from the reception timing using the step control signal. In this configuration, the read-only memory may have a two-stage configuration of first and second read-only memories.

Next, the present invention will be explained in detail with reference to the drawings. In the embodiment described below, a reception timing device for a 1.544 Mb/s (megabits/second) system PCM primary group will be described, but the effectiveness of the present invention is not limited to this.

FIG. 1 is a diagram showing a frame structure of 1.544 Mb/s system primary group PCM 24 channel multiplex communication. As shown in Figure 1, one frame (24 channels) consists of 193 bits (one frame synchronization pulse +
24×8 bits), of which F _i (i=
The 1 bit marked 1, 2, . . . , 12) is a frame synchronization pulse. As shown in FIG. 2, one multiframe is composed of 12 frames, and the 12-bit synchronization pulses from _F1 to _F12 are arranged in the pattern shown.

Frame synchronization determines the frame phase of the reception timing counter by detecting a frame synchronization pattern as shown in FIG. When it is in
It stably maintains the correct frame phase even if the synchronization pattern is received incorrectly due to a code error that occurs in the transmission path, and quickly responds when synchronization occurs and the frame phase of the reception timing counter deviates from the correct phase. It is necessary to restore the correct phase.

The part designated by reference numeral 1 in FIG. 2 shows an embodiment of the digital code reception timing device of the invention used for this purpose. A reception timing signal 1 synchronized with the reception digital code string from the reception digital code 10 and the clock signal 11.
2 is generated and supplied to the received signal processing section 2.
Note that in the following description, the term "terminal" or "signal" and "signal line" may be used to mean the same thing. The received signal processing unit 2 decodes or decodes the received digital code string, and in the 1.544 Mb/s PCM device, performs decoding into an analog signal and channel separation.

The digital code reception timing device 1 includes a reception timing counter 200, a parallelization circuit 300 for a received digital code string, a read-only memory 400, and a register 500.

The reception timing counter 200 divides the frequency of a clock pulse synchronized with the received digital code string using a frequency division ratio determined by the frame structure of the received digital code string. In the case of 1.544 Mb/s PCM, the clock is divided by 193. to create a 125μs (microsecond) frame, which is further divided by 12.
Create a 1.5ms (millisecond) multiframe. Symbols in the block of reception timing counter 200
CK is a clock input terminal, and symbol OUT is a frequency-divided output signal terminal, which generates a carry signal at the output terminal CY at one clock interval for every multi-frame count. Also, count enable terminal CE is “0”
When , the counting function is stopped regardless of the presence or absence of clock input.

Such a reception timing counter 200 is
As shown in FIG. 3, this can be easily realized using an integrated circuit (IC). Reference numbers 201, 202 and 2
The counter designated 03 is a 4-bit binary counter, and the gates designated 204 and 205 are two-input NAND gates. Signal line 19
When a clock pulse is applied through the signal line 11 while the counters 201 and 202 are at "1",
counts clock pulses. The count value becomes 255, and the carry output CY of the counter 202 becomes “1”.
Then, the load input terminals LD of the counters 201 and 201 become “0” via the NAND gate 204.
Since the next clock loads the value 63 through the preset input terminals A, B, C and D, the counters 201 and 202 operate as 193 frequency counters. The carry signal CY of the counter 202 is also given to the count enable terminal ENT of the counter 203, and when the counter 203 counts the carry signal CY of the counter 202 and the count reaches 15, it generates a carry signal CY on the signal line 13. A load pulse is sent to the counter 203 via the NAND gate 205, and the value 4 is loaded on the next clock. As a result, counter 20
3 operates as a divide-by-12 counter. Signal line 1
According to 3, the clock pulse is 12×193=
Every time the frequency is divided by 2316, only one bit "1" appears. When the signal line 19 is kept at “0”,
counter 201, regardless of the presence of a clock input.
202 and 203 do not change state and signal line 1
The value immediately before 9 becomes "0" is retained. The carry output CY of the reception timing counter 200 is applied to the address input terminal A9 of the memory 400 via the signal line 13, and the count enable input CE of the reception timing counter 200 is applied to the output of the memory 400 via the signal line 19. Given from terminal O ₀ .

The received digital code string parallelization circuit 300 is
The shift operation for the received digital code string inputted through the terminal DI is performed by the clock pulse inputted through the terminal CK, and the output terminals Q _A , Q
This allows the frame patterns to appear in parallel in _B , . . . , _QG . If the frame pulses are concentrated, it can be configured with a short shift register, but in the case of the frame configuration shown in Figure 1, the delay between the output terminals Q _A and Q _B is 193 bits, and the delay is in units of 193 bits. It can be configured using multiple delay circuits. In the frame configuration shown in FIG. 1, if frame pulses F ₁ to F ₇ are used as frame synchronization patterns, the output terminal Q of the parallelization circuit 300
Since frame pulses _{F 1} , F ₂ , ......, F ₇ can be made to occur in parallel in G , Q F , ......, _{Q A} once every multiframe, this pattern can be connected to the signal line 16. A synchronization check can be performed by applying the signal to the address input terminals A0, A1, .

In the read-only memory 400, the carry signal CY from the reception timing counter 200 is “1”.
Only when A9="1", the parallelization pattern of the received digital code string applied to address input terminals A6 to A0 is checked. In the synchronous state, when "1" is given to the address input terminal A9 of the memory 400 from the reception timing counter, the frame pulses F ₁ to F are sent to the signal line 16 unless a code error occurs on the frame pulse during transmission. ₇ appear in parallel, the operation of the reception timing device 1 is controlled. in this way,
When A9="1", address input terminals A6 to A
As long as the frame synchronization pattern is received at 0, the output O ₀ of the memory 400 is kept at 1, and the reception timing counter 200 does not stop incrementing. The operation continues with the frame phase matching the frame phase of the received digital code string. Even if the pattern applied to the address input terminals A6 to A0 at the time when the reception timing counter 200 indicates the frame synchronization position, that is, at the time when A9="1" is not a frame synchronization pattern, It is also possible that a pattern other than the frame synchronization pattern was created due to a code error. Therefore, when in synchronization, as long as a code pattern is received that is at a constant and relatively close Hamming distance (different number of bits when two code patterns are compared for each digit) from the frame synchronization pattern, that code By regarding the pattern as a frame synchronization pattern, it is possible to prevent an unnecessary synchronization pull-in operation from starting due to a simple code error. That is,
When A9="1", address input terminals A6 to A
Even if the code pattern given to O0 is not the frame synchronization pattern itself, if it is at a Hamming distance close to the frame synchronization pattern, the output _O0 of the memory 400 is kept at "1" and the synchronization is restored. No operations are performed.

Address input terminal A6 when A9="1"
If the code pattern of A0 is not within the allowable Hamming distance from the frame synchronization pattern, there is a high possibility that synchronization will be lost, so the output of the memory 400 is
Set _O1 to "1" to indicate that the machine is on alert.
The output _O1 is applied to the register 500 via the signal line 18, and is fed back to the address input terminal A7 of the read-only memory 400 via the signal line 15 after being delayed by 1 bit in the register 500.
If it is further determined that the code pattern of the address input terminals A6 to A0 is not within the permissible Hamming distance from the frame synchronization pattern in the state of A7="1" and A9="1", it is determined that synchronization has occurred. to set the output O ₂ to “1”. The output _O2 indicates a flag for distinguishing between a synchronized state and an out-of-synchronized state, and is fed back to the address input terminal A8 via the signal line 17, the register 500, and the signal line 14. A9=
In the state of "1" and when O ₂ = "1", the output O ₀ is set to "0", and the reception timing counter 200 is stopped from incrementing. Therefore, address input terminal A9 remains at "1" at the next clock instant. Therefore, the synchronization pattern continues to be checked. In such an out-of-synchronization state, that is, in the state where A8="1", the memory 40
0 determines that only the code pattern applied to address input terminals A6 to A0 that is a frame synchronization pattern itself is a frame synchronization pattern. That is,
The allowable Hamming distance for determining a frame synchronization pattern is narrowed to 0. If the frame synchronization pattern does not appear at the address input terminals A6 to A0 in this state, O ₀ = “0”, O ₁ = “1”, and O ₂ = “1” are held as they are, and they are reset again at the next clock time. Repeat the same operation. If a frame synchronization pattern occurs at the address input terminals A6 to A0, the output _O0 is returned to "1" and the counting operation of the reception timing counter is restarted, and at the same time, the output _O1 is returned to "1". Even if the frame phases of the received digital code string and the received timing counter do not match, a code pattern that is equal to the frame synchronization pattern may be generated by a stochastic combination of information pulses, so the output _O2 is still "1". will be kept as is. As a result of restarting the counting operation of the reception timing counter, A9 becomes "0", and no synchronization check is performed until A9="1" again after one multiframe.

Next, when A9 = "1", if it is confirmed that the code pattern of address input terminals A6 to A0 is a frame synchronization pattern, it is assumed that correct synchronization has been re-established, and the output _O2 is set to "0". Return to However, if a code pattern other than the frame synchronization pattern is received, the memory 400
The outputs O ₀ , O ₁ , O ₂ are “1”, “1”,
It is set to "0" and the search for a frame synchronization pattern is continued again.

By repeating such operations, it is possible to finally match the frame phases of the received digital code string and the reception timing counter.

FIG. 4 is a flowchart systematically illustrating the above-described operation, from which output states for all combinations of addresses in the read-only memory 400 can be programmed. In FIG. 4, D _H indicates the Hamming distance between the code pattern input to address input terminals A6 to A0 and the frame synchronization pattern, and D _H N indicates that this Hamming distance is N bits or less.

By the way, if the number M of bits of the frame synchronization pattern to be monitored in parallel is large enough, the allowable Hamming distance N
If is sufficiently large, when a code pattern exceeding the allowable Hamming distance N is detected at the time when A9 = "1", it is more likely to be considered that synchronization has actually occurred than to be caused by a code error. I can judge. In this case, the process of setting the output O ₁ to "1" and checking the synchronization pattern again may be skipped, and the output O ₂ may be set to "1" all at once to determine that the synchronization is out of synchronization. In this case, the internal state control signal requires only one bit for identifying the synchronized state/out-of-synchronization state.

As described above in detail, the digital code reception timing device according to the present invention can realize a frame synchronization function by simply adding a small number of ICs to the reception timing counter, and can reduce the size and size of the reception timing device. It greatly contributes to economicization. In fact, both the read-only memory 400 and the register 500 are each a single chip IC (integrated circuit).
Since it can be realized using a conventional receiver timing device, it is possible to significantly reduce the number of IC chips compared to conventional receive timing devices. In addition, the read-only memory 400 is commercially available.
PROM (programmable read-only memory),
Each register can use a D type flip-flop.

By the way, when the number of bits of a frame synchronization pattern to be monitored in parallel at one time is large, the memory size of the read-only memory 400 becomes large.

FIG. 5 shows a configuration for reducing memory size in such a case. FIG. 5 shows only the parts that are different from the configuration shown in FIG. 2, and the read-only memory 400 in FIG. 2 has a different configuration in FIG. The signals generated on signal lines 13 to 19 are the second
Equivalent to that for the configuration shown. In FIG. 5, reference numeral 501 indicates a first read-only memory;
Reference numeral 502 is a second read-only memory. In the first read-only memory 501, signal line 1
6 to address input terminals B0, B1, . . .
..., B6, and outputs "1" to the signal line 161 via the output terminal P1 at the time of detection. At the same time, a frame synchronization pattern and a code pattern within a certain Hamming distance from the frame synchronization pattern are detected, and upon detection, "1" is output to the signal line 162 via the output terminal P0. Therefore, the signal line 161
When is "1", the signal line 162 is always "1", but the signal line 162 has more chances of being "1".

In the second read-only memory 502, in the synchronized state (C3="0"), when C4="1", the second read-only memory 502 monitors whether or not there is "1" at the input C0 via the signal line 162, and synchronizes. In the off state (C3="1"), it is monitored via the signal line 161 whether or not there is "1" at the input C1.

FIG. 6 is a flowchart systematically showing this operation. First and second read-only memories 50
The program of No. 1,502 can be easily performed from the above explanation and the flowchart of FIG.

When the frame synchronization pattern is not one type but a plurality of patterns are switched and used at regular intervals, the first read-only memory 501 stores two types of frames within Hamming distances of 0 and N, respectively. It is also possible to perform pattern detection using the following criteria, and selectively extract one set of a plurality of sets of detection results temporally using a frame timing signal from a reception timing counter. This temporal selection extraction function can be included in the second read-only memory 502 or can be configured using a selector.

[Brief explanation of the drawing]

1 and 2 are diagrams showing the frame format of a 1.544 Mb/s primary group PCM signal for explaining the frame synchronization circuit of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram showing a specific configuration of the reception timing counter, FIG. 4 is a diagram showing a flowchart for determining the correspondence between input and output codes of the read-only memory in the embodiment of FIG. 2, and FIG. A diagram showing a modification of the embodiment of FIG. 2, and FIG. 6 are a flowchart showing the correspondence between input and output codes of the second read-only memory shown in FIG. In FIG. 2, reference numerals 200...reception timing counter, 300...data delay circuit, 4
00...Read-only memory, 500...Register. Also, in FIG. 5, reference numerals 501 and 502 . . . first and second read-only memories.

Claims (1)

[Scope of Claims] 1. A reception timing counter that divides a clock pulse synchronized with a received digital code string by a frequency division ratio determined by the frame structure of the received digital code string; a data delay circuit that parallelizes frame synchronization pulses; and a counting state signal in which state transition information representing a state transition of synchronization pull-in is written in advance and indicating that the reception timing counter has reached a predetermined count value. a read-only memory that outputs state transition information of a state to be transitioned to the next time and an increment control signal to the reception timing counter using the output of the data delay circuit and the state transition information of the previous time as an address; 1. A digital code reception timing device comprising: a register that delays the next state transition information read from the memory by one bit to create the previous state transition information. 2. In the digital code reception timing device according to claim 1, the read-only memory is constituted by first and second read-only memories, and the first read-only memory includes the data delay circuit. Parallel output signals are input to output a synchronization pattern detection output, a synchronization pattern, and a detection output of a code pattern within a certain predetermined Hamming distance from the synchronization pattern, and the second read-only memory stores the above-mentioned data. A digital code reception timing device, characterized in that the output of the first read-only memory, the counting state signal, and the previous state transition information are inputted, and the next time state transition information is outputted.