JPH02288741A - Frame pull-in circuit - Google Patents

Abstract

PURPOSE:To attain acquisition of synchronism at an input with a few frames by adopting such as constitution of the circuit that the arrangement of a prescribed number of frame synchronizing bits differs in all parts as the frame synchronization bit. CONSTITUTION:A frame synchronizing bit inputted serially is fetched one by one bit according to a reference clock in a serial/parallel conversion section 11 and converted into a prescribed number of parallel signals while being shifted. Moreover, a parallel signal for a prescribed number of arrangement stored in advance is outputted by using the arrangement of the parallel signals of a prescribed number inputted from the said serial/parallel conversion section 11 as an address in a memory section 13. The said output is latched by a flip- flop circuit 14 and outputted according to a reference clock. The output from the said serial/parallel conversion section 11 or the flip-flop 14 is selected depending whether or not the synchronization is taken and inputted to the memory section 13 by the said operation.

Description

[Detailed Description of the Invention] [Summary] Regarding the low-speed frame synchronization pull-in method in a time division multiplexer, the synchronization pull-in time can be reduced by considering the arrangement of the X50 synchronization pattern and enabling synchronization pull-in with input of a small number of frames. For the purpose of providing a shortened frame synchronization pull-in circuit, using a frame synchronization bit pattern in which the arrangement of a predetermined number of frame synchronization bits is different in all parts, the frame synchronization bits manually input in series are used as a reference clock. a serial/parallel converter that captures and shifts one bit at a time and converts it into a predetermined number of parallel signals; a memory section that outputs a predetermined number of parallel signals; and a flip-flop circuit that temporarily holds the output of the memory section and outputs it according to the reference clock. and a selection section that selects the output of the flip-flop circuit and inputs the selected output to the memory section.

[Industrial application field]

The present invention relates to a low-speed frame synchronization pull-in method in a time division multiplexer.

An example of a frame structure in multiplexed transmission is shown in FIG. 6. (a) shows one time slot of a high-speed frame;
b) shows a multi-time slot in which an arbitrary number of frames (20 in the figure) are taken out from the high-speed frame, and (C) shows the channel capacity by speed.
This is an example. In addition, F is a frame synchronization bit, D1 to D6 are information bits, S is a status bit, and A is a bus status bit (l l 11. when abnormal.
'), CI is the channel number.

Here, high-speed frame synchronization is performed by detecting and holding the frame leading position W (frame synchronization position) of the frame configuration in order to correctly separate the time-division multiplexed pulse modulation signal. Detection of a frame synchronization position is generally performed by detecting whether a frame synchronization code in a frame structure appears at a frame repetition period.

In addition, low-speed synchronization is performed by extracting the second arbitrary frame during the high-speed frame synchronization and treating the extracted frames as one multiframe by looking at the pattern of synchronization bits located at the beginning of each frame. This low-speed synchronization is necessary when a terminal device reads a designated frame (such as a channel as shown in FIG. 6). recent years,
As the appearance pattern (synchronization pattern) of low-speed synchronization code,
For example, there is the X50 frame synchronization pattern recommended by Eva CCITT. This pattern is shown in the first bit of each frame of the multi-time slot in Figure 4 (AI
The pattern is IOloolooOOIOIOllo). This pattern is constructed so that no similar pattern exists when looking at consecutive 5 bits.

(Prior Art) Fig. 5 shows an example of the configuration of a conventional low-speed synchronous pull-in circuit.In the figure, 41 is a serial/parallel (S/P) conversion circuit;
42 is a comparison section, 43 is a counter section that operates in 20 cycles,
44 is a memory section in which the X50 synchronization patterns are sequentially stored. The case where the frame leading bit of a multi-time slot has an X50 synchronization pattern as shown in FIG. 4 will be described below.

Conventionally, as an initial operation, a signal in which the frame synchronization bits of the X50 synchronization pattern are serial is input to the serial/parallel conversion section 41. The frame synchronization bits can be retrieved simply by reading out the first bit for each extracted frame, and this can be done easily if the high-speed synchronization is achieved. The S/P converter 41 shifts the input signal in accordance with the reference clock and outputs it as a parallel signal in 5-bit increments in accordance with the reference clock.

The reference clock is a clock synchronized with the input of the one frame. The output is input to the comparison section 42. The comparator 42 holds the last 5-bit pattern (01110) of the x50 synchronization pattern, and detects that the pattern matches the input cover pattern. - When a match is detected, a detection signal is input to the counter 43. Upon receiving the detection signal, the counter 43 starts counting according to the clock and outputs the counter value at that time to the memory section 45. The counter section 44 outputs a reset signal when the counter value is 20, and is reset by a logical sum with the detection signal of the comparison section 42 and starts counting again.

The memory unit 45 sequentially outputs the x5o synchronization pattern bit by bit according to the counter value. By comparing the output with frame bits similar to those input to the S/P converter 41, a match or non-defeat is detected. When coincidence is confirmed a predetermined number of times (backward protection), it is determined that the synchronization state is established, and the counter value is constantly compared with the synchronization pattern based on the output signal from the memory section 45. Thereafter, when a predetermined percentage of out-of-synchronization is detected (forward protection), the same operation as the initial operation is performed.

[Problem to be solved by the invention]

In the case of the method shown in the prior art, the comparing section 42
In order to detect the last 5 bits of the X50 synchronization pattern in
In the worst case, the number of bits is 20 (if the last 5 bits are input from the first frame), that is, the number of input frames is 20 frames,
In other words, it is equivalent to l multi-frames. This has caused a problem in that it takes a very long time to pull in the synchronization even if the time for the rearward protection is taken into consideration.

In the present invention, by considering the arrangement of the X50 synchronization pattern and making it possible to pull in synchronization with input of a small number of frames,
An object of the present invention is to provide a frame synchronization pull-in circuit that reduces synchronization pull-in time.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the synchronous pull-in circuit according to the present invention. In the figure, 11 is an S/P conversion section, 12 is a selection section, 13 is a memory section, and 14 is a flip-flop (FF) circuit.

In order to achieve the above object, the present invention uses a frame synchronization bit pattern in which a predetermined number of frame synchronization bits are arranged differently in all parts.

First, in the serial/parallel converter 11, the serially inputted frame synchronization bits are taken in one bit at a time according to the reference clock, and are converted into a predetermined number of parallel signals while being shifted. Furthermore, in the memory section 13,
Using the array of a predetermined number of parallel signals inputted from the serial/parallel converter 11 as an address, a predetermined number of parallel signals in a pre-stored array is output. The output is held at one end by the flip-flop circuit 14 and output in accordance with the reference clock.

Through the above operation, the outputs of the serial/parallel converter 11 and the flip-flop 14 are selected and input to the memory unit 13 depending on whether synchronization is achieved or not.

[Effect]

By using the above means, a predetermined number of parallel signals input in the memory section 13 are used as addresses to output a predetermined number of parallel signals, that is, a synchronization pattern, in an arbitrary arrangement stored in the memory. In other words, a synchronization pattern is detected when 5 bits are input, and then synchronization is determined by several synchronization detections due to backward protection. Therefore, synchronization can be achieved in a time corresponding to the number of incoming collision protection stages of 5 frames, and synchronization can be achieved in a short time.

〔Example 〕

A configuration diagram of an embodiment of the present invention is shown in FIG. In this embodiment, the output of the S/P converter 11 is 5 bits, and a shift register is configured with four FF circuits.

In addition, the memory section 13 uses a ROM in this embodiment, and the R
Output signals corresponding to addresses are stored in the OM as shown in FIG. However, the figure does not show the pattern of a 5-bit array expressed in hexadecimal. That is, for example, if the input to the memory unit 13 is (00001,1
01 in hexadecimal), the output uses this as the address (
00010° (02) in hexadecimal. However, in the above arrangement, the outputs of each section are arranged in the order of 5.4, 3, and 2.1. Also, the output numbers of each part on the drawing are 1, 2, 3゜4.5
are assumed to correspond to each other.

Embodiments will be described in detail below with reference to the drawings. In this embodiment, a case will be explained in which the predetermined number mentioned in the above means is 5 and an X50 synchronization pattern is used as the frame synchronization pattern.

The arrangement of adjacent 5 bits of the X50 synchronization pattern is expressed in hexadecimal as shown in FIG. 43(a). As you can see from this, the arrays of 5 bits that meet next to each other are all different. The present invention utilizes this.

First, the one-term pull-in in the initial operation will be explained.

At the same time that an arbitrary frame is captured from the high-speed frame, the first bit of the frame is read and S/
The signal is input to the P converter 11.

The S/P converter 11 takes in the input serial synchronous bit signal while shifting it bit by bit in accordance with the reference clock CLK. Further, in accordance with the reference clock CLK, the input 1 pip) (S/P conversion section output 1) and each FF circuit output (S/P conversion section outputs 2 to 5) are transmitted to the selection section 12 as parallel signals.

(For example, when All0I is output, the next shift is 11010, then 10100... (However, the order is shown in the order of outputs of each section 5, 4, 3, 2.1.)) S/P conversion section 11 Since the output of RO is not synchronized in the initial operation, it passes through the selection section 12 and is output from RO.
Input to M13. The ROM 13 uses the input parallel signal as an address to detect and output the corresponding 5-bit data.

Here, regarding the relationship between address and output, if the address is All0I, the output is 11010, and the address is 11.
．． 11, the output is 10100... and so on.
As shown in the figure, it is configured to output a pattern that is one phase behind the address pattern in the X50 frame synchronization pattern.

In this way, the parallel signal output from ROM13 is FF at one end.
The signal is input to the circuit 14 and output after l frames. The signal at the final stage of the output is sent to the synchronous bit comparison circuit 15 (here EX
-OR circuit), the signal a is compared with a signal similar to the signal a input to the S/P converter 11. Then, the output from the synchronization bit comparator 15 matches the synchronization protection circuit 16.
Input the mismatch signal e. When the synchronization protection circuit 16 continuously detects the match signal e from the synchronization bit comparator 15 a predetermined number of times, it considers the synchronization pull-in to be completed.

In other words, this is a means of rear protection.

When the synchronization protection circuit 16 considers that the synchronization pull-in is completed, it notifies the selection means of the switching signal f. According to the said notification, R.O.
The input to M13 is switched to the input from the FF circuit 14. Therefore, the selection section 12, ROM 13, and FF circuit 14 form one closed loop. By doing this, even if the pattern of frame synchronization bits is reversed due to a bit error, no phase shift of the X50 synchronization pattern will occur, and loss of synchronization due to a single bit error is prevented.

The above is the synchronous pull-in of the initial operation. The subsequent operation will be explained below. After synchronization is achieved by the above operation,
The synchronization pattern comparison circuit 15 sends a mismatch signal to the synchronization protection circuit 16 at a predetermined rate (for example, the EX-OR circuit 1
If the output signal e of 5 is input with 6 or more mismatches detected out of 10), the synchronization protection circuit 16 considers it to be out of synchronization,
A switching signal f is transmitted to the selection unit 12, and upon receiving the switching signal f, the selection unit 12 changes the input to the ROM 13 from the FF circuit 14 to the S/
The P converter 11 is switched over and synchronization pull-in is performed again in the same manner as the initial operation. In this case, the S/P converter 11
When the error bits inside have been output, the EX-O
A coincidence signal is detected from the R circuit 15, and it is determined that synchronization occurs after backward protection.

The operation of the embodiment has been described above, and the embodiment will be explained in more detail by specifically setting the signals below. A specific signal is shown in FIG. a is the synchronization bit of the serial signal, CLK
is the reference clock, b is each output of the S/P conversion section 11, C is each output of the memory section 13, d is each output of the FF circuit, e is E
The output of the X-OR circuit 15 and f indicate the output of the protection circuit 16. In this example, a case is taken where the input is just from the first frame of a multi-frame. S/P as shown
It takes five reference clocks to output five synchronization bits from the converter 11. And S/P
The output of the converter 11 is used as an address, and a corresponding parallel signal C is output. In the FF circuit 14, the output C of the memory section 13 is held for one clock, and is output with a phase delay of one clock from the output C of the memory section 13. By doing so, the phases of the signals to be compared in the EX-OR circuit 15 are adjusted. When the frame synchronization bit is normal, the output of the EX-OR circuit 15 is compared with the output 1 of the graphic signal FF circuit 14, and a match signal e is output. After that, when a match signal is output continuously, the protection circuit 1
6 outputs a switching signal f to the selection section 12. In FIG. 4, the rear protection is shown as three stages.

The present invention has been described above according to the embodiments. In the embodiments, the X'50 synchronization pattern has been explained.
The present invention is effective for a synchronization pattern in which a predetermined number of arrays similar to the V.50 synchronization pattern all have different configurations.

〔Effect of the invention 〕

According to the present invention, the present invention considers a synchronization pattern in which a predetermined number of arrays are all different configurations, such as the X50 synchronization pattern array, and enables synchronization pull-in with input of a small number of frames, thereby reducing the synchronization pull-in time. This makes it possible to provide a frame synchronization pull-in circuit that shortens the time required.

[Brief explanation of drawings]

Fig. 1 shows the principle configuration of the present invention, Fig. 2 shows an embodiment of the invention, Fig. 3 shows an address-data comparison table, Fig. 4 shows a specific signal example, and Fig. 5 shows the conventional configuration. Figure 6 is an example of a frame configuration diagram. In the figure, 11, 12, 13, 14...S/P conversion section...selection section...memory section...FF circuit frame number 1234567 g'/10 H2B +4151
41'l +81'l 2a 1234 Zorro ROM〒data (b) Address data number of 4 slow frames

Claims (1)

[Scope of Claims] Using a frame synchronization bit pattern configured such that the arrangement of a predetermined number of frame synchronization bits is different in all parts, the frame synchronization bits input in series are captured one bit at a time according to a reference clock, A serial/parallel converter (11) converts the signal into a predetermined number of parallel signals while shifting
), a memory section (13) that outputs a predetermined number of parallel signals in a pre-stored array using the predetermined number of parallel signal arrays of the serial/parallel conversion section (11) as addresses; A flip-flop circuit (13) holds one end of the output and outputs it according to the reference clock.
4), and the serial/parallel converter (11) and the flip-flop circuit (1) depending on whether they are synchronized or not.
4) A synchronous pull-in circuit characterized in that it has a selection section (12) for selecting an output from the output terminal 4) and inputting the selected output to the memory section (13).