KR100221307B1 - Apparatus for generating an external e1 data in a synchronous transfer mode - Google Patents

Abstract

The present invention relates to an external E1 data generating device synchronized with a system clock in a synchronous transmission device.

The circuit according to the present invention includes a clock supply unit 10 for extracting a clock from an optical system and E1 data, and a system internal clock generator for receiving a clock from the clock supply unit 10 and generating a system clock required for a local system. 4) a reference clock selector 20 for selecting a reference clock according to a reference clock selection signal among clocks output from the clock supply unit 10, an oscillator 30 oscillating a predetermined clock frequency, and selecting the reference clock The phase synchronizer 40 and the phase synchronizer 40 which generate an E1 frame signal and an E1 clock synchronized with the reference clock by receiving the reference clock output from the unit 20 and the clock generated by the oscillator 30. E1 framer 50 for generating unipolar E1 data using the output as an input, and E1 data output from the E1 framer 50 and E1 clock output from the phase synchronizer 40, and receive unipolar E1. day And a line coding it consists of a connection line E1 50 to be converted to suit the polar outputs the E1 TIP (TIP) and E1 ring (RING), may generate an external E1 data in synchronization with the system clock.

Description

External E1 data generator in synchronous transfer mode

The present invention relates to a technique for synchronizing clocks between nodes in a synchronous transmission device having a plurality of nodes, in particular a first node for synchronizing a system clock of another node with a system clock generated at the first node. The present invention relates to a device for generating external E1 data synchronized with a system clock.

In general, in a communication network consisting of digital all-electronic exchanges, the clocks of all exchanges are synchronized with the Korean Standard Clock (KRF) provided by the Korea Standards Institute in Daejeon. It is. In other words, the main oscillator of high stability is placed in the master station, and this clock is distributed to each station via the transmission line. However, when the clock source and its roots fail, each station receives an unstable clock signal, so almost all systems have duplicated synchronous clock source signals. Thus, when one clock source fails, the clock signal is input from the other clock source to operate.

In addition, each station receives clocks from the optical path as well as the master station. In the worst case, all of these clock sources may fail. To this end, each station is equipped with a free-running function, so that when the unstable clock is applied, the oscillator can oscillate in its own frequency to maintain the network.

In such a synchronous digital transmitter, the E1 method of line code method is HDB3 (High Density Bipolar) method, which makes positive and negative marks alternately every time binary 1 occurs, and the maximum number of binary 0s that occurs continuously is 3 Limited to. Thus, when n + 1 zeros occur, the n + 1th zero is replaced by a mark called Violation, and the violation mark always has the same polarity as the mark of the previous logic 1, so that the mark is not normal data. Tells. In addition, if violations occur continuously, the polarity of the violations is monitored, and if a violation of the same polarity occurs, a double violation is made. The first violation occurs at the first zero of the n + 1 zeros and has the opposite polarity as the previous mark, and the second violation has the same polarity as the previous mark at the n + 1 zero position. Therefore, even when the binary signal has a long matrix of zeros, timing information can be obtained.

In the related art, as illustrated in FIG. 1, an externally input E1 data (the bits of this frame are all '1' and hereinafter referred to as Framed all '1') is line coded by the HDB3 method to extract a clock. Immediately, the input data is looped to generate external E1 data.

Referring to FIG. 1, the external sync clock input unit 1 receives the E1 data from an upper system or a synchronization source, extracts a clock, and synchronizes the external sync clock output unit 3 with the sync clock selector 2. The clock is provided to the internal clock generator 4 of the system. The system internal clock generator 4 receives a clock to generate a system clock required for a local system. At this time, if the clock selector 2 selects an externally input clock and uses the clock synchronized with the external clock, the E1 data generated by the external sync clock output unit 3 and the system clock are synchronized.

However, if the synchronous clock selector 2 uses a clock synchronized with another clock source, the external E1 data and the system clock use the respective clock sources, so that the externally generated E1 data and the system clock are not synchronized. .

That is, when the dotted line in the synchronous clock selector 2 connected to the system internal clock generator 4 and the external synchronous clock output unit 3 is a switch, the system internal clock generator 4 turns off the switch. When the external clock is interrupted and the clock is input from the optical system or the clock is generated by a free running operation within the external system, the external sync clock output unit 3 still receives the external sync clock through the sync clock selector 2. Since the clock is input from the input unit 1, there is a problem that the synchronization between the E1 data output to the outside and the system clock is not matched.

Accordingly, an object of the present invention is to provide an apparatus for generating external E1 data synchronized with a system clock.

The circuit of the present invention for achieving the above object is a clock supply unit for extracting a clock from the optical system and the E1 data, a system internal clock generation unit for receiving a clock from the clock supply unit to generate a system clock required for the local system, A reference clock selection unit for selecting a reference clock according to a reference clock selection signal among the clocks output by the clock supply unit, an oscillator oscillating a predetermined clock frequency, a reference clock output by the reference clock selection unit, and a clock generated by the oscillator Receives an E1 frame signal synchronized with a reference clock and a phase synchronizer for generating an E1 clock, and receives the E1 data output from the E1 framer and the E1 clock output from the phase synchronizer and line-codes the unipolar E1 data. Consisting of an E1 line connection that converts to polarity and outputs an E1 tip and an E1 ring. It features.

1 is a block diagram illustrating a process in which clocks are transmitted hierarchically from a clock source;

2 is a block diagram illustrating an external E1 data generator according to the present invention.

＊ Description of symbols according to the main parts of the drawings

4: Internal clock generating unit 10: Clock supply unit

11: optical clock receiver A 12: optical clock receiver B

13: External synchronization E1 clock input unit 14: Clock regeneration unit

20: reference clock selector 30: oscillator

40: phase synchronizer 50: E1 framer

60: E1 line connection

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an external E1 data generator according to the present invention.

As shown in FIG. 2, the E1 data generator includes a clock supply unit 10, a system internal clock generator 4, a reference clock selector 20, an oscillator 30, a phase synchronizer 40, and an E1 framer 50. ) And an E1 line connecting portion 60.

In addition, the clock supply unit 10 includes an optical clock receiver A 11, an optical clock receiver B 12, an external synchronous E1 clock input unit 13, and a clock regenerating unit 14. Provide a clock.

The reference clock selector 20 receives the first received 8KHz through the optical clock receiver A11, the second received 8KHz and the E1 data through the optical clock receiver B12, and receives the external synchronization E1 clock input unit 13. Reference clock selection signal by inputting the clock information from the clock information input unit and receiving the external 8KHz extracted the clock through the clock reproducing unit 14, the internal 8KHz by the free running of the system internal clock generator 4, and the reference clock selection signal. Generates a reference clock signal of 8KHz. In other words, if the local system receives the clock from the optical system, the reference clock selection signal selects the first received 8KHz or the second received 8KHz to synchronize with the system clock, and if the local system receives the clock from the E1 data, selects the reference clock. The unit 20 selects and synchronizes an external 8KHz, and likewise, if the local system generates a clock in itself, the reference clock selector 20 selects an internal 8KHz to synchronize.

On the other hand, the oscillator 30 oscillates a predetermined clock signal (for example, 16.384 MHz). The phase synchronizer 40 receives an 8 KHz reference clock selected by the reference clock selector 20 and a 16.384 MHz clock of the oscillator 30 to provide an 8 KHz E1 frame signal synchronized with the reference clock and an E1 clock of 2.048 MHz. The E1 framer 50 generates the E1 data (Framed all'1 ') synchronized with the E1 clock of 2.048 MHz by inputting the E1 frame signal and the E1 clock.

The E1 line connection unit 60 receives the unipolar E1 data output from the E1 framer 50 and the E1 clock output from the phase synchronizer 40 and line-codes the unipolar E1 data (HDB3). Framde all '1') is converted to bipolar E1 data and outputs an E1 tip (TIP) and an E1 ring (RING).

As described above, the circuit of the present invention has an effect of generating external E1 data synchronized with the system clock by selecting a reference clock according to the clock source of the local system.

Claims (1)

In a synchronous transmission device in which the clock source is duplicated and generates E1 data by receiving a clock through an external clock source or an optical transmission path, A clock supply unit 10 for extracting a clock from the optical system and the E1 data; A system internal clock generator (4) for receiving a clock from the clock supply unit (10) to generate a system clock required for a local system; A reference clock selector 20 for selecting a reference clock according to a reference clock selection signal from among clocks output by the clock supply unit 10; An oscillator 30 oscillating a predetermined clock frequency; A phase synchronizer 40 which receives the reference clock output by the reference clock selector 20 and the clock generated by the oscillator 30 and generates an E1 frame signal and an E1 clock synchronized with the reference clock; An E1 framer 50 for generating unipolar E1 data by using the output of the phase synchronizer 40 as an input; And The E1 data output from the E1 framer 50 and the E1 clock output from the phase synchronizer 40 are input and line-coded to the unipolar E1 data to be bipolar, and the E1 tip TIP and the E1 ring External E1 data generator, characterized in that consisting of the E1 line connecting portion (50) for outputting.

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