KR100198785B1 - Apparatus for transmitting frequency information - Google Patents

Abstract

In the present invention, the count period is set based on the basic clock, the number of cycles of the basic clock during the count period is counted, and the result is transmitted. In the second and subsequent servers, The present invention relates to a frequency information transmission apparatus and a transmission method for time information management, in which frequency information transmitted from a previous stage can be directly transmitted as frequency information to a next stage server when frequency synchronization is obtained.

Description

Frequency information transmission device and transmission method for time information management

The present invention relates to a frequency information transmission apparatus and a transmission method for managing time information between servers providing multimedia services.

In a server providing a multimedia service, time management between servers is an important factor for preventing reuse of services provided by the user and the server. These are generated by a phase-locked oscillator that uses a synchronous signal as a reference clock to synchronize the servers with the basic clock necessary for synchronization of the servers. The frequency of the synchronization clock needs to be the same as the synchronization clock of the transmission side when the reception side processes. The frequency information transmission method of the synchronization clock counts a conventional period as the number of cycles of the basic clock and transmits a count result. That is, when the predetermined time is about 33 msec, which is the period of one image frame, the count result in the case of the transmission clock rate of 6.312 Mbps is 210610 (336 B2 in hexadecimal), and the fluctuation width of this value is about ± 30ppm, the count result is 21064 (336AC) to 210616 (336B8), so the data of the lower 8 bits of the counter is transmitted. On the receiving side, it has a PLO that generates a synchronization clock. It generates a video frame pulse based on the PLO output, counts the transmission length during one video frame, and outputs the lower 8 bits of the count result and the 8- The output frequency of the PLO is controlled so that the difference between the data is 0, thereby generating a clock having the same value as the synchronization frequency of the transmission side. In this frequency information transmission method, since only the value of the transmission speed at which the server is transmitted is considered, only the lower 8-bit data which is the count result of the count is different every time the transmission speed is changed corresponding to the transmission rank. For this reason, in the case of a system configuration in which a synchronization device within a frame for 32 Mbps and a frame-to-frame synchronization device such as 6.3 Mbps are multi-stage cascade-connected, a coding device of a second stage or less operates PLO based on 8- And the server is reproducing the synchronization clock. Therefore, in such a multi-stage connection system, the PLO for synchronous clock recovery is connected in multiple stages, and the time from the PLO to the synchronous state is long at the final stage, so that it takes a long time to obtain a stable service . In addition, since the circuit configuration differs for each synchronizing device of the server, there is a disadvantage in that the circuit can not be used in common.

Therefore, the present invention sets the count period based on the fundamental frequency, counts the number of periods of the fundamental frequency for each counting period, and transmits the result, and transmits the result of transmission to the second- The present invention provides a frequency information transmission apparatus and a transmission method for time information management, which can transmit the 8-bit frequency information transmitted from the transmission side to a server of the next stage without writing the same. There is a purpose.

According to an aspect of the present invention, there is provided a data transmission system including a reception interface circuit for converting data input through a data input terminal into a signal conforming to a signal format on a transmission path, extracting a transmission clock from the data sequence, A first dividing circuit for dividing frequency information by inputting an output of the receiving interface circuit according to a transmission clock of the interface circuit; a first dividing circuit for dividing frequency information by receiving a transmission clock of the receiving interface circuit; A clock regeneration circuit which receives the output of the demultiplexing circuit and reproduces a transmission clock in accordance with the output of the first demultiplexing circuit and a demodulation circuit which demultiplexes the demultiplexed frequency of the demultiplexing circuit Convert information to a clock with a speed for signal processing A signal processing circuit for performing predetermined signal processing on the output of the first buffer circuit in accordance with the output of the clock regeneration circuit; A phase-locked oscillator which receives an output of the second transfer circuit as an input; and a phase-locked oscillator which is inputted through a clock and a loop-back clock input terminal of the internal clock source A second frequency dividing circuit for dividing the frequency information by using the output of the third frequency dividing circuit as an input; and a third frequency dividing circuit for dividing the output of the frequency dividing circuit in accordance with the output of the second frequency dividing circuit A frequency information reproducing circuit for reproducing the frequency information as an input; and a reproducing circuit for reproducing the frequency information reproduced by the second switching circuit, the third switching circuit, A first switching circuit for selectively controlling the output of the clock recovery circuit and an output of the signal processing circuit in accordance with the output of the clock recovery circuit and the output of the third switching circuit; A first multiplexing circuit for multiplexing the output of the converted second buffer circuit and the output of the frequency information reproducing circuit according to the output of the third switching circuit; And a transmission interface circuit for converting the output of the first multiplexing circuit into a signal format on a transmission path and sending out the data through a data output terminal.

It is a further object of the present invention to provide a method of measuring a transmission rate of a transmission line, comprising the steps of: setting a measurement period of a count in common on a transmission side and a reception side, Measuring the number of basic clock pulses for each period; and transmitting the measurement result of the number of pulses to the receiving side as frequency information.

A step of counting a clock relating to a base every counting period by setting a counting period on the basis of the fundamental frequency and transmitting a count result; and a step of counting a frequency between a transmission speed of the input stage and a transmission speed of the output stage And transmitting the count information transmitted from the previous stage to the next stage server as frequency information when synchronization is obtained.

FIG. 1 is a block diagram of a frequency information transmission apparatus for time information management according to the present invention; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

1: Data input terminal 2: Receive interface circuit

3: Separation circuit 4, 6: First and second buffer circuits

5: Signal processing circuit 7, 203: First and second multiplexing circuits

8: transmission interface circuit 9: data output terminal

10, 17, 101, 201: first, second, third,

11, 15, 16: First, second and third switching circuits

12: Internal clock source 13: External supply clock input terminal

14: loop-back clock input terminal 18: phase-locked oscillator

100: basic clock regeneration circuit 102, 202: first and second counter

103: a subtraction circuit 104: a filter

105: voltage-controlled oscillator 200: frequency information reproducing circuit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The accompanying drawings are block diagrams of a frequency information transmission apparatus for time information management according to the present invention.

Reference numeral 1 denotes a data input terminal, 2 denotes a reception interface circuit, 3 denotes a separation circuit, 4 denotes a first and a second buffer circuit, 5 denotes a signal processing circuit, 7 denotes a first and a second multiplexing circuit, Reference numeral 9 denotes a data output terminal, reference numerals 10, 17, 101 and 201 denote first to fourth frequency dividing circuits, reference numerals 11, 15 and 16 denote first, second and third switching circuits, Reference numeral 102 denotes a first and a second counter, reference numeral 103 denotes a subtraction circuit, reference numeral 104 denotes a filter, reference numeral 105 denotes a voltage controlled oscillator, reference numeral 200 denotes a voltage controlled oscillator, Is a frequency information generating circuit.

First, the data input from the data input terminal 1 is converted into a unipolar signal, which is a signal format (for example, a signal format capable of being processed from a bipolar signal) on the transmission path in the reception interface circuit 2, . The reception interface circuit 2 extracts the transmission clock from the data series and supplies the transmission clock to the first frequency division circuit 10, the separation circuit 3 and the first buffer circuit 4, respectively. The separation circuit 3 separates the frequency information from the signal supplied from the reception interface circuit 2. The separated frequency information is input to the first buffer circuit 4 and is converted from the transmission clock speed to the speed of the basic clock system for signal processing. The output signal of the converted first buffer circuit 4 is input to the signal processing circuit 5 to perform predetermined signal processing. The output signal of the signal processing circuit 5 is input to the second buffer circuit 6 and is converted from the speed of the basic clock fq to the speed of the next stage transfer clock f12. The output signal of the converted second buffer circuit 6 is input to the first multiplexing circuit 7. The first multiplexing circuit 7 multiplexes the frequency information and outputs it to the transmission interface circuit 8. In the transmission interface circuit 8, data is converted in the form of a signal on a transmission path and transmitted through a data output terminal 9. The transmission clock f11 output from the reception interface circuit 2 is used for processing to the input terminal of the first buffer circuit 4 and is also divided by the first division circuit 10 at a predetermined division ratio. On the other hand, the transmission speed f12 of the next transmission path is the same as that of the output of the internal clock source 12 in the third switching circuit 16, the clock inputted through the loopback clock input terminal 14, The output is switched and supplied. The output of the third switching circuit 16 is used for processing below the output terminal of the second buffer circuit 6 and the second dividing circuit 17 divides the output of the third switching circuit 16 at a predetermined division ratio. Here, the clock supplied to the loopback clock input terminal 14 is selected when the clock extracted from the input data series of the transmission path at the next stage extending in two directions is looped back and used as the transmission clock f12. The input of the phase-locked oscillator 18 is connected to an external clock supply terminal 13, for example, by selecting either a clock supplied from an external clock supply device or an output of the frequency divider circuit 10, One transfer clock f12 is generated. The second third switching circuits 15 and 16 are controlled according to the first switching circuit 11 in response to the transmission system, but the method of making them is not limited to the example shown in the accompanying drawings. The output frequency of the first and second frequency dividers 10 and 17 is a frequency (8 kHz) common to various transmission speeds or the like. The basic clock regeneration circuit 100 and the frequency information generation circuit 200 are operated on the basis of the common frequency (8 kHz).

In the basic clock regenerating circuit 100, the third dividing circuit 101 receives the output of the first dividing circuit 10 and divides it by a predetermined dividing ratio. The output signal of the divided third dividing circuit 101 is input to the first counter 102. The first counter 102 outputs a reset signal according to the output signal of the third frequency divider circuit 101 to be input. The first counter 102 periodically resets in accordance with the reset signal, counts the output clock of the voltage-controlled oscillator 105 input during the period, and outputs the count result data immediately before the counter is reset to the subtraction circuit 103 ). The subtraction circuit 103 calculates the output of the first counter 102 in accordance with the frequency information supplied from the separation circuit 3 and supplies the result to the filter 104. Here, the frequency information supplied from the separating circuit 3 is lower 8-bit data of the count result obtained by counting the clock used in the preceding stage device in the same cycle as the reset period of the first counter 102. [ Therefore, when the output frequency fq of the voltage-controlled oscillator 105 is higher than the frequency of the clock used in the preceding stage apparatus, the output of the subtraction circuit 103 becomes negative (-). The minus (-) output of the subtraction circuit 103 controls the output frequency fq of the smoothed voltage controlled oscillator 105 to be gradually lowered by the filter 104. Conversely, when the output frequency fq of the voltage controlled oscillator 105 is low, the filter 104 controls the output frequency fq of the smoothed voltage controlled oscillator 105 to be high. Therefore, it becomes possible to generate the same frequency as that of the device at the preceding stage. The filter 104 can be made in various ways starting with a method using a digital integrating circuit and a D / A converting circuit.

In the frequency information generating circuit 200, the fourth frequency divider circuit 201 receives the output of the second frequency divider circuit 17 and divides it by a predetermined frequency division ratio. The output signal of the divided fourth divider circuit 201 is input to the second counter 102. The second counter 102 outputs a reset signal according to the output signal of the fourth dividing circuit 201 to be inputted. The second counter 202 periodically resets according to the reset signal, counts the output clock of the voltage-controlled oscillator 105 input during the period, and outputs the count result data immediately before the counter is reset to the second multiplexing circuit (203). The second multiplexing circuit 203 is controlled by the first multiplexing circuit 11 and selects the output of the demultiplexing circuit 3 when the frequency synchronization between the input terminal transmission rate and the output terminal transmission rate of the apparatus is obtained, (7). In other cases, the output of the second counter 202 is selected and supplied to the first multiplexing circuit 7. The input frequencies of the third and fourth frequency dividers 101 and 201 are common to the entire system, and these predetermined frequency division ratios are commonly used throughout the system. Therefore, the basic clock regeneration circuit 100 and the frequency information generation circuit 200 are also commonly formed in the entire system.

On the other hand, the transmission line clock counted by reversing the relationship between the reset signal of the second counter 202 and the clock is multiplied by 1024 based on the frequency (8 kHz) common to the clocks of the respective transmission paths connected to the digital link A clock of 8.192 MHz is generated in common, and the number of pulses per one video frame is transmitted, thereby enabling a multi-link connection.

As described above, according to the present invention, since the synchronous clock regenerating circuit and the frequency information generating circuit are configured to be common to the entire system, the advantage of being able to make these circuits common to various apparatuses have.

In addition, when frequency synchronization is established between the input terminal transmission rate and the output terminal transmission rate in the frequency information generation circuit, the frequency information transmitted from the device at the front end can be directly transmitted to the device at the rear end. Therefore, the synchronous clock regeneration circuit including the phase-locked oscillator does not pass through any of the stages in the middle of the clock reproduced by the final-stage apparatus, so that the synchronous pull-in time is shortened and the time from receiving the stable service is shortened It is effective.

Claims (6)

A receiving interface circuit for converting data input through a data input terminal into a signal conforming to a signal format on a transmission path and extracting and outputting a transmission clock from the data sequence; A first dividing circuit for dividing the frequency information by using the output of the circuit as an input; a first dividing circuit for dividing the frequency information by using the transmission clock of the receiving interface circuit as an input; A clock regeneration circuit for regenerating a transmission clock in accordance with an output of the first frequency division circuit and a frequency divider for dividing the separated frequency information of the separation circuit in accordance with an output of a transmission clock and a clock regeneration circuit of the reception interface circuit, A first buffer circuit for converting the clock signal into a clock signal, A signal processing circuit which performs predetermined signal processing on the output of the first buffer circuit in accordance with the output of the reproducing circuit and an external clock which is inputted through the output of the first frequency dividing circuit and the external supply clock terminal A third switching circuit having a second switching circuit, a phase-locked oscillator inputting an output of the second switching circuit, and a clock input through the phase-locked oscillator, a clock of an internal clock source, A second dividing circuit for dividing the frequency information by an input of the output of the third switching circuit and for reproducing the frequency information by using the output of the frequency dividing circuit in accordance with the output of the second frequency dividing circuit A frequency information reproducing circuit, and a first switching circuit for selectively controlling the second switching circuit, the third switching circuit, and the frequency information reproducing circuit A second buffer circuit for converting an output of the signal processing circuit from a speed of a basic clock to a speed of a next transmission clock in accordance with an output of the clock regeneration circuit and an output of the third switching circuit; A first multiplexing circuit for multiplexing the output of the converted second buffer circuit and the output of the frequency information reproducing circuit in accordance with the output of the third multiplexing circuit and a multiplexing circuit for multiplexing the output of the first multiplexing circuit in accordance with the output of the third transferring circuit And a transmission interface circuit for converting the data into a signal format on the transmission path and transmitting the data through a data output terminal. The clock recovery circuit according to claim 1, wherein the clock regeneration circuit comprises: a third frequency division circuit for dividing the output of the first frequency division circuit by a predetermined frequency division ratio; and a second frequency division circuit for counting the output of the voltage control oscillator in accordance with the output of the third frequency division circuit A subtracting circuit for calculating the frequency information supplied from the separating circuit and the output of the second counter and a voltage controlled oscillator for receiving the frequency information calculated from the subtracting circuit through a filter. Frequency information transmission device for information management. The frequency control apparatus according to claim 1, wherein the frequency information generating circuit comprises: a fourth frequency dividing circuit for frequency dividing the output of the second frequency dividing circuit to a predetermined frequency division ratio; and a frequency dividing circuit for counting the output of the voltage control oscillator 2 counter and a second multiplexing circuit for multiplexing the outputs of the frequency dividing circuit and the second counter in accordance with the output of the first transferring circuit. A frequency information transmission method for transmitting frequency information of a clock having time information to a reception side and for reproducing a clock having the same frequency as a transmission side based on transmitted frequency information at a reception side, Measuring the number of basic clock pulses for each measurement period, and measuring the number of pulses of the clock signal for each measurement period as frequency information And transmitting the frequency information to the receiving side. The method according to claim 4, wherein the step of transmitting the measurement result of the number of pulses to the reception side as frequency information includes counting the number of pulses per specific period and transmitting the counted number as frequency information to the reception side. Information transmission method. A frequency information transmission method for sequentially transmitting frequency information of a clock having time information to each of a plurality of cascade-connected cascaded devices, the method comprising: setting a count period based on a fundamental frequency to count a basic clock for each count period, And transmitting the count information transmitted from the preceding stage to the next stage server as frequency information when frequency synchronization between the transmission rate of the input stage and the transmission rate of the output stage is obtained in the second stage or lower server And transmitting the frequency information.