KR19980025931A - Frequency information transmission apparatus and method for time information management - Google Patents

Abstract

The present invention sets a count period based on the base clock, counts the number of cycles of the base clock during the count period, and transmits the result. When frequency synchronization is obtained, the present invention relates to a frequency information transmission apparatus and a transmission method for time information management, in which the frequency information transmitted from the front end can be transmitted as it is to the next server.

Description

Frequency information transmission apparatus and method for time information management

The present invention relates to a frequency information transmission apparatus and a transmission method for managing time information between servers providing a multimedia service.

In a server providing a multimedia service, time management between servers is an important factor for preventing user authentication and reusing services provided by the server. These are generated based on the phase-locked oscillator whose synchronization clock is the reference signal as the basic clock necessary for the synchronization of the servers. The frequency of this synchronization clock needs to use the same frequency as the synchronization clock of the transmission side when processing on the receiving side. In the frequency information transmission method of the synchronization clock, a predetermined period of time is counted by the number of cycles of the basic clock to transmit a count result. In other words, when the predetermined time is set to about 33 msec, which is the period of one video frame, the count result at the transmission clock rate of 6,312 Mbps is 210610 (336B2 in hexadecimal), and the variation of this value is approximately ± ± the variation in the synchronization frequency. In the case of 30 ppm, since the count result is 21064 (336AC) to 210616 (336B8), data of the lower 8 bits of the counter is transmitted. The receiver has a PLO that generates a synchronization clock, generates a video frame pulse based on the PLO output, counts the transmission length for one video frame, and counts the lower 8 bits of the count result and 8-bit data sent from the transmitter. In comparison, the output frequency of the PLO is controlled so that the data difference is zero, thereby generating a clock having the same value as the synchronization frequency of the transmitter. In the frequency information transmission method, the conventional method simply considers the value of the transmission speed at which the server is transmitted. Therefore, the lower 8 bit data, which is the count result of the counter, is changed every time the transmission speed is different according to the transmission level. For this reason, in the case of a system configuration in which a synchronization device in a frame for 32 Mbps and an inter-frame synchronization device such as 6.3 Mbps are cascade-connected, the PLO is driven based on 8-bit frequency information transmitted from the transmitting side in the second or lower encoder. Playing the server's synchronization clock. Therefore, this multi-stage access system has a drawback in that the PLO for synchronizing clock reproduction is also multi-stage connected, and in the final stage, the time until the PLO is synchronized is increased, resulting in a long time for stable service. . In addition, since the circuit configuration is different for various synchronization devices of the server, there is a disadvantage in that the circuits cannot be commonized.

Therefore, the present invention sets a count period based on the fundamental frequency, counts the number of cycles of the fundamental frequency for each count period, and transmits the result. The transmission speed of the input terminal and the transmission speed of the output terminal in the second or less server are transmitted. Provided is a frequency information transmission apparatus and a transmission method for time information management, in which the frequency between the two stages can be transmitted to the next server without creating and writing 8-bit frequency information transmitted from the transmitter when synchronization is obtained. There is a purpose.

The present invention for achieving the above object converts the data input through the data input terminal into a signal suitable for the signal format on the transmission path, the receiving interface circuit for extracting and outputting the transmission clock from the data series, and the receiving A separation circuit for separating frequency information by using an output of the receiving interface circuit as an input according to a transmission clock of an interface circuit, a first division circuit for splitting frequency information by using a transmission clock of the receiving interface circuit; A clock regeneration circuit for inputting an output of the separation circuit and reproducing a transmission clock according to the output of the first division circuit, and a separation of the separation circuit according to an output of the transmission clock and the clock reproduction circuit of the reception interface circuit. Convert frequency information to a clock for signal processing speed The signal processing circuit performs predetermined signal processing on the output of the first buffer circuit according to the output of the first buffer circuit, the clock reproducing circuit, the output of the first division circuit and the external supply clock terminal. A second switching circuit having an input external clock as an input, a phase locked oscillator having an output of the second switching circuit as an input, a phase locked oscillator, a clock of an internal clock source, and a loopback clock input terminal; A third switching circuit for inputting a clock, a second splitting circuit for splitting frequency information with an output of the third switching circuit, and an output of the splitting circuit in accordance with the output of the second splitting circuit. A frequency information reproducing circuit for reproducing frequency information as an input, and selectively controlling the second switching circuit, the third switching circuit, and the frequency information reproducing circuit. A first switching circuit and a second buffer circuit for converting the output of the signal processing circuit from the speed of the basic clock to the speed of the next transmission clock in accordance with the output of the clock regeneration circuit and the output of the third switching circuit. A first multiplexing circuit for multiplexing the output of the converted second buffer circuit and the output of the frequency information reproducing circuit according to the output of the third switching circuit, and the first multiplexing according to the output of the third switching circuit. It is characterized by consisting of a transmission interface circuit for converting the output of the circuit into a signal format on the transmission path and then sending it out through the data output terminal.

In addition, another object to achieve the above object is to directly set the measurement period of the counter in common to the transmitting and receiving side on the basis of the frequency obtained in common to the transmission speed of the various transmission paths, and the measurement And measuring the number of basic clock pulses per cycle and transmitting the measurement result of the number of pulses as frequency information to the receiving side.

Also, setting a count period based on the fundamental frequency to count a clock related to the basis of each count period and transmitting a count result, and a frequency between the transmission rate of the input stage and the transmission rate of the output stage in the second or lower server. When synchronization is obtained, the method includes transmitting the count information transmitted from the front end to the next server as frequency information.

The accompanying drawings are block diagrams of a frequency information transmission apparatus for managing time information according to the present invention.

* Description of the symbols for the main parts of the drawings *

1: Data input terminal 2: Receive interface circuit

3: Separation circuit 4, 6: First and second buffer circuit

5: signal processing circuit 7, 203: first and second multiplexing circuit

8: Transmission interface circuit 9: Data output terminal

10, 17, 101, and 201: first, second, third, and fourth division circuits

11, 15 and 16: First, second and third switching circuits

12: Internal clock source 13: Externally supplied clock input terminal

14 Loopback clock input terminal 18: Phase locked oscillator

100: basic clock regeneration circuit 102, 202: first and second counters

103: subtraction circuit 104: filter

105: voltage controlled oscillator 200: frequency information reproduction circuit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The accompanying drawings are block diagrams of a frequency information transmission apparatus for managing time information according to the present invention.

Reference numeral 1 is a data input terminal, 2 is a receiving interface circuit, 3 is a separate circuit, 4 and 6 are first and second buffer circuits, 5 is a signal processing circuit, 7, 203 is a first and second multiplexing circuit, 8 Is a transmission interface circuit, 9 is a data output terminal, 10, 17, 101, and 201 are first through fourth division circuits, 11, 15 and 16 are first through third switching circuits, 12 is an internal clock source, and 13 is an external Supply clock terminal, 14 is loopback clock terminal, 18 is phase locked oscillator, 100 is basic clock regeneration circuit, 102 and 202 are first and second counters, 103 is subtraction circuit, 104 is filter, 105 is voltage controlled oscillator, 200 Is a frequency information generating circuit.

First, the data input from the data input terminal 1 is converted into a unipolar signal in a signal format (for example, a signal format that can be processed from a bipolar signal) on the transmission path by the receiving interface circuit 2 and separated into a separate circuit 3. Supplied. In addition, the reception interface circuit 2 extracts the transmission clock from the data series and supplies it to the first division circuit 10, the separation circuit 3, and the first buffer circuit 4, respectively. The separating circuit 3 separates frequency information from the signal supplied from the receiving interface circuit 2. The separated frequency information is input to the first buffer circuit 4 to be converted from the speed of the transmission clock to the speed of the basic clock system for signal processing. The output signal of the converted first buffer circuit 4 is input to the signal processing circuit 5 to perform a predetermined signal processing. The output signal of the signal-processed signal processing circuit 5 is input to the second buffer circuit 6 to be converted from the speed of the basic clock fq to the speed of the next transmission clock f12. The output signal of the converted second buffer circuit 6 is input to the first multiplexing circuit 7. The first multiplexing circuit 7 multiplexes frequency information and outputs the same to the transmission interface circuit 8. The transmission interface circuit 8 converts the data into a signal format on the transmission path and transmits the data through the data output terminal 9.

The transmission clock f11 output from the reception interface circuit 2 is used for processing up to the input terminal of the first buffer circuit 4 and is divided at a predetermined division ratio in the first division circuit 10. On the other hand, the transmission speed f12 of the transmission path of the next stage is the clock or phase synchronization oscillator 18 input from the third switching circuit 16 through the output of the internal clock source 12 and the loopback clock input terminal 14. It is supplied by switching the output of. The output of the third switching circuit 16 is used for processing below the output terminal of the second buffer circuit 6, and is also divided by the second division circuit 17 at a predetermined division ratio. The clock supplied to the loopback clock input terminal 14 is selected when the clock extracted from the input data sequence of the transmission path of the next stage extending in both directions is looped back and used as the transmission clock f12. In addition, the input of the phase-locked oscillator 18 passes through an external supply clock terminal 13, for example, selects either a clock supplied from an external clock supply device or an output of the frequency divider circuit 10 to correspond to the input signal thereof. One transmission clock f12 is generated. The second third switching circuits 15 and 16 are controlled according to the first switching circuit 11 in response to the transmission system, but the method of making them is not limited to the example shown in the accompanying drawings. As the output frequencies of the first and second division circuits 10 and 17, a frequency (8 kHz) or the like common to various transmission speeds is used. The basic clock regeneration circuit 100 and the frequency information generation circuit 200 are operated based on the common frequency (8 kHz).

In the basic clock regeneration circuit 100, the third division circuit 101 divides the output of the first division circuit 10 as an input at a predetermined division ratio. The output signal of the divided third division circuit 101 is input to the first counter 102. The first counter 102 outputs a reset signal according to the output signal of the third division circuit 101 input. The first counter 102 is periodically reset according to the reset signal to count the output clock of the voltage-controlled oscillator 105 inputted between the periods to subtract the count result data before the counter is reset. ) Calculates the output of the first counter 102 according to the frequency information supplied from the separation circuit 3 and supplies the result to the filter 104. Here, the frequency information supplied from the separation circuit 3 is the lower 8-bit data of the count result obtained by counting the clock used in the apparatus of the previous stage between the same period as the reset period of the first counter 102. Therefore, when the output frequency fq of the voltage controlled oscillator 105 is higher than the frequency of the clock used in the preceding apparatus, the output of the subtraction circuit 103 becomes negative (-). The negative output of the subtraction circuit 103 controls the output frequency fq of the voltage controlled oscillator 105 smoothed by the filter 104 to be gradually lowered. Conversely, when the output frequency fq of the voltage controlled oscillator 105 is low, the output frequency fq of the voltage controlled oscillator 105 smoothed by the filter 104 is controlled to be high. Therefore, it becomes possible to generate the same frequency as the device of the front end. The filter 104 can be made according to various methods, including a method using a digital integrating circuit and a D / A conversion circuit.

In the frequency information generating circuit 200, the fourth division circuit 201 divides the output of the second division circuit 17 into an input at a predetermined division ratio. The output signal of the divided fourth division circuit 201 is input to the second counter 102. The second counter 102 outputs a reset signal according to the output signal of the fourth division circuit 201 that is input. The second counter 202 is periodically reset according to the reset signal to count the output clock of the voltage-controlled oscillator 105 input between the periods, and the second multiplexing circuit counts the count result data just before the counter is reset. 203 is supplied. The second multiplexing circuit 203 is controlled by the first steel circuit 11 and selects the output of the separation circuit 3 when the frequency synchronization of the input transmission speed and the output transmission speed of the device is obtained. It is supplied to (7). In another case, the output of the second counter 202 is selected and supplied to the first multiplexing circuit 7. The input frequencies of the third and fourth division circuits 101 and 201 are common to the whole system, and these predetermined division ratios are also commonly used throughout the system. Thus, the basic clock regeneration circuit 100 and the frequency information generation circuit 200 are also commonly configured throughout the system.

On the other hand, by reversing the relationship between the reset signal and the clock of the second counter 202, the transmission-side clock counted is 1024 times based on the frequency (8 kHz) common to the clocks of each transmission path connected digitally. Multi-link connection is possible by generating a common 8.192kHz clock and transmitting the number of pulses per one video frame.

As described above, according to the present invention, since the synchronization clock regeneration circuit and the frequency information generation circuit are configured to be common to the entire system, these circuits are commonly configured to various devices, thereby reducing the price of the device. have.

In addition, when frequency synchronization is established between the input transmission speed and the output transmission speed in the frequency information generating circuit, the frequency information transmitted from the previous device can be transmitted to the latter device as it is. Therefore, the clock reproduced by the device of the last stage does not pass through the synchronization clock regeneration circuit including the phase synchronization oscillator in the middle so that the synchronous retrieval time can be increased and the time required for stable service can be shortened. There is.

Claims (6)

A receiving interface circuit for converting data input through a data input terminal into a signal format signal on a transmission path, and extracting and outputting a transmission clock from a data series; A separation circuit for separating frequency information by inputting the output of the reception interface circuit according to a transmission clock of the reception interface circuit; A first division circuit configured to divide frequency information by inputting a transmission clock of the reception interface circuit; A clock regeneration circuit configured to regenerate a transmission clock along the output of the first division circuit, the output of the separation circuit being an input; A first buffer circuit for converting the separated frequency information of the separation circuit to the speed of the basic clock system for signal processing in accordance with the transmission clock of the receiving interface circuit and the output of the clock reproducing circuit; A signal processing circuit which performs predetermined signal processing on the output of the first buffer circuit in accordance with the output of the clock reproducing circuit; A second switching circuit for inputting an external clock input through an output of the first division circuit and an external supply clock terminal; A phase locked oscillator having an output of the second switching circuit as an input; A third switching circuit for inputting a clock inputted through the phase locked oscillator, a clock of an internal clock source, and a loopback clock input terminal, respectively; A second divider circuit configured to divide frequency information by using an output of the third transfer circuit as an input; A frequency information reproducing circuit for reproducing frequency information by inputting the output of the frequency dividing circuit according to the output of the second frequency dividing circuit; A first switching circuit for selectively controlling the second switching circuit, the third switching circuit and the frequency information reproducing circuit; A second buffer circuit for converting the output of the signal processing circuit from the speed of the basic clock to the speed of the next transmission clock in accordance with the output of the clock regeneration circuit and the output of the third switching circuit; A first multiplexing circuit for multiplexing the output of the converted second buffer circuit and the output of the frequency information reproducing circuit according to the output of the third switching circuit; Frequency for managing time information, characterized in that the transmission interface circuit for converting the output of the first multiplexing circuit in the form of a signal on the transmission path according to the output of the third switching circuit and then outputs the data through the data output terminal Information transmission device. The clock divider circuit of claim 1, further comprising: a third divider circuit for dividing an output of the first divider circuit at a predetermined divide ratio; A second counter to count the output of the voltage controlled oscillator in accordance with the output of the third divider circuit; A subtraction circuit for calculating the frequency information supplied from the separation circuit and the output of the second counter; And a voltage controlled oscillator for inputting frequency information calculated from the subtraction circuit through a filter. The frequency divider circuit of claim 1, further comprising: a fourth divider circuit for dividing the output of the second divider circuit at a predetermined divide ratio; A second counter for counting the output of the voltage controlled oscillator according to the output of the fourth division circuit; And a second multiplexing circuit configured to multiplex the outputs of the dividing circuit and the second counter according to the output of the first switching circuit. In the frequency information transmission method of transmitting the frequency information of the clock with the time information to the receiving side and the receiving side reproduces the clock of the same frequency as the transmitting side based on the transmitted frequency information, Directly setting the counter measurement period in common to the transmitting side and the receiving side based on the frequency obtained and generated in common to the transmission speeds of the various transmission paths; Measuring a basic clock pulse number for each measurement period; And transmitting the measurement result of the number of pulses as frequency information to a receiving side. 5. The method of claim 4, wherein the transmitting the measurement result of the number of pulses to the receiving side as frequency information includes counting the number of pulses per specific period and transmitting the frequency information to the receiving side as frequency information. How to send information. An information method for sequentially transmitting frequency information of a clock with time information to devices of each stage connected in cascaded connection, Setting a count period based on the fundamental frequency to count the basic clock for each count period and transmitting the count result; If the frequency synchronization between the transmission speed of the input stage and the transmission speed of the output stage is obtained in the second stage or less server, the step comprising the step of transmitting the count information transmitted from the front end as frequency information to the next stage server Frequency information transmission method for information management.