KR100199960B1 - Apparatus for generating and reproducing sync. clock - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Synchronous Clock Generation and Playback

2. The technical problem to be solved by the invention

In order to match the conventional DS class 2 signal and MPEG2 TS signal with ATM network, the AAL layer processing caused by changing the processing of the AAL layer according to the service characteristic is solved.

3. Summary of Solution to Invention

A line interface unit 10 for inputting and outputting DS2 or MPEG2 TS signals; A network reference clock generator 20 generating a network reference clock obtained from the network; A transmission synchronization clock generation section 30 for generating a synchronization information clock for processing the DS2 signal and the MPEG2 TS signal; An ATM cell processing unit (40) for inserting and transmitting the synchronization information clock generated by the transmission synchronization clock generation unit (30) into an ATM cell information field and separating the received AMT cell; A reception synchronization clock generation unit (50) for generating a reception side synchronization information clock for processing the service data received from the ATM cell processing unit (40); And a synchronization clock recovery unit 60 for restoring the synchronization clock by comparing and processing the synchronization information clock generated by the reception synchronization clock generator 50 and the synchronization information clock extracted from the ATM cell processor 40. I did it.

4. Important uses of the invention

It is applied to match DS class 2 signal and MPEG2 TS signal to ATM network in broadband integrated telecommunication network.

Description

Synchronous Clock Generation and Playback

In general, broadband signal level 2 (DS2) signals and video on demand (VOD), CATV, and MPEG2 moving picture expert group 2 transport streams, which are emerging in the broadband integrated telecommunication network (B-ISDN). When an ATM cell is configured to connect a signal or the like to an ATM network, the processing of the AAL layer is different for each service characteristic in the ATM Adaptation Layer (AAL) layer.

In other words, ATM is the core technology for integrating and accommodating various broadband communication services in the broadband integrated telecommunication network. In order to match DS2 and MPEG2 TS signals such as general telephone and data service ISDN services to ATM networks, The service is performed by changing the processing of the AAL layer.

In this case, transmission of synchronization information is required for CBR (Constant Bit Rate) service of DS2 level signal and MPEG2 TS signal, and it is also important to recover the clock from the transferred synchronization information. Will be.

Therefore, this conventional technology has a problem that the AAL layer processing is complicated because the processing of the AAL layer is different depending on the service characteristics in order to match the DS2 class signal and the MPEG2 TS signal to the ATM network.

Therefore, the present invention has been proposed to solve various problems that occur when performing a service to the ATM network in the general broadband information communication network as described above,

An object of the present invention is to provide a synchronization clock generation and reproducing apparatus for easily matching a DS2 level signal and an MPEG2 TS (6.312M CBR) signal to an ATM network in a broadband integrated telecommunication network (B-ISDN).

Technical means for achieving the object of the present invention,

A line interface unit for inputting / outputting DS2 level signals and MPEG2 TS signals;

A network reference clock generator for generating a network reference clock obtained from the network;

A transmission synchronization clock generation unit for generating a synchronization information clock for processing the DS2 level signal and the MPEG2 TS signal;

An ATM cell processing unit for inserting and transmitting a synchronization information clock generated by the transmission synchronization clock generation unit into an ATM cell information field and separating the received ATM cell;

A reception synchronization clock generation unit for generating a reception side synchronization information clock for processing the service data received from the ATM cell processing unit;

And a synchronization clock recovery unit for restoring the synchronization clock by comparing and processing the synchronization information clock generated by the reception synchronization clock generator and the synchronization information clock extracted from the ATM cell processor.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

1 is a block diagram of a synchronous clock generation and reproduction apparatus according to the present invention.

2 is an ATM cell format diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

10: line interface unit 20: network reference clock generation unit

30: transmission synchronous clock generation unit 40: ATM cell processing unit

50: Receive sync clock generation unit 60: Sync clock recovery unit

1 is a block diagram of a synchronization clock generation and generation device according to the present invention. As shown, a line interface unit 10 for inputting and outputting DS2 or MPEG2 TS signals, a network reference clock generator 20 for generating a 155.52MIIz network reference clock input from the network, and A transmission synchronization clock generation unit 30 for generating a synchronization clock for processing DS2 signals and MPEG2 TS signals, and a synchronization clock generated by the transmission synchronization clock generation unit 30 is inserted into an ATM cell information field for transmission and reception. ATM cell processing unit 40 which separates and transmits the received ATM cell to the receiving unit, and a receiving synchronization clock generating unit generating a receiving side synchronization clock to extract a synchronization clock from the ATM cell received from the ATM cell processing unit 40 ( 50) and a synchronous clock recovery unit 60 for restoring the synchronous clock by comparing and processing the synchronous clock generated by the reception synchronous clock generator 50 and the synchronous clock extracted from the ATM cell processor 40. It became.

In this case, the transmission synchronization clock generation unit 30 divides the 3008 divider 31 which divides the input DS2 clock (6.312MIIz) by 3008 and the 155.52MIIz network reference clock generated by the network reference clock generator 20. 20 divisions 32 for generating a clock for generating synchronization information SRTS and 20 divided clocks 7.776 MIIz in the 20 divisions 32 are counted and outputted as 4 bits. 4 bit counter 33 and a clock divided by the 3008 frequency divider 31 to latch 34 which latches the 4-bit count value output from the 4-bit counter 33 and generates the synchronization information (SRTS). It was made up.

In addition, the reception synchronization clock generation unit 30 is a 3008 frequency divider 31 for dividing the input DS2 clock (6.312MIIz) 3008 and the 155.52MIIz network reference clock generated by the network reference clock generator 20 20 dividers 32 for generating a clock to generate reception synchronization information (SRTS) by 20 divisions, and a clock (7.776MIIz) divided by 20 in the 20 divider 32 are counted and the result values are output as 4 bits. A latch 34 which latches a 4-bit count value output from the 4-bit counter 33 with a clock divided by the 3008 divider 31 to generate the synchronization information SRTS. It consisted of

In addition, the synchronous clock recovery unit 60 extracts a 4-bit synchronous clock from the first octet of the information field processed by the ATM cell processing unit 40, and the synchronous clock detection unit 61. The comparator 62 compares the sending sync clock detected by the reception sync clock generated by the reception sync clock generator 50 with the difference value between the sync clock output from the comparator 63 and the reception sync clock. A divider is selected according to a divider selector 63 for generating a divider select signal, a divider 64 for dividing the network reference clock in two, and a select signal output from the divider selector 63. 13 and 12 dividers 65 for selecting and dividing the clock output from the two dividers 64 to restore the synchronous clock.

The operation of the apparatus for generating and reproducing a synchronous clock according to the present invention configured as described above will be described with reference to FIG. 2.

First, the present invention provides a synchronization clock (Synchornous Residual) which is a difference between a network clock frequency and a signal DS2, MPEGG2 TS to be serviced in order to transmit a signal (DS2, MPEGG2 TS) that does not match the frequency of the network clock at the transmitter. The SRTS is transmitted, and the receiver recovers the service clock using the SRTS transmitted from the transmitter.

Here, the transmission of the SRTS is performed in four cells of eight cells (i.e., SN = 1,3,5 only in the CSI bit of the odd cell through the first octet CSI bit of the information field consisting of 48 octets as in the ATM cell configuration of FIG. 2). (7), CSI4 bits are transmitted and received periodically.

The operation according to the preferred embodiment of the present invention will be described below with reference to this concept of the present invention.

First, the line interface unit 10 inputs and outputs a DS2 signal or an MPEGG2 TS signal, and the 3008 (31) in the transmission synchronization clock generator 30 receives the DS2 clock (6.312) obtained from the line interface unit 10. 3008 MIIz) is outputted. That is, the 3008 (31) transmits 4 bits of synchronization information (STRS) per 8 ATM cell information fields (47 octets * 8 bits * 8 cells = 3008) so that the DS2 clock is divided into 3008. do. In addition, the 20 divider 32 divides the 155.52 MIIz network reference clock generated by the network reference clock generator 20 to generate a clock for generating synchronization information SRTS. That is, the frequency divider 32 divides the network reference clock by 20 because the reference clock must be larger than the service frequency (6.312MIIz) and smaller than twice the service frequency. (6.312MIIz7.776MIIz2 * (6.312MIIz): 155.52MIIz / 20 = 7.776MIIz) In addition, the 4-bit counter 33 counts the 20-minute divided clock (7.7776MIIz) in the above-described 20-minute period 32 to obtain the result. As a result, the latch 34 latches the 4-bit count value output from the 4-bit counter 33 by the clock divided by the 3008 divider 31 so that the first octet of the information field of the ATM cell. As a result, 4-bit value is generated as the synchronization information (SRTS) by one bit only when the odd cell of the eight cells (SN = 1, 3, 5, 7).

The 4-bit SRTS generated in this way is input into the ATM cell processing unit 40. Accordingly, the ATM cell processing unit 40 converts the 4-bit STRS inputted from the first octet generation unit 42 into the information field first. The information field 47 octet generation unit 43 generates the information signal (6.312MIIz) to be serviced as an information field in units of 47 octets, and the ATM cell combination unit 44 performs the above information field. The first octet containing the 47 octets generated by the 47 octet generating unit 43 and the synchronization information generated by the first octet generating unit 42 and the cell head generated by the ATM cell head generating unit 41 are second. The ATM cells are completed by mapping them to the same format.

The ATM cell thus completed is transmitted to the receiving side through the line interface unit 10, and the receiving side reverses the combination of the ATM cell received in the ATM cell combination unit 44 in the ATM cell processing unit 40. Each octet is separated and passed to each octet generator.

On the other hand, the reception synchronization clock generator 50 on the receiving side divides the network reference clock 20 minutes through the 20 divider 51, and the 20-bit divided clock (7.776MIIz) is used by the 4-bit counter 52. Counting generates a 4-bit count value. In addition, the 3008 divider 53 divides the DS2 clock (6.312MIIz) obtained from the above-described line interface unit 30 by 3008, and the latch 54 divides the above-described clock into a clock divided by the 3008 divider 53. A clock for extracting a synchronous clock is generated by latching a 4-bit count value generated by the bit counter 52.

Then, the synchronous clock recovery unit 60 extracts a 4-bit synchronous clock from the first octet of the information field processed by the ATM cell processor 40 in the synchronous clock detector 61, and transmits the extracted 4-bit. The synchronous clock and the 4-bit synchronous clock generated by the reception synchronous clock generator 50 are compared by the comparator 62. The comparator 62 calculates a difference value between the extracted synchronous clock and the received synchronous clock and transfers the difference value to the divider selector 63. The divider selector 63 selects the divider based on the selected value. Allow the recovery of the synchronous clock.

That is, the divider selector 63 determines a value to be output from the 13 or 12 divider 65 according to the SRTS difference value (+ 7--8) obtained by the comparator 62 described above. Then, the 13 or 12 divider 65 divides the clock divided by the divider 64 into the divider determined by the divider selector 63 to generate a reconstructed clock for restoring the serviced data.

That is, the 13 or 12 divider 65 determines the mood period with the current service 80 clock plus the SRTS value output from the comparator 62 (80 + SRTS), and the clock divided by 13 divided by 77.76MIIz every cycle ( 77.76 / 13 = 5.554MIIz) is output to 27 clocks, and the 12-division clock (7.76MIIz / 13 = 5.554MIIz) is output for the remaining period (80 + SRTS-13).

As an example, when the SRTS value is 0, 27 clocks of 13. clocks divided by 77.76MIIz clocks output from the two dividers 64 are output, and 53 clocks of clocks divided by 12 clocks are divided.

As described above, the present invention generates and transmits a synchronization information clock on the receiving side to restore serviced data on the receiving side, and extracts the synchronization information clock on the receiving side to restore the serviced data. There is an effect that can easily match the signal to the ATM network.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating and reproducing a synchronous clock, and in particular, to generate and reproduce a synchronous clock for easily matching a DS2 level signal and an MPEG2 TS (6.312M CBR) signal to an ATM network in a wide area information network (B-ISDN). Relates to a device.

Claims (4)

A line interface unit (10) for inputting and outputting DS2 level signals and MPEG2 TS signals in a broadband integrated information communication network (B-ISDN) for accommodating various broadband communication services; A network reference clock generator 20 generating a network reference clock obtained from the network; A transmission synchronization clock generation section 30 for generating a synchronization information clock for processing the DS2 signal and the MPEG2 TS signal; An ATM cell processor (40) for inserting and transmitting the synchronization information clock generated by the transmission sync clock generator (30) into an ATM cell information field and separating the received ATM cells; A reception synchronization clock generation unit (50) for generating a reception side synchronization information clock for processing the service data received from the ATM cell processing unit (40); And a synchronization clock recovery unit 60 for restoring the synchronization clock by comparing and processing the synchronization information clock generated by the reception synchronization clock generation unit 50 and the synchronization information clock extracted from the ATM cell processing unit 40. Synchronous clock generation and playback device, characterized in that. The reception synchronization clock generator 30 further includes a 3008 divider 31 for dividing an input DS2 clock (6.312 MIIz) by 3008 and a 155.52 MIIz generated by the network reference clock generator 20. 20 dividers 32 which generate a clock for generating synchronization information (SRTS) by dividing the network reference clock by 20 and a clock (7.776MIIz) divided by 20 in the 20 divider 32 are counted. A 4-bit counter 33 for outputting the 4-bit counter, and a 4-bit counter value output from the 4-bit counter 33 by a clock divided by the 3008 divider 31 to generate the synchronization information (SRTS). Synchronous clock generating and reproducing apparatus, characterized in that consisting of a latch (34). The reception synchronization clock generator 30 further includes a 3008 divider 31 for dividing an input DS2 clock (6.312 MIIz) by 3008 and a 155.52 MIIz generated by the network reference clock generator 20. 20 dividers 32 which generate a clock for generating synchronization information (SRTS) by dividing the network reference clock by 20 and a clock (7.776MIIz) divided by 20 in the 20 divider 32 are counted. A 4-bit counter 33 for outputting the 4-bit counter, and a 4-bit counter value output from the 4-bit counter 33 by a clock divided by the 3008 divider 31 to generate the synchronization information (SRTS). Synchronous clock generating and reproducing apparatus, characterized in that consisting of a latch (34). The synchronization clock recovery unit (60) of claim 1, wherein the synchronization clock recovery unit (60) extracts a 4-bit synchronization clock from the first octet of the information field processed by the ATM cell processing unit (40). A comparator 62 for comparing the transmission synchronization clock detected by the detection unit 61 with the reception synchronization clock generated by the reception synchronization clock generation unit 50, a synchronization clock and a reception synchronization clock output from the comparator 63; A divider selector 63 for generating a divider select signal with a difference value of?, A divider 64 for dividing the network reference clock in two, and a select signal output from the divider selector 63; And a 13 or 12 divider 65 for selecting a divider according to the divided divider and dividing the clock output from the 2 divider 64 to restore the synchronous clock. .