KR100212062B1 - Network synchronization circuit - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

The present invention relates to a network synchronization circuit for synchronizing clocks using the SRAT method to synchronize synchronization between stations linking an ATM network with a PDH network.

I. The technical problem to be solved by the invention

In order to prevent the cause of underflow or overflow, use the SRTS method in the ATM network to synchronize the clock between the host and the counterpart.

All. Summary of Solution of the Invention

A network clock generator for inputting a clock signal transmitted from an ATM network to generate and output an ALL1 system clock and an SRTS reference clock signal, and compares an SRTS reference clock output from the network clock generator and a reception recovery clock signal from a PDH line. A comparator for outputting an SRTS code difference value, a code converter for inputting an SRTS code difference value outputted from the comparator, and converting the code value for controlling the actual clock speed by a cross table having a constant value; A D / A converter converting the code value output from the SRTS code converter into an analog signal and outputting the analog signal; a low pass filter for low-pass filtering the analog signal converted by the D / A converter into a voltage; Vcxo generates a reception recovery clock corresponding to the voltage output from the low pass filter.

la. Important uses of the invention

Applies to ATM networks.

Description

Network synchronization circuit

The present invention relates to a network synchronization circuit, and more particularly, to a network synchronization circuit for synchronizing clocks using an SRAT method in order to synchronize synchronization between stations linking an ATM network and a PDH network.

In general, a PDH (Synchronous Digital Hierarchy) network or a SDH (Synchronous Digital Hierarchy) network adds a clock component to a transmitted data component to match the transmission speed between two destinations, and transmits it to the opposite station. At this time, since the medium for transmitting data is transmitted as it is without changing the data stream, the transmission speed can be reproduced using the speed of the data contained in the payload as it is. That is, since the speed of the bit data stream is the clock speed of the transmission medium, the original clock can be reproduced using this.

Data and clocks are regenerated in the process of regenerating bipolar signals (Unipolar) transmitted from the line interface in the PDH network or SDH network through the cable. This signal is encoded and transmitted using a specific method to modify the level before it is transmitted, and is then decoded in the corresponding method at the receiving end to reproduce the original signal. In the ATM network, the bit data stream transmitted from the PDH network is once formatted by the ATM cell format, transformed into a byte-cell cell stream instead of the bit data stream, and transmitted to the opposite station. It cannot be transferred. ATM cell streams are not continuous bit streams. If you do not use the ATM network to regenerate clock components, you will not be able to reproduce the clocks of your own country. Because the transmission rate of the memory cannot be matched, a bit error may occur due to speed unmatch on the transmission, resulting in underflow or overflow.

Accordingly, an object of the present invention is to provide a network synchronization circuit for synchronizing a clock between a local station and a large country by using a synchronous chronological time stamp (SRTS) method in an ATM network to prevent the causes of underflow or overflow as described above. .

In order to achieve the above object, the present invention provides a network clock generation unit for generating and outputting an ALL1 system clock and an SRTS reference clock signal by inputting a clock signal transmitted from an ATM network, and an SRTS reference clock output from the network clock generation unit. Comparing unit for comparing the received recovery clock signal from the PDH line and outputting the SRTS code difference value, and inputting the SRTS code difference value output from the comparison unit to adjust the actual clock speed by a cross table having a constant value A code conversion unit for converting and outputting a code value, a D / A converter for converting and outputting a code value output from the SRTS code conversion unit into an analog signal, and low-pass filtering the analog signal converted by the D / A converter. A low pass filter for converting and outputting a voltage, and a reception recovery circle corresponding to a voltage output from the low pass filter For generating it is characterized in that it consists of Vcxo.

1 is a reception clock recovery circuit diagram according to an embodiment of the present invention

2 is a detailed circuit diagram of a comparison unit 12 according to an embodiment of the present invention.

3 is an exemplary cross table for converting a code value in the SRTS code conversion unit 16 according to an embodiment of the present invention.

4 to 14 are diagrams illustrating a program for implementing the present invention.

15 is a reception clock recovery circuit diagram according to another embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a reception clock recovery circuit diagram according to an embodiment of the present invention.

The network clock generation unit 10 inputs a clock signal transmitted from an ATM network with the first and second frequency multipliers 22 and 24 connected in series to generate and output an ALL1 system clock and an SRTS reference clock signal. The comparator 12 may be configured with a chip of WAC-021 manufactured and sold by IgT, and compares the SRTS reference clock output from the network clock generation unit 10 with the reception recovery clock signal from the PDH line to output the SRTS code difference value. . The code converter 14 inputs the SRTS code difference value output from the comparator 12, converts the code into a code value for adjusting the actual clock speed by a cross table having a constant value. The D / A converter 16 converts the code value for adjusting the actual clock speed into an analog signal and outputs the analog signal. The low pass filter LPF 18 performs low pass filtering on the converted analog signal and converts the converted analog signal into a voltage. The reception clock recovery unit 20 may be configured as Vcxo, and generates a reception recovery clock corresponding to the voltage output from the LPF 18.

2 is a detailed circuit diagram of a comparison unit 12 according to an embodiment of the present invention.

The SRTS code extractor 30 extracts an SRTS code value from an ATM cell received from an ATM network. The divider 32 divides the reception recovery clock and outputs the divided recovery clock. The counter 34 counts and outputs the SRTS reference clock value. The latch 36 latches the counting value output from the counter 34 into a clock divided from the divider 32 to output an SRTS code value. The adder 38 adds the SRTS code value extracted from the SRTS extractor 30 and the SRTS code value latched out from the latch 36 to output the difference value.

3 is an exemplary cross table for converting a code value in the SRTS code conversion unit 16 according to an embodiment of the present invention.

1 to 3 will be described in detail the operation of the preferred embodiment of the present invention.

The standard of the present invention uses the SRTS (Synchrous Residual Time Stamp) method established by ccitt I.363 / 361 or bellcore. The SRTS code is used to reproduce the original components of the source clock at the receiving end, and is added without modification of the cell size by the AAL1 Cell Fomat corresponding to ATM Rayer 1 and transmitted to the PDH interface AAL1 receiving end of the large country using the ATM network. . It is designed to synchronize the clock of the own station and the station in the synchronous network, and it is performed using the divided clock of SDH 155.52MHz for the network synchronizer. The contents of this technical standard are that the code of SRTS is composed of 4-bit code, and the 4-bit code is loaded on the CSI-Header of a cell made in AAL1 format to extract the SRTS code from the header and compared with the SRTS code generated by the receiving terminal itself. do. At this time, the difference between the clock component of the own station and the oscillator of the station is detected to determine the fast and slow degree of the station clock. According to the degree of fast and slow of the clock, the clock of both stations is synchronized by reducing the difference with the clock of the own station using the PLL. 1 and 2, the first frequency multiplier 22 multiplies the clock received from the ATM network, for example, 19.44 MHz by 2 times and outputs 38.88 MHz. The second frequency multiplier 24 multiplies the clock multiplied by the first frequency multiplier 22, for example, 38.88 MHz by a multiple of 2 and outputs 77.76 MHz. The comparator 12 compares the SRTS reference clock outputted from the first frequency multiplier 22, for example, 77.76MHz, and the received recovery clock signal received from the PDH line, for example 44.736MHz, and outputs an SRTS code difference value. A detailed operation of the comparator 12 outputting the SRTS code difference value will be described with reference to FIG. 2. The SRTS code extractor 30 extracts an SRTS code value from an ATM cell received from an ATM network. The divider 32 divides the reception recovery clock by a predetermined amount and outputs the received recovery clock to the latch 36. The counter 34 counts by the 77.76MHz value of the SRTS reference clock and outputs a 4-bit counting value to the latch 36. The latch 36 latches the 4-bit counting value output from the counter 34 into a clock divided from the divider 32 to output the SRTS code value to the adder 38. The adder 38 adds the SRTS code value extracted from the SRTS extractor 30 and the SRTS code value latched out from the latch 36 and outputs the difference value to the SRTS code conversion unit 14. The code converter 14 inputs the SRTS code difference value output from the comparator 12, converts the code value for controlling the actual clock speed by a cross table having a constant value as shown in FIG. Output For example, when the output value of the code converter 14 is 0010, a new code value 1010 corresponding to the code value for adjusting the actual speed is output to the D / A converter 16. At this time, the D / A converter 16 converts the code value 1010 for adjusting the actual clock speed into an analog signal and outputs the analog signal to the low pass filter 18. The low pass filter LPF 18 performs low pass filtering on the converted analog signal and converts the converted analog signal into a voltage. The reception clock recovery unit 20 generates a reception recovery clock corresponding to the voltage output from the LPF 18 and feeds it back to the input of the divider 32. This operation is repeated to synchronize the clocks of the host and the player.

In one embodiment of the present invention, after comparing the SRTS code value from the ATM cell received from the ATM network in the comparator 12 and comparing the code value generated by the transmitter itself to adjust the clock speed in the code converter 14 The clock is synchronized using a PLL by converting the code value into a code value, and examples of a program for implementing the same are shown in FIGS. 4 to 14.

15 is a reception clock recovery circuit diagram according to another embodiment of the present invention.

It has the same configuration as that of Fig. 1, but further includes a network clock synchronizer 26, a receive clock synchronizer 28, a MUX 29, and a CPU 27. The network clock synchronization unit 26 performs the operation described in FIG. 1 using 38.88 MHz obtained by multiplying the 19.44 MHz clock provided by the ATM network in the first frequency multiplier 22 and 77.76 MHz multiplied by the second frequency multiplier 24 in the second frequency multiplier 24 The clock can be synchronized in the same way. In addition, the receiving clock may be synchronized with the 44.736 MHz clock signal generated from the transmitter framer in the same manner as the operation of SRTS 14 described with reference to FIG. 1. At this time, the CPU 27 selects one of the code converter 14, the network clock synchronizer 26, and the receive clock synchronizer 28 to operate. The CPU 27 selects the MTS 29 to convert one of the three SRTS codes to the D / A converter 16. The clock is output through the same operation as in the aforementioned method. The network clock synchronizing unit 26 synchronizes the reception recovery clock with a clock provided by an ATM network, and the reception clock synchronization unit 28 synchronizes the reception recovery clock with a clock provided from a transmitting end framer of a user (USES). Therefore, the network clock synchronizer 26 and the receive clock synchronizer 28 are the same as those of the code converter 14, but have different input sources. The FPGA50 can be implemented with the 2C15-208S3 manufactured and sold by ATT, USA, and consists of a CPU 27, a code converter 14, a network clock synchronizer 26, a receive clock synchronizer 28, and a MUX 29.

As described above, the present invention generates its own SRTS code to indicate how much phase difference its clock component has from the synchronous clock by using the same clock synchronized between the own station and the large station in the ATM network. At this time, the two generated SRTS codes are generated based on the synchronized clock, so even if they are not connected by physical lines, the two components can be compared to extract the difference components.

In addition, the difference component is extracted by comparing the two components, which indicates how far the local clock is from the synchronous clock, so that the result can be changed to a numerical value so that the outside can be traced by the distance by driving the PLL circuit. There is an advantage in that a synchronization network can be formed even between two separate networks.

Claims (5)

In a network synchronization circuit using SRTS, a network clock generation unit for inputting a clock signal transmitted from an ATM network to generate and output an ALL1 system clock and an SRTS reference clock signal, and an output signal from the network clock generation unit. Comparing the SRTS reference clock and the received recovery clock signal from the PDH line and outputting the SRTS code difference value, and inputting the SRTS code difference value outputted from the comparison unit, the actual clock speed by a cross table having a constant value A code conversion unit for converting and outputting a code value for adjustment, a D / A converter for converting and outputting a code value output from the code conversion unit into an analog signal, and a low pass of the analog signal converted from the D / A converter. A low pass filter for filtering and converting the voltage into a voltage, and a number corresponding to the voltage output from the low pass filter A network synchronization circuit using SRTS, comprising: a reception clock recovery unit for generating a new recovery clock. 2. The apparatus of claim 1, wherein the comparing unit comprises: an SRTS code extracting unit for extracting an SRTS code value from an ATM cell received from the ATM network, a divider for dividing and outputting the reception recovery clock, and the SRTS reference clock value; A counter for counting and outputting the counter, a latch for latching a counting value output from the counter to a clock divided from the divider, and outputting an SRTS code value, and an SRTS code value extracted from the SRTS extracting unit and the latch 36. And an adder configured to add the latched SRTS code value and output the difference value. 3. The network synchronization circuit as claimed in claim 2, wherein the counter is a 4-bit counter. 4. The network synchronization circuit as claimed in claim 3, wherein the SRTS reference clock is 77.76 MHz. 5. The network synchronization circuit as claimed in claim 4, wherein the reception recovery clock is 44.736 MHz.

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