JP3609728B2 - Transmission equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to communication between LANs (Local Area Networks) by Gb (Gbit), for example, ITU-TG. The present invention relates to a transmission apparatus applied to a transmission system which can be performed at a higher speed and a longer distance via an optical transport network (OTN) defined in 709.
[0002]
[Prior art]
The Ethernet based on Gb has a transmission distance limitation, and the length is 1000BASE-LX, which is about 5 km according to the standard. Therefore, in order for the Ethernet connection devices to perform longer distance communication, it is necessary to accommodate the Ethernet signal in the long distance transmission device.
Conventionally, when an IP (Internet Protocol) frame such as Gigabit Ethernet is transmitted over a long distance, a method of accommodating in an SDH (Synchronous Digital Hierarchy) is generally used.
[0003]
In this case: 1. Change clock. Two issues of mapping to frames must be solved.
1. Is a clock that synchronizes signals when an Ethernet signal in which terminals operate asynchronously is accommodated in an SDH that synchronizes with the entire network, or when a signal transmitted by SDH is returned to the Ethernet again. Is to change.
2. Is how to handle excess and deficient data when the transmission rates of Gigabit Ethernet and SDH do not match. For example, a technology that maps a Gigabit Ethernet signal with a bit rate of 1.25 Gbit / s on an optical transmission line to an SDH frame having a different speed (such as 2.48832 Gbit / s, 9.95328 Gbit / s). is there.
[0004]
Conventionally, in order to solve these problems, a method of mapping an IP signal once in an ATM (Asynchronous Transfer Mode) and then mapping it to an SDH frame, Layer 3 (OSI basic reference model layer 3: network layer) The IP frame is once terminated at a higher layer such as), and then accommodated in the SDH frame.
[0005]
[Problems to be solved by the invention]
The conventional method requires intermediate framing processing such as ATM and the termination of the upper layer, and the overhead (useless processing) becomes large, so that the processing circuit becomes complicated and the delay becomes large. There is.
[0006]
[Means for Solving the Problems]
In order to solve the above-described problems, in the present invention, the GbE signal of the gigabit LAN is accommodated in an OTN that is more flexible than SDH, thereby simplifying the tributary framing processing required in SDH and reducing it with a simple circuit. Delayed transmission is possible.
In addition, by using a FIFO (First In First Out) memory, clock transfer is performed in both directions of GbE-OTN, and the transmission rate is adjusted by stuff bits, so that signals can be accommodated in the OTN. In addition, since a signal having exactly the same bit pattern as the input signal is transmitted, 100% transparent transmission is guaranteed, and it is possible to construct a transmission system in which the influence of this signal transfer does not appear at all in GbE. Become.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a schematic configuration of a transmission system to which the transmission apparatus of the present invention is applied.
This transmission system is configured by connecting transmission apparatuses connected to a plurality of gigabit LANs (hereinafter referred to as “GbE”) through an optical transmission network (OTN: Optical Transport Network, hereinafter referred to as “OTN”).
The transmission apparatus comprises a GbE interface connected to the GbE, and GbE-OTN / OTN-GbE clock change means connected to the GbE interface, from a connected OTN interface O TN.
[0008]
The GbE signal input to the transmission apparatus is converted into an electrical signal (optical / electrical conversion) by the GbE interface. Since GbE operates asynchronously with the OTN, the GbE signal is switched to the OTN clock here. At this time, the empty space of 0ch is filled with stuff bits by the stuff bit insertion means. Thereafter, it is handled in the same manner as general 0ch, and after being transmitted to the destination transmission device, it is divided into 0ch.
Then, the transmitted OTN signal is received by the OTN interface, the data / stuff is discriminated, the stuff bit inserted at the transmitting end is deleted by the stuff bit deleting means, and the OTN-GbE clock changing means again performs GbE again. Is output to the gigabit LAN (GbE) via the GbE interface in synchronization with the clock.
[0009]
FIG. 2 shows an explanatory diagram of an embodiment of the GbE-OTN clock changing means.
A signal input from the GbE interface is divided into two paths, one is written in the clock extraction means and the other is written in the FIFO memory. At the time of this writing, the clock for writing synchronization extracted by the clock extracting means is used. Here, the same clock is also output to the stuff bit insertion means, and is used to determine the stuff bit insertion timing and the stuff bit length.
As long as there is no read stop signal, the data written in the FIFO memory is read according to the read synchronization clock provided from the OTN interface.
(The read signal in this case is shown on the right in FIG. 2)
When a read stop signal is input, reading of data from the FIFO memory is stopped, and stuff bits are inserted by stuff bit insertion means (see FIG. 5).
[0010]
FIG. 3 shows an explanatory diagram of Embodiment 1 of the OTN-GbE clock changing means.
A signal input from the OTN interface is first subjected to identification of a stuff bit portion and calculation of a clock frequency of a GbE data portion by a data / stuff bit discrimination means (see FIG. 8) described later.
Thereafter, the signal input to the OTN-GbE clock changing means is divided into two paths, one written into the clock extracting means and the other into the FIFO memory. At the time of this writing, the clock for writing synchronization extracted by the clock extracting means is used. At this time, the stuff bit is not written in the FIFO memory but simply discarded due to the write stop signal from the data / stuff determining means. The data written in the FIFO memory is read according to the read synchronization clock generated by the GbE signal transmission clock generation means that receives the clock frequency control signal from the data / stuff determination means, and is output to the GbE interface. At this time, there is a possibility that the GbE signal transmission clock and the frequency of the GbE clock on the input side to the transmission apparatus do not match within the range of the GbE standard. Therefore, the transmission frequency of the GbE signal transmission clock generation means is adjusted by the clock frequency control signal input from the data / stuff determination means so that both, that is, the reception clock of the transmission side GbE and the transmission clock transmitted to the reception side GbE match. Be controlled.
[0011]
FIG. 4 is an explanatory diagram of a second embodiment of the OTN-GbE clock changing means.
A signal input from the OTN interface is first subjected to identification of a stuff bit portion and calculation of a clock frequency of the GbE data portion by a data / stuff discrimination means (see FIG. 8) described later.
Thereafter, the signal input to the OTN-GbE clock changing means is written into the FIFO memory in synchronization with the OTN clock provided from the OTN interface instead of the write synchronization clock extracted by the clock extracting means of the first embodiment. . At this time, the stuff bit is not written in the FIFO memory but simply discarded due to the write stop signal from the data / stuff determining means. The data written in the FIFO memory is read according to the read synchronization clock generated by the GbE signal transmission clock generation means, and is output to the GbE interface. At this time, there is a possibility that the GbE signal transmission clock and the frequency of the GbE clock on the input side to the transmission apparatus do not match within the range of the GbE standard. Therefore, the oscillation frequency of the GbE signal transmission clock generating means is controlled by the clock frequency control signal input from the data / stuff determining means so that they match.
[0012]
2 to 4, the signal synchronization processing can be performed by the GbE interface and the OTN interface so that the read synchronization clock is 1 / parallel number. (Note that stuff bits are not shown in each signal in FIGS. 2 to 4.)
FIG. 5 is an explanatory diagram of an embodiment of the stuff bit insertion means.
The stuff bit insertion means includes data / stuff determination means, data / stuff selection means, and stuff generation means.
Normally, the data / stuff determining means in the figure is in a state where both the read stop signal and the stuff selection signal are OFF, and the GbE data signal read from the FIFO memory of the GbE-OTN clock changing means is output to the OTN interface. Is done.
[0013]
However, this data / stuff determining means compares the frequency difference and phase difference between the write synchronization clock and the read synchronization clock, and turns on and off the read stop signal and the stuff selection signal according to certain conditions.
While this signal is ON, reading of data from the FIFO memory is stopped, and the data / stuff selection means selects an input (ie, stuff bit) from the stuff generation means according to this signal and outputs it to the OTN interface. .
The stuff generation means generates a bit pattern that does not appear in the original data, thereby making it possible to easily identify the stuff bits in the data / stuff determination means.
[0014]
In this way, after the stuff bit is inserted between the data, when the read stop signal and the stuff selection signal are turned OFF, the data read from the FIFO memory is output to the OTN interface again.
FIG. 6 is an explanatory diagram of Example 1 of the data / staff determining means.
This is a method in which the data length is fixed and the staff length is variable.
The data / stuff determining means comprises a bit counting means, a phase comparing means, and a stuff insertion determining means.
[0015]
The bit counting means counts the number of bits of data read from the FIFO memory by counting the read synchronization clock, and turns on the stuff insertion start signal when this exceeds a predetermined threshold value. .
Upon receiving this signal, the stuff insertion determining means turns on the read stop signal and the stuff selection signal.
On the other hand, the phase comparison means inputs the stuff insertion start signal, the write synchronization clock, and the read synchronization clock, and compares the phase difference between the write synchronization clock and the read synchronization clock to thereby determine the length of the stuff bit to be inserted. When a necessary stuff bit is inserted, the stuff insertion stop signal is turned ON.
[0016]
The stuff insertion determining means receives the stuff insertion start signal and the stuff insertion stop signal, and outputs a read stop signal and a stuff selection signal.
The data / stuff selection means selects and outputs the output data of the FIFO memory or the stuff generated by the stuff generation means according to the stuff selection signal.
FIG. 7 shows an explanatory diagram of Embodiment 2 of the data / staff determining means.
This is a method of variable data length and fixed staff length.
The data / stuff determining means comprises a bit counting means, a phase comparing means, and a stuff insertion determining means.
[0017]
The bit counting means counts the read synchronization clock and outputs a stuff (+1) signal every time it exceeds a certain number. When the staff insertion determination means receives this signal, it increments the internal counter by +1. When the counter exceeds a certain threshold, the read stop signal and the stuff selection signal are turned ON only for a certain number of bits.
On the other hand, the phase comparison means compares the phase difference between the write synchronization clock and the read synchronization clock, and outputs an insertion stuff signal, a stuff (+) signal, or a stuff (−) signal.
[0018]
The staff insertion judgment means outputs a staff selection signal for adjusting the length of the staff to be inserted by this signal.
The data / stuff selection means selects and outputs the data and the staff generated by the staff generation means in accordance with the staff selection signal.
FIG. 8 is an explanatory diagram of an embodiment of the data / staff discrimination means.
The data / stuff determining means is composed of a staff identifying means and a clock frequency arithmetic circuit.
[0019]
A signal input from the OTN interface is branched into two, one being sent to the OTN-GbE clock changing means and the other being sent to the data / stuff determining means.
The stuff identification means identifies the stuff, and when the input signal is stuff, turns on the write stop signal and outputs it to the OTN-GbE clock changing means, and outputs the data / stuff identification signal to the clock frequency arithmetic circuit.
In the clock frequency arithmetic circuit, the number of bits of data and stuff is counted based on the clock of the signal input from the OTN interface, the synchronization frequency of the original GbE signal is obtained from the ratio of both, and the GbE of the OTN-GbE clock changing means is obtained. A clock frequency control signal is output to the signal transmission clock generation means.
[0020]
The stuff bit deleting means is configured by prohibiting writing of the stuff bit into the FIFO memory by the data / stuff determining means and the write stop signal which is the output signal.
FIG. 9 shows an explanatory diagram of Embodiment 3 of the OTN-GbE clock changing means.
When the clock stop means receives the write stop signal, it blocks the write synchronization clock output from the clock extraction means, thereby stopping the writing to the stuff FIFO memory. The phase of the signal that has the write clock 1 / n (n: integer) by the counting means and the signal that the output of the GbE signal transmission clock generating means (that is, the read synchronization clock) is 1 / n by the counting means The phase comparator compares the outputs, drives a voltage controlled oscillator (VCO) through a filter (FIL: Filter), multiplies the output of the VCO by n, and outputs a read synchronization clock. In this way, the read synchronization clock is controlled. (The control of this read synchronization clock is described in “Edited by Yoshiharu Shigei, Electronic Engineering Progress Series 7 High-Speed PCM Corona, 1975, page 139, FIG. 3”.)
[0021]
【The invention's effect】
Since the present invention is configured as described above, conventionally, instead of transmitting an Ethernet signal after being accommodated in SDH and converting it again to an Ethernet signal, a highly flexible OTN is used. As a result, the circuit can be simplified and the delay time can be shortened. In addition, clock transfer is performed in both directions of GbE-OTN using a FIFO memory, and the transmission rate is adjusted by stuff bits, so that signals can be accommodated in the OTN. In addition, since a signal having exactly the same bit pattern as the input signal is transmitted, 100% transparent transmission is guaranteed, and it is possible to construct a transmission system in which the influence of this signal transfer does not appear at all in GbE. Become.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a transmission system using a transmission apparatus of the present invention.
FIG. 2 is an explanatory diagram of an embodiment of the GbE-OTN clock changing means of the present invention.
FIG. 3 is an explanatory diagram of a first embodiment of the OTN-GbE clock changing means according to the present invention.
FIG. 4 is an explanatory diagram of a second embodiment of the OTN-GbE clock changing means according to the present invention.
FIG. 5 is an explanatory diagram of an embodiment of stuff bit insertion means of the present invention.
FIG. 6 is an explanatory diagram of Example 1 of data / staff determining means of the present invention.
FIG. 7 is an explanatory diagram of Embodiment 2 of the data / staff determining means of the present invention.
FIG. 8 is an explanatory diagram of an embodiment of the data / staff discrimination means of the present invention.
FIG. 9 is an explanatory diagram of Embodiment 3 of the OTN-GbE clock changing means according to the present invention.

Claims (6)

I EEE Gigabit LAN as defined in 802.3z (hereinafter referred to as "GbE") and a signal interface, a large capacity of optical transport network than LAN as defined in ITU-T G.709 (OTN: Optical Transport Network, (Hereinafter referred to as “ OTN ”)
Equipped with stuff bit insertion means to insert stuff bits to fill the free space when accommodating the GbE signal received from the GbE interface in the OTN, and the GbE-OTN clock that is output to the OTN interface by switching to the OTN synchronization clock Changing means,
Equipped with stuff bit deletion means for deleting stuff bits of the OTN signal received from the OTN interface, and composed of OTN-GbE clock change means for changing to the GbE clock,
The GbE-OTN clock changing means is
A GbE clock extraction means for extracting a clock from the GbE signals,
The GbE signal is written in synchronization with the GbE clock of the GbE clock extraction means, and is provided with a FIFO memory that is synchronized with the OTN clock and is read by a read stop and restart signal generated based on the stuff bit insertion signal of the stuff bit insertion means ,
The stuff bit insertion means includes
Stuff generation means for generating a bit pattern that does not appear on the GbE transmission line code;
Input the synchronization clock for writing generated by the GbE-OTN clock switching means and the readout synchronization clock output from the OTN interface, and the readout stop signal that stops the readout when the preset number of data is read is obtained. Data / stuff determining means for outputting a tough selection signal instructing insertion of a stuff bit length to be inserted;
And data that was changed placed on the OTN clock inputs the two staffs which is an output of the staff generating means, and a data staff selection means for outputting either one of data or stuff only to the OTN interface by staff selection signal ,
A transmission apparatus characterized in that an input GbE signal is accommodated in an OTN and transmitted, and a signal received from the OTN is output as a GbE signal. The transmission apparatus according to claim 1 ,
OTN-GbE clock transfer means is
OTN clock extraction means for extracting the OTN clock from the OTN signal;
Clock frequency to identify the stuff signal of the OTN signal, generate a write stop signal, and match the reception clock of the transmission side GbE and the transmission clock of the reception side GbE based on the data / stuff identification signal of the OTN clock and the OTN signal Write stop / clock frequency control signal generating means for generating a control signal;
GbE signal transmission clock generating means for changing and outputting a clock frequency for GbE signal transmission by the clock frequency control signal;
A transmission apparatus comprising: a FIFO memory that synchronizes an OTN signal with an OTN clock of an OTN clock extracting means, writes an OTN signal by writing stop and restart by the write stop signal, and reads in synchronization with a GbE signal transmission clock. The transmission apparatus according to claim 1 ,
OTN-GbE clock transfer means is
Clock frequency to identify the stuff signal of the OTN signal, generate a write stop signal, and match the reception clock of the transmission side GbE and the transmission clock of the reception side GbE based on the data / stuff identification signal of the OTN clock and the OTN signal Write stop / clock frequency control signal generating means for generating a control signal;
GbE signal transmission clock generating means for changing and outputting a clock frequency for GbE signal transmission by the clock frequency control signal;
A transmission apparatus comprising: a FIFO memory that synchronizes an OTN signal with an OTN clock, writes an OTN signal by writing stop and restart by the write stop signal, and reads in synchronization with a GbE signal transmission clock. The transmission apparatus according to claim 1 ,
Data / staff decision means
A bit counting means for inputting a read synchronization clock output from the OTN interface, and outputting a stuff insertion start signal when the number of clocks exceeds a set fixed value;
The write synchronization clock output from the GbE-OTN clock transfer means and the read synchronization clock output from the OTN interface are input, the phase of both is compared, and the threshold value with the absolute value of the phase difference is set. Phase comparison means for outputting an insertion stuff number control signal when exceeding,
The stuff insertion start signal and the insertion stuff number control signal are input. When the stuff insertion start signal is “1”, the stuff selection signal is set to “1”, and simultaneously the read stop signal is output as “1” to control the number of insertion stuffs. If the signal is “+1”, the number of stuffs is increased. If the signal is “0”, the number of stuffs is not changed. A transmission apparatus characterized by that. The transmission apparatus according to claim 1 ,
Data / staff decision means
A bit counting means for inputting a read synchronization clock output from the OTN interface and outputting a stuff (+1) signal when the number of clocks is exceeded and exceeds a predetermined value,
The write synchronization clock output from the GbE-OTN clock transfer means and the read synchronization clock output from the OTN interface are input, the phase of both is compared, and the threshold value with the absolute value of the phase difference is set. Phase comparison means that outputs a stuff (± 1) signal when exceeded,
The stuff (+1) signal of the bit number counting means and the stuff (± 1) signal of the phase comparison means are input. If the stuff (+1) signal is “1”, the counter is increased. The stuff insertion judgment means for reducing the stuff selection signal to 1 and setting the stuff selection signal to '1' when the counter exceeds a set threshold value, and outputting a stuff selection signal for holding a stuff selection / read stop state by a certain number of bits. A transmission apparatus comprising: The transmission apparatus according to claim 1 ,
Staff deletion means
Pattern matching is performed on the signal output from the OTN interface, and when a bit pattern not included in the GbE transmission line code appears, the write stop signal is set to “1”, and the data and stuff in the input signal from the OTN interface And a data / stuff discrimination means for outputting a clock frequency control signal for matching the reception clock of the transmission side GbE and the transmission clock of the reception side GbE according to the ratio of the two.

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