KR0145178B1 - Independent clocking local area network nd nodes used for the same - Google Patents

Abstract

A plurality of nodes having extracting means for extracting the received clock signal, frame generating means, means for reproducing the synchronous clock signal, synchronizing means, and means for embedding the change point position into the specific region within the frame as the change point position information of the sync clock signal As an independent synchronous local area network consisting of devices and transmission lines, the number of nodes is limited by the number of jitter, the system is weak in transmission errors on the transmission path, the physical transmission speed is larger than the logical transmission speed, and the frame processing is complicated. To solve this problem, a clock source generating an independent clock signal at each node, means for forming a fixed length frame based on the oscillation frequency of the clock source, means for extracting a clock received at each node, and received information. Storage means for temporarily storing, one when the amount of information stored in the storage means becomes larger than a first predetermined reference value Increase the amount of information sent out into the frame and, when the amount of information stored in the storage means becomes smaller than the reference value of the predetermined second, to establish the information songchulryang control means for reducing the amount of information to be sent into one frame. It is possible to configure a multi-media LAN that can control jitter of the synchronous clock to a level that does not cause jitter accumulation on the transmission clock, and can use internationally standardized fixed-length frames. It is possible to realize LAN with the same physical transmission speed and logical transmission speed.

Description

Independent Synchronous Internal Communication Network and Node Device Used in It

1 is a block diagram of one embodiment of an independent synchronous LAN according to the present invention;

2 is a diagram showing the usage of the multi-media LAN.

3 is a frame diagram used in a LAN of the present invention.

4 illustrates the structure of section overhead in a frame.

5 is a block diagram showing a configuration of a node constituting a LAN of the present invention.

6 shows the signal structure of the clock pointer used in the LAN embodiment of the present invention.

7 is a pattern diagram of a synchronization clock reproduced in an embodiment of the present invention.

8 is a block diagram of a synchronous clock generation circuit in an embodiment of the present invention.

9 is a block diagram of a clock pointer generation circuit in an embodiment of the present invention.

10 is a waveform diagram illustrating a jitter generating mechanism in the case of a synchronous clock relay.

11 and 12 are block diagrams of stuffing parts in a master node according to an embodiment of the present invention.

13 is a distribution chart of the SOH region in the stuffing buffer input and output.

14 is a block diagram of a stuffing control unit in a general node.

15 is a frame format diagram of a conventional FDD-I.

* Explanation of symbols for main parts of the drawings

1: transmission path 2-1 ~ 2-13: node

5-1, 5-2: PBX 6-1 ~ 6-3: RSU

7-1, 7-2: Image device 12, 16: Path

9: external clock 10: PLL

14-8 to 14-11: stuffing buffer

The present invention is referred to as an independent synchronous local area information network, that is, a local area network (hereinafter referred to as a local area network) in which each node device has an independent clock source of a clock signal and is transmitted using a clock signal from which the information signal is oscillated. In particular, the present invention relates to a structure of a multi-media LAN in which data transmission errors due to jitter accumulation do not occur even when the number of connected node devices increases.

In a LAN, a plurality of node devices (hereinafter simply referred to as nodes) are connected to each other in a single transmission path, and high-speed information transmission and exchange functions are efficiently executed within a limited service area, and various types of LANs are provided. This has been put to practical use. Representatively, a ring LAN having a ring-shaped transmission path and a bus-type LAN having a bus-shaped transmission path are known. In such a LAN structure, a synchronous system becomes a problem. Ideally, all of the nodes constituting the LAN are preferably operated with the same clock signal (hereinafter simply referred to as a clock). When all nodes operate with the same clock, the information transmission speed and the information reception speed must be the same. Therefore, it is possible not to use a buffer for transmitting and receiving information. As such, a standard IEEE 802.5 (token ring) (Document ANSI / IEEE std 802.5-1985 ISO / DP 8802/5 Local Area Networks Token Ring Access Method) is known as a LAN in which all nodes operate at the same clock. In each node of the standard IEEE 802.5, the clock component included in the signal received at the previous (transmission) node is reproduced by means of a phase locked loop (PLL), and the reproduced clock is supplied into the receiving node. Information is sent to the next node by the reproduced clock (dependent synchronization). The clock for synchronization is relayed at each node as described above to round the ring, so that the entire system operates in synchronization with the synchronization clock generated by the master node. However, since the clock is reproduced and relayed at each node, jitter generated during the reproduction and relay of the clock is accumulated. Since the received data is reproduced by a clock having such jitter, a problem arises that the received data is not reproduced correctly when the jitter becomes large. This accumulation of jitter often limits the number of nodes that can be operationally accessed.

In order to prevent such accumulation of jitter, a system (independent synchronous system) is proposed in which clock reproduction and relaying are not executed, each node has its own independent clock source, and an information signal is transmitted using an oscillated clock. It became. For example, this system is described in detail in specification FDDI-I (Document ISO / IEC JTC1 SC13 N477: Draft for ISO 9314-1: Fiber Distributed Data Interface (FDDI) Token Ring Physical Layer Protocol (PHY)).

However, in FDD-1, only the information signal transmitted from LAN is asynchronous information, that is, information that does not need to be transmitted periodically, and the information is a frame for transmitting information (hereinafter simply referred to as a frame, which is a maximum of 4,500 bytes). Is transmitted and received as a unit. 8 or more bytes of space are inserted between the frames, and the difference in clock frequency between nodes is absorbed by increasing or decreasing the size of the space. Therefore, each node can communicate with each other without causing overflow or underflow by reproducing and relaying only data.

The independent synchronous system described above is a system applicable only to a LAN that supplies only asynchronous data. However, a representative example is not only asynchronous data but also synchronous information (information, voice, and data that need to be periodically transmitted a predetermined amount in recent years. Although this may be taken as asynchronous information, buffer processing is performed in order to guarantee periodicity in a transmitting and receiving terminal. The need for a high-speed LAN, referred to as a multimedia backbone LAN, which can also be transmitted and exchanged, is increasing. The multi-media backbone LAN accommodates low-speed asynchronous data-only LANs such as IEEE 802.3, 802.4, and 802.5, and FDD-I, a high-speed LAN, to realize information transfer and exchange between LANs. In order to achieve this, information transmission is supported between synchronization system devices such as PBX (premises exchange) and TDM (time division multiple device). Conventional synchronization system devices are designed on the premise that they operate at the same synchronization clock when interconnected. Therefore, in a network including such a synchronization device, it is necessary to supply the synchronization clock to the synchronization device via a node in the network.

In addition, since information must be transmitted periodically and at the same speed between the synchronization system devices, it is desirable to make the amount of information applied to each node the same in the entire system. Therefore, it is necessary to supply a synchronous clock common to all nodes.

As a result, an easy-to-configure slave synchronization system was used for synchronization of the multi-media LAN. As for such a technique, Al. 2 Gbps optical LAN for wideband office communication is described in the literature of the IEEE Gloal Telecommunication Conference 1985.15-4.

In the LAN of the slave synchronization system described above, the synchronization clock is distributed by the fact that the clock generated by the master node is reproduced and relayed by each node. In this system, since all nodes operate with a common synchronous clock, it is easy to connect synchronous devices. However, since jitter accumulates as described above, there is a problem in that the number of nodes that can be connected is limited.

In this multi-media LAN, an independent synchronization system has been proposed in which each node transmits a signal to a transmission path using a clock oscillated at each station as another method for solving the problem of jitter accumulation. However, it is necessary to study how such a multi-media LAN includes a synchronous device different from an asynchronous data-only LAN. For example, the standard FDDI-II (Draft Proposed American Standard, January 20, 1989), currently being standardized by the American National Standards Institute (ANSI), is considering using an independent synchronization system. . FIG. 15 shows the structure of a transmission frame (referred to as a cycle in FDDI-II) employed in FDDI-II. The information is inserted in a transmission frame of a fixed period and transmitted. The frame consists of a preamble, a cycle header, and an information part. The period of the frame is 125 ㎲ (1/8 KHz). The information transmission speed is 100 Mb / s, but 4 bits of information are converted into 5 bits for transmission of DC frequency components on the transmission path and transmission of special codes (for frame detection and control signals). do.

Therefore, the physical transmission rate is 125 Mb / s. Although the number of bits in the preamble region varies depending on the oscillation frequency deviation of the clock of each node, the number of bits is adjusted so that the cycle period is 125 kHz. The master node generates a frame period according to the oscillation frequency of the external clock or the local station. At each node, the synchronous clock is extracted from the received signal using a PLL, a tank circuit, or the like. By using the extracted clock to accurately receive the received signal and detecting the synchronization pattern in the cycle header, it becomes possible to receive the information in the frame.

In the above-described FDDI-II standard, the oscillation frequency deviation of each node is adjusted by adjusting the length of the preamble portion between frames, and periodic data transmission is realized by introducing a frame structure.

As described above, the multi-media LAN needs to distribute the same synchronization clock between the synchronization system devices through the node in order to transmit not only asynchronous information but also synchronization information. Therefore, there is a problem in both of the above-described slave synchronization system and independent synchronization FDDI-II system as the synchronization system. That is, in the dependent synchronization system, the limitation of the number of nodes due to the jitter accumulation described above becomes a problem.

The FDDI-II system has the following problems.

The first problem is that the system is weak in transmission error on the transmission path. In high-speed LAN, optical fiber is used for transmission, but the bit error rate in optical transmission is usually about 10 ^-9 .

Bit errors generated in such random or burst shapes will not be magnified by the network. In the FDDI-II system, the start position of each frame is recognized by detecting a specific bit pattern that does not exist in the information, and an error of one frame may occur due to a bit error in this portion.

In addition, the length of the output frame is determined by the length of the frame received at each node, and there is a possibility that a frame recognition error of one node is extended to a plurality of nodes.

The second problem is that the physical transmission rate is larger than the logical transmission rate. This is because the use of a specific bit pattern that does not appear in the information portion through frame recognition, so that 4-bit information is transmitted after being encoded with a 5-bit transmission code. In FDDI-II, the physical transmission rate is set to 125Mb / s for the information transmission rate 100Mb / s, and only 80% of the transmission band is used for actual information transmission.

A third problem is that frame processing is complicated because the frame is of variable length.

An object of the present invention is to solve the above-mentioned problems, i.e., a standalone premises network and premises node for distributing synchronous clocks among synchronous devices even when a frame having a small jitter and a fixed length is used. To provide.

In order to achieve the above object, according to the present invention, in the premises information communication network consisting of a transmission line for interconnecting a plurality of lower networks including a synchronization system device, a plurality of nodes connecting the lower network to the transmission line, Information is transmitted using a fixed length frame, and a clock source for generating an independent clock signal at each node and a means for forming a fixed length frame based on the oscillation frequency of the clock source are provided to use an independent synchronization system. The distribution of common synchronous clocks required for the mechanism allows the change point position information of the synchronous clock to fit in a specific area in a fixed length frame within the transmission. The change point position information means that a reference point such as a start point or an end point of a clock during the period of a transmission frame having a fixed length formed by each node is temporal position information. Since each node has an independent clock, the period of the fixed length transmission frame formed by each node and the period of the common synchronous clock are independent so that the change point position information is varied at each node.

In addition, since each node needs to generate a fixed length transmission frame with an independent clock signal and make the amount of information applied to the network constant, a means for extracting a clock received in each nude, and temporarily storing the received information. Storage means for increasing the amount of information sent into one frame when the amount of information stored in the storage means becomes larger than the first predetermined reference value and into one frame when the amount of information stored in the storage means becomes smaller than the predetermined second reference value. An information sending amount control means for reducing the amount of information to be sent is provided.

As a configuration of the preferred embodiment, a common sync clock is sent from the master node. In addition, a Network Node Interface for the Synchromous Digital Interface (NNI) standard specified by the International Telegraph and Telephone Consultative Committee (CCIT) standard is used for the physical layer. In particular, a SONET (Synchronous Optical Network) frame is used as the fixed length frame, and the change point position information on the common synchronous clock is transmitted using the section overhead area of the SONET frame.

The clock frequency of each node is independent (independent synchronization), and the speed of transmitted information is common in the whole system. Therefore, the NNI-based stuffing function is used to absorb the difference between the node clock frequency and the information transmission speed at each node. The sync clock is distributed by setting an overhead portion of the NNI reference, i.e., a sync clock period to be distributed at a frequency approximately equal to the frame frequency and transmitting change point position information of the sync clock.

According to the present invention, the problem of data transmission error due to clock jitter accumulation is solved by making clock frequencies of each node independent. In addition, the use of the NNI standard, which is an international standard for the physical layer, makes it possible to use connectivity and technology with public networks. In addition, frame synchronization can be obtained by using a fixed-length frame even when a specific pattern for frame synchronization is not used. That is, even if the same pattern as the pattern for frame synchronization is used in the information unit, the frame synchronization pattern appears periodically, so that the frame start position can be recognized by detecting the periodicity. Therefore, the physical transmission rate and the information transmission rate can be made almost equal to each other.

In addition, independent synchronization can be realized by using the NNI-based stuffing function. That is, each node is monitored for the difference between its own node clock and the amount of information of all nodes, and the stuffing is performed in the direction of decreasing the difference when the secondary exceeds the prescribed threshold, whereby the clock frequency at each node is increased. While maintaining independently, the amount of information applied to the transmission line can be kept constant. The information rate applied to the transmission line by the master node is specified. In addition, distribution of the common synchronization clock required for the synchronization system device is made possible by transmitting the change point position information of the synchronization clock using the control information transmission area (NNI reference overhead area). When the distributed sync clock frequency is set to be close to the frame repetition frequency, the number of sync clock change points in one frame becomes one of zero, one, or two. Therefore, the synchronization clock can be distributed by providing an area capable of transmitting two change point information into the control information area. Further, by synchronizing the amount of information applied in the LAN to the synchronization clock and supplying the synchronization clock to the synchronization system device, it is possible to prevent the overflow or underflow of the synchronization information at the node.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

EMBODIMENT OF THE INVENTION Hereinafter, the structure of this invention is demonstrated with an Example.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

1 and 2 show the configuration of a multi-media LAN in an embodiment of an independent synchronous LAN according to the present invention.

FIG. 1 illustrates a part of FIG. 2 in detail for convenience of description.

In the multi-media LAN shown in FIG. 2, the nodes 2-1 to 2-13 are connected in a ring shape to the transmission line 1. The transmission line 1 is an optical fiber and the transmission speed is 155.52 Mb / s. CCITT's NNI standard specifies the transmission rate and frame format of the physical layer. That is, the transmission rate is 155.52 Mb / s. The frame format of the NNI will be described with reference to FIG. 3 later. A synchronization device and a synchronization device can also be connected to the multimedia LAN. In Fig. 2, PBXs 5-1 and 5-2, remote units (RSU) 6-1, 6-2 and 6-3 of the PBX, image device (7-1) and (7-2), a multiplexing device (MUX) 3-1, (3-2) and (3-3), which communicate with a remote over a high-speed digital line, is connected as a synchronization device. . These devices are connected to each other via a channel that guarantees periodic information transmission. On the other hand, FDDI-I (4-1), (4-2), (4-3) and (4-4), which are LANs as asynchronous devices, are nodes (2-3) and (2-13) of a multi-media LAN. Is directly connected to the transmission line 1 via (2-4) and (2-12). The workstations WS, the computers HOST, CCP, and the like are directly connected to the FDDI-I (4-1) to (4-4) or via low speed LANs such as IEEE 802.3, 802.5, and the like. It is also possible to accommodate this directly in the node. Multiplexing devices commonly used for synchronous and asynchronous devices may be used. In a multi-media LAN, since a plurality of synchronous and asynchronous devices are connected at high speed to each other, information transmission and exchange between the devices can be performed.

3 shows the structure of a frame transmitted to a LAN.

The frame is the same as a SONET frame that satisfies the NNI criteria, consisting of 270 rows and 9 columns, and 2,430 bytes (270 × 9) are transmitted about every 125 Hz (depending on the oscillation frequency of the node). Therefore, the transmission frequency is about 155.52 MHz. Of the 270 rows in the frame, the first nine rows are the section overhead (hereinafter referred to as SOH) areas and are used for control and transmission of control information between nodes.

The remaining area is used for information transfer. In order to keep the information transfer rate in the multi-media LAN independent of the frequency of the node clock, the information is transferred using a 2,349 (261 x 9) byte block called the virtual container 4 (hereinafter referred to as VC-4). Is sent. The positional relationship between the VC-4 and the frame does not need to be fixed, and the positional relationship varies according to the difference in the speed of the information transmitted on the node clock and the transmission line. That is, the start position of VC-4 can be set at any position (3 byte units) of the information part in a frame.

4 shows the SOH region in detail. For example, A1 and A2 represent a synchronization pattern, and the start position of the frame is detected by periodic detection of A1 and A2 (frame period is constant).

In addition, since frame synchronization patterns A1 and A2 appear periodically, error synchronization according to bit errors generated in transmission by determining (synchronization protection) a synchronization error by not detecting several synchronization patterns after frame synchronization is established. It is possible to prevent other occurrences.

The AU pointer (including stuffing area) in the fourth row of SOH indicates the starting position of the VC-4. In the information transfer section in the frame, addresses are added in units of 3 bytes from the fourth row and the tenth column, and the address of the start position of VC-4 is included in the AU pointer. Therefore, the starting position of VC-4 can be found by looking at the AU pointer. When the relative position between the frame and the VC-4 is changed (called stuffing), the seventh to twelve columns of the fourth row are used. There are two types of stuffing: positive stuffing and negative stuffing, so that the difference in speed can be properly compensated according to the magnitude of the frame repetition rate and information transmission rate determined by the clock frequency of the node. Used. When the frame repetition rate of the node is large, it is necessary to move the head of VC-4 in the direction in which the head address increases with respect to the frame. Thus, the fourth row and ten

When the frame repetition frequency is smaller than the information transmission rate, the head position of the VC-4 is changed by transmitting information using the fourth row and the seventh to ninth columns (negative stuffing). That is, the difference between the frame repetition rate and the information transmission rate can be adjusted by varying the size of the information transmission region in one frame.

The occurrence of stuffing is notified to the downstream node by changing the value of the pointer. The deviation between the frame repetition rate and the information transmission rate is defined as the allowed stuffing frequency. According to the NNI criteria, stuffing can only be performed once in four frames, allowing three bytes of variation in four frames. Therefore, the node clock frequency deviation of each node must be within ± 309 ppm (= 3 / (2,430 × 4)) with respect to the information transmission rate. In FIG. 4, D1 to D12 represent a 12-byte data area called a data communication channel and are used for transmission of control information between nodes. In this embodiment, the change point position information of the sync clock is transmitted using this area. The bytes B1, B2, C1, E1, E2, F1, K1, K2, Z1, and Z2 are irrelevant in the description of the present invention, and thus the detailed description thereof is omitted.

Referring back to FIG. 1, information transmission and clock distribution in the multimedia LAN will be described. In FIG. 1, only nodes (2-8) to (2-11) of FIG. 2 are shown, and the rest are omitted. The interface unit with the device connected to the node is shown only for the nodes 2-9. 2-8) is a master node, and supplies a common synchronization clock (8 KHz) to other nodes In Fig. 1, the path 12 is a distribution path of the synchronization clock, and the path 16 is an information transmission path. On the physical side, the two paths are multiplied and transmission is performed using a single transmission path In a multi-media LAN, the externally supplied external clock 9 (8KHz) is a common synchronization clock. It is distributed to the nodes 2-8 to 2-11, and supplied from each node to the synchronization terminal connected to the node, and outputting VC-4 in synchronization with the external clock 9. The information transmission rate is determined, and each of the nodes 2-9 to 2-11 transmits the common synchronization clock information from the master node 2-8 to the relay device 11-9. (11-11) or relaying to the next node by the relay device In each node, the clock jitter generated at the time of clock relay by the phase-locked loop 13-9 (omitted for other nodes) is And the synchronization clock is supplied to the synchronization system 7-2. Each node has its own oscillators 15-8 to 15-11, and the frame clock is generated by the oscillated node clock. And sends it to the next node The stuffing buffers 14-8 and 14-11 are used to absorb the difference between the receive frequency and the transmit frequency.

If the amount of information stored in the buffer varies by more than ± 3 bytes from the median of the buffer capacity, stuffing is performed and the amount of information applied to the ring is adjusted to be constant over the entire LAN. The synchronization clock information arrives at the node almost periodically, but is not completely synchronized with the synchronization clock distributed within a short time due to the effect of stuffing. Therefore, this change part is controlled by the delay control circuit 16-9. It is necessary for the master node 2-8 to have a function of controlling the delay such that the delay around the ring is an integer multiple of the frame period so that no information defect occurs during relaying. Usually, a buffer having a capacity of about one frame is provided separately from the stuffing buffer (for example, Japanese Patent Publication No. 61-44426). For simplicity of explanation, FIG. 1 illustrates this function in the stuffing buffer 14-8.

5 illustrates the structure of nodes 2-9 in FIG. 1 in detail.

The same parts as those shown in FIG. 1 use the same reference numerals. The nodes 2-9 are divided into three regions of dashed lines A, B, and C according to the type of clock used. The area A is operated by the reception clock reproduced by the optical receiver 21 in the received data.

The area B is operated by the self node clock supplied from the clock source 15-9 included in the node. Area C is operated by the synchronization clock supplied from the master node. Although the transmission frequency is 155.52 MHz, information is processed in units of 1 byte in the node. Therefore, in the node, the frame synchronization circuit 22 is operated with a clock of 19.44 MHz, which is 1/8 of the transmission frequency 155.52 MHz. Therefore, the oscillation frequency of the clock source 15-9 of the node is 19.44 MHz.

The optical signal received in the area A is converted into an electrical signal in the optical receiver 21, and the transmission clock (155.52 MHz), that is, the clock of the upper node is extracted as the received clock. The extracted reception clock is supplied to the frame synchronization circuit 22, the multiple separation / SOH extraction circuit 23, and the clock generation circuit 26 in the area A. The starting position of the frame is detected in the frame synchronizing circuit. The multiplexing / SOH extraction circuit 23 converts the signals of 155.52 Mb / s in parallel and in parallel to the unit of 19.44 MHz, and extracts the SOH portion of the received frame.

The elastic buffer 24 in the area B is used to absorb the frequency difference and the phase difference between the received (transmit) clock and the node clock. The portion of VC-4 in the received frame information is written into the elastic buffer 24 in units of bytes. Information for indicating the head of VC-4 is also written at the same time. The access control circuit 25 monitors the empty state of the elastic buffer 24 and synchronizes the VC-4 data with the node clock by reading the data using the node clock in bytes when the VC-4 data exists. Let's do it. Since the amount of information in the VC-4 is 261/270 of the amount of information in the frame (see Figure 3), if the node clock frequency deviation is controlled to within 3.8% (actually, the frequency deviation is set to 308 ppm to prevent overflow of the stuffing buffer). ). Overflow of the elastic buffer 24 does not occur.

The access control circuit 25 also relays information and exchanges information with the synchronous and asynchronous devices connected to the node. As a method for transmitting synchronous and asynchronous information, a time division system for dividing the interior of the VC-4 into two areas for synchronous information transmission and asynchronous information transmission, and for dividing the VC-4 into an area called a slot, The dividing method (slotting) is used for asynchronous information. In addition, as a system for accessing a ring of asynchronous information, various techniques are known (see, for example, David C. Flint, The Data Ring Main: An Introduction to Local Area Network), and any method can be applied. The present invention mainly relates to the structure of a physical layer.

Therefore, the description of the access system to the ring is omitted. The synchronizing device includes an access control circuit via a synchronizing device interface 30, a synchronizing buffer 28 for receiving data, and a synchronizing buffer 29 for transmission data (corresponding to (16-9) shown in FIG. 1). 25). The synchronizing device interface 30 terminates the protocol of the synchronizing device and converts it into the information format in the ring. In addition, the synchronization buffers 28 and 29 for the reception and transmission data are used to absorb phase differences and instantaneous frequency differences between common synchronization clocks and node clocks. The synchronization system interface 30 belongs to the area C and operates as a common synchronization clock.

On the other hand, although the asynchronous device is connected via the non-machine device interface 31, it is not necessary to guarantee the periodicity of information transmission.

Therefore, the asynchronous system interface 31 is operated by the node clock like the access control circuit 25.

At the node 2-9, information is sent in the frame period defined by the node clock. Therefore, the amount of information that the VC-4 can transmit is generally different from the amount of information of the VC-4 input to the node 2-9. The stuffing function is used to absorb the difference in the amount of information.

± 3 바이트로 설정한 경우, 스터핑 버퍼의 내에 축적된 정보의 용량이 스터핑 버퍼 용량의

+ 3 바이트를 넘은 경우에는 네가티브 스터핑을 실행하며, 1프레임 내에 전송할 수 있는 정보량을 증가시켜서 조정한다.The output of the access control circuit 25 is written to the stuffing buffer 14-9 in units of bytes. The stuffing control / frame generation circuit 33 generates the frames described with reference to Figs. The stuffing is executed when the amount of information in the stuffing buffer 14-9 is monitored and the predetermined threshold value is exceeded. For example, the threshold value of the stuffing buffer capacity

When set to ± 3 bytes, the amount of information accumulated in the stuffing buffer is equal to the amount of stuffing buffer capacity.

If it exceeds +3 bytes, negative stuffing is performed and the amount of information that can be transmitted in one frame is increased.

- 3 바이트를 하회하는 경우에는 포지티브 스터핑을 실행하여, 1프레임 내에 전송 가능한 절보량을 감소시켜서 조정한다. 상술한 바와 같이 스터핑 버퍼(14-9)의 오버플로우, 언더플로우를 발생시키지 않기 위해서는 노드 클럭의 주파수 편차를 ± 308ppm 이내로 할 필요가 있다. SOH 삽입 다중(MUX) 회로(34)는 SOH 정보를 삽입하고 바이트 단위의 정보를 다중하여, 155.52 Mb/s 의 정보로 한다. 노드 클럭(19.44 MHz) 은 PLL 등에 의해 8배로 되어 155.52 MHz 의 클럭으로 되고, 이것이 SOH 삽입 다중회로(34), 광송신기(35)에 공급된다.(도면에서 결선은 생략되어 있다). 직렬 변환된 정보는 광 송신기(35)에서 광 신호로 변환되어 전송선로인 광파이버에 송출된다.The amount of information accumulated in the stuffing buffer is equal to the amount of stuffing buffer capacity.

If less than 3 bytes, positive stuffing is performed to reduce the amount of compromise that can be transmitted in one frame. As described above, the frequency deviation of the node clock needs to be within ± 308 ppm in order not to cause overflow or underflow of the stuffing buffer 14-9. The SOH insertion multiplexing (MUX) circuit 34 inserts SOH information and multiplexes the information in bytes to make the information of 155.52 Mb / s. The node clock (19.44 MHz) is multiplied by a PLL or the like and becomes a clock of 155.52 MHz, which is supplied to the SOH insertion multiple circuit 34 and the optical transmitter 35 (wiring is omitted in the drawing). The serially converted information is converted into an optical signal by the optical transmitter 35 and transmitted to the optical fiber which is a transmission line.

In addition, the synchronous clock information in the SOH extracted by the multiple separation / SOH extraction circuit 23 is transmitted to the clock generation circuit 26 via the signal line 41 to generate a synchronous clock. The generated synchronous clock is suppressed by jitter in the PLL 13-9, and is supplied to the synchronization buffer 28 and the synchronization device interface 30 for the received data. The generated synchronous clock is also synchronized to the node clock in the synchronization signal 27 (the details will be described by the embodiment of FIG. 8). The clock pointer generation circuit 32 counts the change point position of the sync clock synchronized to the node clock at the start position of the frame, and adds it to the SOH insertion multiplexer 34 as the change point position information of the sync clock. The start position of the frame can be known by the frame start signal 36 from the stuffing control / frame generation circuit 33. The SOH insertion multiplexer 34 inserts the change point position information of the sync clock into the data communication channel of the SOH, and sends it to the next node as sync clock information.

Hereinafter, the distribution method of the synchronous clock will be described in detail. 6 shows a transmission format of change point position information of a synchronization clock. The entire area of 5 bytes is used. For example, transmission is performed using D1 to D5 of the data communication channel of the SONET frame described in FIG. Considering the case where there are two clock change points in one frame, two clock pointers indicating the change point positions of the sync clock are transmitted. The last one byte is a cyclic redundancy check (CRC) code for error checking.

7 shows the relationship between the transmission format and the clock to be reproduced.

The synchronous clock (8 KHz) is sampled by the node clock (19.44 ± 8 MHz) of the front end node, and the change point position information is transmitted in the format shown in FIG. Since the period (125 동기 ± α) of the common sync clock and the frame period in which the front end node occurs are different, there is no change point in one frame (case (III) of FIG. 7 and one change point (case ( I)) and two cases of change (case (II)), each node reproduces the node clock of the front end node by dividing the transmission clock (155.52 MHz) reproduced from the received optical signal into 8 divisions, and then synchronizes it with the synchronous clock. A common clock is reproduced using the change point position information of 2,430 pcs of node clocks in one frame, counted from the start of the frame, and at what clock the clock has changed. The pointers A and B can be represented by 12 bits, but two bytes are used for each pointer to divide the information into bytes. ) Is in the frame The first synchronous clock change point is indicated, and the pointer B indicates the second change point, and if there is no corresponding change point, all bits are 1. In FIG. 7, in case I, the change point is 1 in the frame. Is shown as a pointer A. The receiving node counts the node clock reproduced at the start position of the receiving frame and generates a pulse at the time when N1 (the value of the pointer A) pcs. The common clock is reproduced by two cases: in case (II), there are two change points, and a pulse is generated at each time point when the N1 and N2 clocks are counted.

Case III shows the case where there is no change point in the frame. All the bits are 1 in both the pointers A and B. If a CRC error occurs in the pointer, the received pointer information is abolished, and the change point is determined by counting 2.430 clocks from the last change point of the reproduced synchronization clock. Since the deviation between the node clock and the synchronous clock can usually be controlled small, this makes it possible to control the influence of the transmission error even if a transmission error occurs.

FIG. 8 shows a detailed view of the clock generation circuit 26 and the synchronization circuit 27 of FIG. For simplicity, the CRC error check processing circuit is omitted. The transmission clock reproduced by the optical receiver 21 is divided by eight by the multiple separation / SOH extraction circuit 23, and the reproduction clock (19.44 ± β) by the signal line 41 together with the extracted clock pointers (A) and (B). MHz) and is transmitted to the clock generation circuit 26. The received two pointers A and B are used to generate the change point position information of the sync clock in the next frame. Therefore, the lower 12 bits of the pointers A and B are loaded into the latches 45 and 50 by the frame start signal 36. On the other hand, the two 12-bit counters 43 and 48 are reset by the frame start signal 36 and start counting up. When the value of the counter 43 (or 48) and the latch 45 (or 50) match, the output of the comparator 44 (or (49) becomes H, and is set / reset type. Set flip-flop 47 (or 52). Flip-flops 47 and 52 are reset by the delayed signals in delay elements 46 and 51, respectively. Therefore, if the counter value matches the value of the pointer, a pulse is generated at that point. Since the maximum counter value is 2.430, when the mode bit of the pointer is 1, the pointer and the counter do not coincide so that no clock is generated. Since the output of the flip-flop 47 represents the change point by the pointer A, and the output of the flip-flop 52 represents the change point by the pointer B, the OR of the two outputs is changed by the OR gate 53. By obtaining this, the synchronous clock can be reproduced. Since the output of the clock generation circuit 26 is synchronized with the node clock of the reproduced front end node, it is impossible to use the clock pointer generation circuit 32 that operates on the self-node clock. Therefore, the clock synchronizing circuit 27 synchronizes with the self node clock.

The synchronization circuit 27 is constituted by cascade-connecting two edge trigger type flip-flops 54 and 55 in two stages.

Two flip-flops 54 and 55 are supplied with a self-node clock.

Since the inputs of the flip-flops 54 and 55 and the self-node clock are asynchronous, the output sometimes becomes unstable. However, when the instability is resolved, the output is synchronized to the self-node clock by taking the output of the flip-flop 54 as the flip-flop 55. The output 38 of the clock synchronization circuit 27 is applied to the clock pointer generation circuit 32.

9 shows a detailed view of the clock pointer generation circuit 32. As shown in FIG. The number of self-node clocks from the start of the frame in the self-node to the change point position of the synchronized synchronous clock 38 is counted by the 12-bit counter 64. The two-bit counter 63 counts the number of sync clock change points in one frame. Both counters 64 and 63 are reset by the frame start signal 36.

In addition, all the bits of the latches 62 and 66 are set to 1 by the frame start signal 36. This outputs all 1s even when no clock change point exists in the frame.

The bit b0 output of the counter 63 indicates that the clock change point is the first (b0 = 1) or the second (b0 = 0) in the frame.

At the first change point, the output of the AND gate 61 changes, and the value of the counter 64 at that time is taken into the latch 62. At the second change point, the output of the AND circuit 65 changes, and the counter value at the change point is taken into the latch 66. The delay circuit 71 is inserted in order to prevent the output of the counter 63 from changing at the change point of the synchronous clock so that the pulse widths of the outputs of the AND gates 61 and 65 become narrow. Looking at the outputs 69 and 70 of the counter 63 and the outputs 67 and 68 of the latches 62 and 66, the synchronous clock change score and the change point position in one frame are found. Therefore, this is used to generate a clock pointer for transmitting to the next node, that is, the change point position information of the sync clock.

Next, clock jitter in the synchronous clock distribution will be described. Synchronization clocks are repeated several times at each node, but jitter occurs when the synchronization circuit 27 of each node performs synchronization.

10 illustrates the mechanism of generation of jitter. As is apparent from the figure, the change point of the reproduced synchronous clock (input of the F / F 54) and the change point of the synchronous clock after synchronization (output of the F / F 55) are shifted from each other by one clock period + ΔX. do. Since the node clock frequency of each node is different, ΔX changes in time and becomes jitter. Since ΔX varies from 0 to a maximum of 50 ns (1 / 19.44 MHz), in the worst case, the maximum value of jitter is 50 ns × number of nodes. However, this jitter is suppressed by the PLL.

Since the amount of jitter attenuation in a PLL is generally proportional to the jitter frequency, high-frequency jitter can be attenuated to levels that are not a problem for the PLL. Therefore, jitter at low frequencies becomes a problem. In order to evaluate the jitter amount when the number of dependent nodes increases, for example, the case of node number 128 is evaluated. Now in the worst case, consider the case where up to 50 ns of jitter at each node is added, resulting in a single frequency of jitter at the 128th node.

The maximum amplitude of jitter is 25 ns × 127 relay = 3.2 kHz. Normally, jitter is specified above 10 Hz (below 10 Hz becomes wander. Consider jitter at 10 Hz. Consider the case where the jitter added in the worst case is a sine wave of 10 Hz. In this case, all jitter power is Focusing on 10Hz.

When the jitter attenuation at 10 Hz of the PLL is set to 30 dB (a voltage-controlled crystal oscillator is used, it is a value that can be easily realized as a state-of-the-art technology), the jitter of the PLL output is about 100 ns, which is acceptable. Although the TTC standard JT-I 431 defines a user / network interface of 1.5 Mb / s, the jitter to be allowed by the terminal is 3.2 kHz in the frequency range of 10 Hz to 120 Hz. The jitter amount can be controlled by changing the parameter of the PLL to change the amount of jitter attenuation, and also by changing the frequency at which the synchronous clock is sampled. In the embodiment, since sampling is performed at 19.44 MHz, the jitter generated during relaying was 50 ns at maximum. However, since jitter generated decreases in inverse proportion to the sampling frequency, the jitter amount can be reduced by increasing the sampling frequency. .

Next, stuffing for absorbing the difference between the node clock frequency and the information transmission rate in each node will be described in detail. In the embodiment shown in FIG. 1, the information transmission rate is defined by an external clock 9. That is, to synchronize the start position of the VC-4 generated by the master node 2-8 with the external clock 9, the stuffing is performed to match both when the start position of the VC-4 is out of sync with the external clock. Run On the other hand, general nodes 2-9 to 2-11 other than the master node 2-8 perform stuffing in order to transmit the amount of information sent from the front end node without excessive or insufficient by the self-node clock. Therefore, the stuffing algorithm is different at the master nodes 2-8 and general nodes 2-9 to 2-11.

11 shows a configuration for realizing stuffing at the master node 2-8. That is, the configuration 33 'of the circuit corresponding to the stuffing control / frame generation circuit 33 of the general node 2-9 is shown. Stuffing at the master node is performed by comparing the external clock with the starting position of VC-4 where the master node occurs, so that both phases are within a certain value. This makes it possible to match the speed of the information output from the master node to the external clock. In FIG. 11, the clock input 17 is an output which reduced the jitter by supplying the external clock 9 of FIG. 1 to the PLL 10. In FIG. The frame generation control circuit 86 synchronizes the clock input 17 with the node clock from the clock source 15-8 in the circuit 82 (the configuration is the same as that of (27) in FIG. 8). The start position signal 87 of the generated VC-4 is compared. The counter 83 is reset by the synchronized external clock and counted up by the node clock. Therefore, the number of node clocks from the start of the synchronized external clock is counted. By loading the value of the counter 83 into the latch 84 by the VC-4 start position signal 87 output from the frame generation control circuit 86, the external clock and the start position of the VC-4 are loaded. The phase difference can be known. Since the phase difference is distributed from 0 to 2,429 (the number of node clocks in one frame -1), for example, negative stuffing when 4 or more and 1,215 or less, and positive stuffing when 1,215 or more and 2,426 or less are performed. Can be controlled to come within 3 clocks from the synchronized external clock. The determination of the phase difference is executed by the determination circuit 85, the result is sent to the frame generation control circuit 86, and stuffing is executed.

Fig. 12 shows a configuration of another embodiment of the stuffing control unit in the master node. In this embodiment, the difference between the number of bytes of VC-4 actually sent and the number of bytes (261 x 9 = 2.349) that is to be originally sent between one cycle of the synchronized external clock is controlled to be below a certain value. In FIG. 12, the same numerals are assigned to the same parts as in FIG. 11, and description thereof is omitted.

Since the counter 83 is reset by a signal in which the external clock 17 is synchronized, the VC-4 output signal supplied by the frame generation control circuit 86 can be counted for one period of the signal in which the external clock is synchronized. have.

At the end of the count, the subtraction circuit 89 obtains the difference between the 23 and 49 and accumulates it in the accumulator 88. The determination circuit 85 determines that the cumulative value exceeds +3 bytes, sends the result to the frame generation control circuit 86, and controls stuffing at the master node.

If the external clock 9 is not available, the clock output from the clock source 15-8 of the master node 2-8 is divided to produce a signal of 8 KHz to be a synchronous clock source. In this case, since the node clock and the synchronization clock are synchronous in the master node, stuffing does not occur.

Next, the stuffing control part in a general node is demonstrated in detail. FIG. 13 illustrates information input and output to the stuffing buffer 14-9 of FIG. 5. The diagonal line in the figure is the SOH area. Although the frame configuration is shown in FIG. 3, frames are transmitted sequentially from left to right and top to bottom. Therefore, as shown in FIG. 13, an SOH region of 9 bytes appears periodically. Since the frame periods of the reception and the transmission and the frame start position are independent of each other, as shown in FIG. 13, the SOH areas of the transmission and the reception are not synchronized, and the phase difference fluctuates in time. Therefore, a problem arises as to whether or not stuffing should be determined depending on the amount of information in the stuffing buffer 14-9. For example, in the period from point a to point b in FIG. 13, information is not written into the stuffing buffer because the input is a 9-byte SOH area, but is read from the stuffing buffer 14-9 because the output is an information area. Therefore, the amount of information in the stuffing buffer at point b is reduced by 9 bytes compared to point a. In this way, the amount of information in the stuffing buffer 14-9 varies by ± 9 bytes depending on the time of observation. In order to prevent this problem, when information in one frame is read in the stuffing buffer 14-9 in units of bytes, one frame of the amount of information in the stuffing buffer 14-9 is stored by storing the position in the buffer in which the information is read. A method of determining whether or not to perform stuffing is adopted based on the minute average value. According to this method, for example, even in a situation as shown in FIG. 13, since the decrease in the amount of information in the stuffing buffer by the write of the SOH region and the increase in the amount of information in the stuffing buffer by the SOH write are offset by averaging, stuffing is executed correctly. do.

FIG. 14 shows the configuration of one embodiment of the stuffing buffer 14-9 and the stuffing control / frame generation circuit 33 of FIG. 5 to explain the above algorithm. The stuffing buffer 14-9 includes a buffer memory 93 for storing information in units of bytes, and counters 94 and 95 for controlling write and read addresses, respectively. The counter 94 is counted up by the write signal 92 each time information is written from the access control circuit 25 via the line 39 and the counter 95 is controlled by the stuffing control and frame generation circuit 33. Each time information is read, it is counted up by the read signal 104.

The counter value is reset when the maximum capacity of the buffer 93 is reached.

Therefore, the subtraction circuit 96 obtains the difference between the values of the counters 94 and 95 so that the amount of information in the buffer memory 93 can be known.

This result is accumulated by one frame using the adder 97 and the latch 98. To obtain the accumulation of one frame, the latch 98 is reset by the frame start signal 101 and supplies the clock 105 only when reading information (except the SOH area). The determination circuit 99 determines whether stuffing should be performed in the next frame, based on the accumulated value of the amount of information in the buffer 93 and the number of transmitted bytes in one frame, at the end of the accumulation of one frame. That is, it is determined whether or not there is stuffing on the basis of the boundary of the number of VC-4 transmitted bytes x (maximum capacity / 2 ± 3 bytes of the buffer 93). The number of transmitted bytes in one frame is only three types, 2,346 bytes (positive stuffing), 2,349 bytes (no stuffing), and 2,352 bytes (negative stuffing) depending on the presence or absence of stuffing in the frame. The control circuit 102 is notified to the determination circuit 99. The determination result is transmitted to the frame generation circuit 102 by the signal line 100 to perform stuffing.

As mentioned above, although the Example of this invention was described, it is clear that this invention is not limited to the said Example. In the above description, a single frame has been described. In practice, many frames are time-division multiplexed and transmitted, but time-division multiplexed transmission is naturally included in the present invention.

For example, if four frames are time-division multiplexed and transmitted (information transfer rate is 155.52 × 4 Mbps), instead of performing stuffing per frame (155.52 Mbps), four frames can be stuffed simultaneously. good.

According to the present invention, it is possible to construct a multi-media LAN which can control jitter in the synchronization clock without the accumulation of jitter in the transmission clock and can be controlled to a level that is not separated. In addition, since internationally standardized fixed-length frames can be used, LANs are resistant to transmission errors and have the same physical and logical transmission rates.

Claims (16)

In an independent synchronous local area network, in which a plurality of nodes are connected via a transmission line, each node includes means for extracting a received clock signal, a clock source for generating an independent node clock signal, and an oscillation frequency of the independent node clock signal. Frame generation means for generating a fixed length frame on the basis of the reference, means for reproducing the sync clock signal transmitted by the upstream node using the change point information provided in a specific region of the reception frame, and the reproduced sync clock signal is independent Synchronizing means for synchronizing to the node clock signal, and detecting a change point of the synchronization clock signal synchronized by the synchronization means to apply the detected change point to a specific area of the frame of the fixed length generated by the frame generation means. An independent synchronous premises information network comprising means for setting as change point information of the synchronized synchronous clock signal . 2. The apparatus of claim 1, wherein the means for detecting and setting each change point of the node counts a time from the generated fixed length frame to a change point of the sync clock signal synchronized with the independent node clock signal. And means for inserting a value obtained as a result of the count into the specific area of the generated fixed length frame. The independent synchronous premises according to claim 1, wherein the generated fixed length frame is composed of a SONET frame, and a specific region in the generated fixed length frame that transmits change point information of the synchronous clock signal is a data communication channel. Information and communication network. The method of claim 1, wherein at least one of the plurality of nodes is a master node that supplies the sync clock signal to the other node as a master sync clock signal, and the master node supplies an external clock signal or the independent node clock signal. Means for setting a change point of the master synchronous clock signal in a specific area of the generated fixed-length frame using as a master synchronous clock signal and generating the information amount defined by the master synchronous clock to be transmitted to a next node. An independent synchronous intra-premises communication network comprising means for adjusting the amount of information transmitted in a fixed length frame. Receiving means for receiving information of a fixed length frame, means for extracting a received clock signal, a clock source for generating an independent node clock signal, and a frame for generating a fixed length frame on the basis of the oscillation frequency of the independent node clock signal Generating means, reading change point information of the synchronization clock signal in a specific region of the fixed length frame received by the reception means, and reproducing the synchronization clock signal sent from an upstream node using the received clock signal; Reproducing means, synchronizing means for synchronizing the generated synchronous clock signal with the independent node clock signal generated by the clock source, means for detecting a change point of the synchronized reproducing synchronous clock signal in the received frame and the synchronizing Means for inserting said change point of said reproduced synchronization clock signal into a specific region of said reproduced fixed length frame; Node for premises network including. In the independent synchronous premises communication network consisting of a plurality of nodes and a transmission line connecting the plurality of nodes, each of the nodes is a means for extracting a received clock signal, a clock source for generating an independent node clock signal, received information Storage means for temporarily storing the data, means for generating a fixed length frame based on the oscillation frequency of the independent node clock signal, and each frame if the amount of information stored in the storage means is larger than a first predetermined reference value. Transmission amount control means for increasing the amount of information to be transmitted and reducing the amount of information to be transmitted in each frame when the amount of information stored in the storage means is less than a second predetermined reference value; Transmitting a sync clock signal to be supplied with a sync terminal by setting a change point of the sync clock signal; An independent synchronous local area network comprising means. 7. The independent apparatus of claim 6, wherein the transmission means comprises means for counting a time from the generated fixed length frame to a change point of the synchronous clock signal and means for inserting a value of the count result into the specific region. Synchronous campus information network. 7. The independent synchronous premises network according to claim 6, wherein the plurality of nodes are connected in a ring shape. 7. The independent synchronous premises according to claim 6, wherein the generated fixed length frame is composed of a SONET frame, and a specific region in the generated fixed length frame that transmits the change point of the synchronous clock signal is a data communication channel. Information and communication network. The method of claim 6, wherein at least one of the plurality of nodes is a master node that supplies the sync clock signal to the other nodes as a master sync clock signal, and wherein the master node supplies an external clock signal or the independent node clock signal. Means for setting a change point of the master synchronous clock signal in a specific region of the generated fixed length frame using a master synchronous clock signal and generating the information amount defined by the master synchronous clock signal to be transmitted to a next node. And a means for adjusting the amount of information transmitted into the fixed-length frame. In the independent synchronous local area network, comprising a plurality of nodes and a transmission line connecting the plurality of nodes, each of the nodes includes: a means for extracting a received clock signal; a clock source for generating an independent node clock signal; Storage means for temporarily storing information, means for generating a fixed length frame based on the oscillation frequency of the independent node clock signal, and each frame if the amount of information stored in the storage means is larger than a first predetermined reference value. And an information delivery amount control means for increasing the amount of information transmitted in the storage unit and reducing the amount of information transmitted in each frame when the amount of information stored in the storage means is smaller than a second predetermined reference value. A result or a summary of accumulated information indicating an amount of information stored in the storage means over at least one frame Means for increasing or decreasing the amount of information in each one frame according to the result of average information representing the amount of information stored in the storage means over one frame, wherein each of the nodes is placed in a specific area of the generated fixed length frame. And means for transmitting the synchronization clock signal supplied to the synchronization terminal by setting a change point of the synchronization clock signal. The fixed length frame of claim 11, wherein the generated fixed length frame is composed of a SONET frame and transmits the change point of the synchronization clock signal. communications network. 12. The method of claim 11, wherein at least one of the plurality of nodes is a master node that supplies the synchronization clock signal to the other node as the master synchronization clock signal, and the master node supplies an external clock signal or the independent node clock signal. Means for setting a change point of the master synchronous clock signal in a specific area of the generated fixed length frame using the master synchronous clock signal and means for adjusting the amount of information transmitted in the generated fixed length frame; Independent Synchronous Campus Information Network. 12. The independent synchronous premises network according to claim 11, wherein the plurality of nodes are connected in a ring shape. 10. The method of claim 8, wherein at least one of the plurality of nodes is a master node that supplies the synchronization clock signal to the other node as a master synchronization clock signal, and wherein the master node supplies an external clock signal or the independent node clock signal. Means for setting a change point of the master synchronous clock signal in the specific region of the generated fixed-length frame using as a master synchronous clock signal, and the information amount defined by the master synchronous clock signal is transmitted to a next node. And a means for adjusting an amount of information transmitted in the generated fixed length frame. 10. The method of claim 9, wherein at least one of the plurality of nodes is a master node for supplying the sync clock signal to the other node as a master sync clock signal, and the master node supplies an external clock signal or the independent node clock signal. Means for setting a change point of the master synchronous clock signal in a specific region of the generated fixed length frame using a master synchronous clock signal and generating the information amount defined by the master synchronous clock signal to be transmitted to a next node. And a means for adjusting the amount of information transmitted in the fixed fixed length frame.

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