CA2090270A1 - Circuit arrangement for equalizing frequency and/or phase variations between an incoming and an outgoing signal - Google Patents
Circuit arrangement for equalizing frequency and/or phase variations between an incoming and an outgoing signalInfo
- Publication number
- CA2090270A1 CA2090270A1 CA002090270A CA2090270A CA2090270A1 CA 2090270 A1 CA2090270 A1 CA 2090270A1 CA 002090270 A CA002090270 A CA 002090270A CA 2090270 A CA2090270 A CA 2090270A CA 2090270 A1 CA2090270 A1 CA 2090270A1
- Authority
- CA
- Canada
- Prior art keywords
- buffer
- read
- signal
- data
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
- H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
Abstract
PHD 92.023 27.01.1993 Abstract:
Circuit arrangement for equalizing frequency and/or phase variations between an incoming and an outgoing signal.
The invention relates to a circuit arrangement for equalizing frequency and/or phase variations between an incoming signal and an outgoing signal which contains data and data gaps. The circuit arrangement comprises a pre-buffer (1) for buffering the data of the incoming signal and a control circuit (2), which control circuit is provided for inserting positive justification data into the signal coming from the pre-buffer (1) when a predetermined lower justification level of the pre-buffer (1) is reached, and provided for supplying justification indication information.
Fig. 2.
Circuit arrangement for equalizing frequency and/or phase variations between an incoming and an outgoing signal.
The invention relates to a circuit arrangement for equalizing frequency and/or phase variations between an incoming signal and an outgoing signal which contains data and data gaps. The circuit arrangement comprises a pre-buffer (1) for buffering the data of the incoming signal and a control circuit (2), which control circuit is provided for inserting positive justification data into the signal coming from the pre-buffer (1) when a predetermined lower justification level of the pre-buffer (1) is reached, and provided for supplying justification indication information.
Fig. 2.
Description
? ~
PHD 92.023 1 27.01.1993 Circuit arrangement for equalizing frequency and/or phase variations between an incoming and an outgoing signal.
The invention relates to a circuit arrangement for equalizing frequency and/or phase variations between an incoming signal and an outgoing signal which contains data and data gaps.
DE-Al-39 20 391 has disclosed a matching circuit in which an incoming S signal having a bit rate of 140 Mbit/s is matched with an outgoing STM-l signal having a bit rate of 155 Mbit/s. The STM-l signal is structured in frames and contains, in addition to the data proper of the incoming signal, control structures and justification data, referenced data gaps. An STM-l frame comprises 270 columns and 9 rows (270bytes per row). The rows 1 to 9 in each of the columns 1 to 9 accommodate the Section 10 Overhead (SOH) for control system and error detection information signals and the rest of the structure (Payload) data of the incoming signal, justification data and further control system information signals. The incoming 140 Mbit/s signal is then carried in a Virtual Container VC4 whose structure is further explained in CCITT Recommendation G709.
A write clock signal with which the data of the incoming signal are written in a buffer is derived from the incoming signal. A local clock signal or read clock signal is used for reading the data. Since the write clock signal and the read clock signal differ as regards frequency and/or phase, justification data are inserted into the outgoing signal. The control of the write and read operations is taken over by a buffer 20 control circuit operated with the write and read clock signals. The buffer control circuit thus performs a synchronisation of the incoming signal with the read clock signal and also justification operations in that it inserts justification data into predetermined justification locations.
It is an object of the invention to provide a circuit arrangement of the type 25 defined in the opening paragraph which carries out in a simple manner a synchronisation of incoming and outgoing signals.
The object is achieved in a circuit arrangement for equalizing frequency and/or phase variations between an incoming signal and an outgoing signal which ~ "~ ?
PHD 92.023 2 27.01.1993 contains data and data gaps, by means of the following characteristic features:
The circuit arrangement comprises - a pre-buffer for buffering the data of the incoming signal and - a control circuit provided for inserting positive justification data ir.to the signal coming from the pre-buffer when a predetermined lower justification level of the pre-buffer is reached, and for supplying justification indication information.
The circuit arrangement according to the invention comprises a pre-buffer and a control circuit, which control circuit establishes a matching of two digital signals having different frequencies. The data of the signal are written in the pre-buffer with 10 the clock frequency of a write clock signal. The write clock signal has been derived from the incoming signal. The data are read from the pre-buffer with the clock frequency of a local clock signal or a read clock signal. In this manner the data are synchronised with the read clock signal.
The write and read operations of the pre-buffer are controlled by a control 15 circuit which inserts positive justification data into the outgoing signal when a specific lower justification level of the pre-buffer is reached. Positive justification is meant to be understood as the omission of a useful information signal from a location which otherwise does carry useful information. Positive justification is necessary when the frequency of the read clock signal exceeds that of the write clock signal. It may also 20 happen that the frequency of the read clock signal is lower than that of the write clock signal. In that case negative justification is to take place before there is an overflow of the pre-buffer. In the case of negative justification, useful information is carried at such a location which otherwise does not carry useful information. A negative justification operation may only be performed during a data gap. During that operation data are 25 inserted in at least one data gap.
The data supplied by the pre-buffer may be applied to a matching circuit which no longer has for its object to establish synchronisation of the data with the read frequency, but is used for inserting the justification data supplied by the pre-buffer and any further justification data into the justification locations predetermined for this 30 purpose. Such justification locations can be learnt from CCIl~ Recommendation G709, for example, For STM-I signals l-aving different containers (for example, VC-ll or VC-3). Due to the synchronisation in the pre-buffer, the circuitry in the matching circuit versus the prior-art circuits is reduced, because ~he matching circuit is operated only PHD 92.023 3 27.01.1993 with a read clock signal and not additionally with the write clock signal (synchronous matching circuit). There is thus asynchronous operation in the simple-structure circuit arrangement according to the invention, which only matches the read clock w;th the write clock.
With the circuit arrangement according to the invention, an incorning signal having a bit rate of 140 Mbit/s can be matched with an outgoing STM-1 signal, or a match can be established in a regenerator circuit which receives an STM-1 signal and supplies an STM-1 signal.
An embodiment of the control circuit is characterized by the following I 0 features:
The control circuit comprises a write address generator, a read address generator, a subtracter circuit and a comparator.
The write address generator is used for producing write addresses with each write clock and the read address generator is used for producing read addresses with each read 1 5 clock.
The write and read address generators are provided for producing addresses in a cyclic order.
The subtracter circuit is used for forming a difference value by subtracting the read address from the write address. The comparator is provided for inhibi~ing the read 20 address generator for one read clock period once the difference value has fallen below a threshold value.
The write address generator produces a new write address with each write clock of a write clock signal. The write address is then changed by a given unit from one write clock to the next. For example, the write address is incremented by " l" with 25 each write clock. The write address generator, when generating write addresses, runs through a specific cycle, so that the write addresses are generated repeatedly. The number of write addresses of a cycle depends on the size of the pre-buffer. The same holds for the read address generator which forms a new read address with each read clock of a read clock signal.
The subtracter circuit in the control circuit subtracts the read address from the write address with the read clock and produces a difference value. In a comparator this difference value is compared with a threshold value. If the difference value is smaller than the threshold value, positive justification takes place. Positive justification PHD 92.023 4 27.01.1993 takes place because the read address generator is inhibited for one read clock period i.e.
the supply of the read clock signal by the rear.l address generator is interrupted for one read clock period. The threshold value corresponds to the lower justification level of the pre-buffer.
~egative justification may only take place if the incoming signal applied to the pre-buffer has a data gap. In the case of a data gap the write address generator is stopped i.e. the write clock signal supply is interrupted. In this case no further data are stored in the pre-buffer. The read address generator, however, continues to produce read addresses as a result of which data are read out from the pre-buffer. Once the 10 threshold value has been reached, the read address generator is also stopped. This interruption in the production of read addresses is terminated when data are again written in the pre-buffer and the difference value reaches at least the threshold value.
The interruption with respect to the writing in the pre-buffer has then lasted at least one read clock period longer than the interruption with respect to the reading of the pre-15 buffer. During a data gap this procedure causes negative justification to take place. Theminimum size of the pre-buffer is to be such that no overflow of the pre-buffer occurs for at least two consecutive data gaps.
The circuit arrangement may be used for processing STM-I signals. Data of this STM-1 signal are then stored in the pre-buffer. The STM-I signal comprises 20 SOH information (SOH = Section Overhead) which is carried in the rows 1 to 9 in the columns 1 to 3 and 5 to 9 of the STM-1 frame. AU pointers which may point to thebeginning of an Administrative Unit AU-4 or AU-3 and may contain justification data are positioned in row 4 in the columns 1 to 9. The SOH information contains control system and error detection information. Only data Iying outside the SOH region are 25 written in the pre-buffer. For this purpose, the matching circuit comprises a receiving frame counter which is provided for inhibiting the write address generator when SOH
information of the STM-l signal occurs, with the exception of the AU pointers. If the SOH information is present, no write address will be generated in the write address generator. When SOH information occurs there is thus a data gap.
The receiving frame counter may additionally be used for producing an AU pointer code when the beginning of the AU pointer is detected. This AU pointer code may be buffered in the pre-buffer and made available to a subsequent matching circ~lit which, as a result, does not need a frame counter.
PHD 92.023 5 27.01.1993 The Administrative Units AU-3 and the dedicated AU pointers are each alternately inserted into the STM-l frames. Ihere are thus three structures which alternately show up in the STM-1 frame. For identifying a structure, the receiving frame counter may additionally comprise a struct lre counter which indica~es a structure 5 and whose count may also be buffered in the pre-buffer and applied to the subsequent matching circuit.
If the read address generator is inhibited, the circuit arrangement is still provided for supplying justification indication information. In this case positive justification - thus no data - takes place. A connected matching circuit is capable of 10 evaluating this justification indication information and insert justification data into the predetermined locations into the signal.
During the operation of the circuit arrangement it may happen, for example, that the read clock signal generator becomes defective. For example, the frequency of the read clock signal may be much larger than normal. In that case a data 15 underflow of the pre-buffer will occur more frequently. For detecting a pre-buffer overflow or a pre-buffer underflow, the control circuit comprises a register and an error evaluation circuit. The register is intended for buffering the difference values to be supplied by the comparator during a read clock period, and the error evaluation circuit is provided for detecting a pre-buffer overflow or a pre-buffer underflow on the basis of 20 the difference value to be supplied by the comparator and the difference value to be supplied by the register.
For the adaptation of an STM-l signal a pre-buffer comprising four memory locations for one-byte-long data signals is sufficient. The read and write address generators may then comprise modulo-4 counters.
An exemplary embodiment of the invention will be further explained hereinafter with reference to the drawing Figures, in which:
Fig. 1 gives a diagrammatic representation of the STM-1 frame 30 comprising a VC-4 container, Fig. 2 shows a transmission system in which the invention may be utilized, Fig. 3 shows an exemplary embodiment of a circuit arrangement PHD 92.023 6 27.01.1993 according to the invention to be used in a system as claimed in Claim 2.
Transmission systems transmitting signals of the synchronous digital S hierarchy comprise, for example, transmitting and receiving circuits (terminal devices), in which frequency andtor phase variations between an incoming and an outgoing signal are equalized by circuit arrangements. The incoming signal is then matched with a local clock signal or a read clock signal. For example, an STM-1 signal is transmitted by such a transmission system. This STM-1 signal is structured in frames and further 10 explained in CCITT Recommendation G709. In the following the parts of the STM-1 frame structure essential to the invention will be explained.
The structure of an STM-1 frame is shown diagrammatically in Fig. la.
The frame comprises 270 columns and 9 rows (270 bytes per row). The rows 1 to 3 and 5 to 9, in each of the columns 1 to 9 carries the what is commonly referred to as 15 Section Overhead (SOH) for control system and error detection information, the fourth row of columns 1 to 9 carries an Administrative Unit denoted AU Pointer (AU-P), and the remaining columns and rows the actual useful information, the STM-1 Payload (P).
As shown in Fig. Ib the STM-1 Payload carries, for example, a Virtual Container VC-4 (in an Administrative Unit AU-4) which consists of a useful information structure and a 20 control system structure POH (Path Overhead). For example, three Administrative Units AU-3 may alternatively be inserted into the STM-1 frame. A container in this case is understood to be the basic container for useful signals. Such a container may carry further containers.
In Fig. 2 a signal generated by a transmitter 20 is transmitted to a 25 receiver 40 over a channel 30. In the receiver 40 the input signal of the receiver having an input data signalling rate is converted into an output signal having an output data signalling rate which may be larger or smaller than the input signalling rate.
An exemplary embodiment of a circuit arrangement (40) according to the invention to be used in a system shown in Fig. 2 will be further explained in the 30 following with reference to Fig. 3 which shows a pre-buffer 1, a control circuit 2, a synchronisation circuit 3 and a receiving frame counter 4. The data of the incoming STM-l signal are applied to the pre-buffer 1 and the synchronisation circuit 3.
The above elements 1 to 4 of Lhe circuit arrangement may be parts of an 2 l, ., .,, ~ ...~
PHD 92.023 7 27.01.1993 application-dependent integrated circuit or processor elements which are computer-designed by means of specific design languages. Therefore, the function of such a circuit is easier to explain by way of status runs or program runs.
The synchronisation circuit 3 may be described by the following status 5 run:
1. Determining the beginning of an STM-1 frame on the basis of the first six bytes (3*Al, 3*A2);
2. Generating a set signal when beginning of frame is detected;
PHD 92.023 1 27.01.1993 Circuit arrangement for equalizing frequency and/or phase variations between an incoming and an outgoing signal.
The invention relates to a circuit arrangement for equalizing frequency and/or phase variations between an incoming signal and an outgoing signal which contains data and data gaps.
DE-Al-39 20 391 has disclosed a matching circuit in which an incoming S signal having a bit rate of 140 Mbit/s is matched with an outgoing STM-l signal having a bit rate of 155 Mbit/s. The STM-l signal is structured in frames and contains, in addition to the data proper of the incoming signal, control structures and justification data, referenced data gaps. An STM-l frame comprises 270 columns and 9 rows (270bytes per row). The rows 1 to 9 in each of the columns 1 to 9 accommodate the Section 10 Overhead (SOH) for control system and error detection information signals and the rest of the structure (Payload) data of the incoming signal, justification data and further control system information signals. The incoming 140 Mbit/s signal is then carried in a Virtual Container VC4 whose structure is further explained in CCITT Recommendation G709.
A write clock signal with which the data of the incoming signal are written in a buffer is derived from the incoming signal. A local clock signal or read clock signal is used for reading the data. Since the write clock signal and the read clock signal differ as regards frequency and/or phase, justification data are inserted into the outgoing signal. The control of the write and read operations is taken over by a buffer 20 control circuit operated with the write and read clock signals. The buffer control circuit thus performs a synchronisation of the incoming signal with the read clock signal and also justification operations in that it inserts justification data into predetermined justification locations.
It is an object of the invention to provide a circuit arrangement of the type 25 defined in the opening paragraph which carries out in a simple manner a synchronisation of incoming and outgoing signals.
The object is achieved in a circuit arrangement for equalizing frequency and/or phase variations between an incoming signal and an outgoing signal which ~ "~ ?
PHD 92.023 2 27.01.1993 contains data and data gaps, by means of the following characteristic features:
The circuit arrangement comprises - a pre-buffer for buffering the data of the incoming signal and - a control circuit provided for inserting positive justification data ir.to the signal coming from the pre-buffer when a predetermined lower justification level of the pre-buffer is reached, and for supplying justification indication information.
The circuit arrangement according to the invention comprises a pre-buffer and a control circuit, which control circuit establishes a matching of two digital signals having different frequencies. The data of the signal are written in the pre-buffer with 10 the clock frequency of a write clock signal. The write clock signal has been derived from the incoming signal. The data are read from the pre-buffer with the clock frequency of a local clock signal or a read clock signal. In this manner the data are synchronised with the read clock signal.
The write and read operations of the pre-buffer are controlled by a control 15 circuit which inserts positive justification data into the outgoing signal when a specific lower justification level of the pre-buffer is reached. Positive justification is meant to be understood as the omission of a useful information signal from a location which otherwise does carry useful information. Positive justification is necessary when the frequency of the read clock signal exceeds that of the write clock signal. It may also 20 happen that the frequency of the read clock signal is lower than that of the write clock signal. In that case negative justification is to take place before there is an overflow of the pre-buffer. In the case of negative justification, useful information is carried at such a location which otherwise does not carry useful information. A negative justification operation may only be performed during a data gap. During that operation data are 25 inserted in at least one data gap.
The data supplied by the pre-buffer may be applied to a matching circuit which no longer has for its object to establish synchronisation of the data with the read frequency, but is used for inserting the justification data supplied by the pre-buffer and any further justification data into the justification locations predetermined for this 30 purpose. Such justification locations can be learnt from CCIl~ Recommendation G709, for example, For STM-I signals l-aving different containers (for example, VC-ll or VC-3). Due to the synchronisation in the pre-buffer, the circuitry in the matching circuit versus the prior-art circuits is reduced, because ~he matching circuit is operated only PHD 92.023 3 27.01.1993 with a read clock signal and not additionally with the write clock signal (synchronous matching circuit). There is thus asynchronous operation in the simple-structure circuit arrangement according to the invention, which only matches the read clock w;th the write clock.
With the circuit arrangement according to the invention, an incorning signal having a bit rate of 140 Mbit/s can be matched with an outgoing STM-1 signal, or a match can be established in a regenerator circuit which receives an STM-1 signal and supplies an STM-1 signal.
An embodiment of the control circuit is characterized by the following I 0 features:
The control circuit comprises a write address generator, a read address generator, a subtracter circuit and a comparator.
The write address generator is used for producing write addresses with each write clock and the read address generator is used for producing read addresses with each read 1 5 clock.
The write and read address generators are provided for producing addresses in a cyclic order.
The subtracter circuit is used for forming a difference value by subtracting the read address from the write address. The comparator is provided for inhibi~ing the read 20 address generator for one read clock period once the difference value has fallen below a threshold value.
The write address generator produces a new write address with each write clock of a write clock signal. The write address is then changed by a given unit from one write clock to the next. For example, the write address is incremented by " l" with 25 each write clock. The write address generator, when generating write addresses, runs through a specific cycle, so that the write addresses are generated repeatedly. The number of write addresses of a cycle depends on the size of the pre-buffer. The same holds for the read address generator which forms a new read address with each read clock of a read clock signal.
The subtracter circuit in the control circuit subtracts the read address from the write address with the read clock and produces a difference value. In a comparator this difference value is compared with a threshold value. If the difference value is smaller than the threshold value, positive justification takes place. Positive justification PHD 92.023 4 27.01.1993 takes place because the read address generator is inhibited for one read clock period i.e.
the supply of the read clock signal by the rear.l address generator is interrupted for one read clock period. The threshold value corresponds to the lower justification level of the pre-buffer.
~egative justification may only take place if the incoming signal applied to the pre-buffer has a data gap. In the case of a data gap the write address generator is stopped i.e. the write clock signal supply is interrupted. In this case no further data are stored in the pre-buffer. The read address generator, however, continues to produce read addresses as a result of which data are read out from the pre-buffer. Once the 10 threshold value has been reached, the read address generator is also stopped. This interruption in the production of read addresses is terminated when data are again written in the pre-buffer and the difference value reaches at least the threshold value.
The interruption with respect to the writing in the pre-buffer has then lasted at least one read clock period longer than the interruption with respect to the reading of the pre-15 buffer. During a data gap this procedure causes negative justification to take place. Theminimum size of the pre-buffer is to be such that no overflow of the pre-buffer occurs for at least two consecutive data gaps.
The circuit arrangement may be used for processing STM-I signals. Data of this STM-1 signal are then stored in the pre-buffer. The STM-I signal comprises 20 SOH information (SOH = Section Overhead) which is carried in the rows 1 to 9 in the columns 1 to 3 and 5 to 9 of the STM-1 frame. AU pointers which may point to thebeginning of an Administrative Unit AU-4 or AU-3 and may contain justification data are positioned in row 4 in the columns 1 to 9. The SOH information contains control system and error detection information. Only data Iying outside the SOH region are 25 written in the pre-buffer. For this purpose, the matching circuit comprises a receiving frame counter which is provided for inhibiting the write address generator when SOH
information of the STM-l signal occurs, with the exception of the AU pointers. If the SOH information is present, no write address will be generated in the write address generator. When SOH information occurs there is thus a data gap.
The receiving frame counter may additionally be used for producing an AU pointer code when the beginning of the AU pointer is detected. This AU pointer code may be buffered in the pre-buffer and made available to a subsequent matching circ~lit which, as a result, does not need a frame counter.
PHD 92.023 5 27.01.1993 The Administrative Units AU-3 and the dedicated AU pointers are each alternately inserted into the STM-l frames. Ihere are thus three structures which alternately show up in the STM-1 frame. For identifying a structure, the receiving frame counter may additionally comprise a struct lre counter which indica~es a structure 5 and whose count may also be buffered in the pre-buffer and applied to the subsequent matching circuit.
If the read address generator is inhibited, the circuit arrangement is still provided for supplying justification indication information. In this case positive justification - thus no data - takes place. A connected matching circuit is capable of 10 evaluating this justification indication information and insert justification data into the predetermined locations into the signal.
During the operation of the circuit arrangement it may happen, for example, that the read clock signal generator becomes defective. For example, the frequency of the read clock signal may be much larger than normal. In that case a data 15 underflow of the pre-buffer will occur more frequently. For detecting a pre-buffer overflow or a pre-buffer underflow, the control circuit comprises a register and an error evaluation circuit. The register is intended for buffering the difference values to be supplied by the comparator during a read clock period, and the error evaluation circuit is provided for detecting a pre-buffer overflow or a pre-buffer underflow on the basis of 20 the difference value to be supplied by the comparator and the difference value to be supplied by the register.
For the adaptation of an STM-l signal a pre-buffer comprising four memory locations for one-byte-long data signals is sufficient. The read and write address generators may then comprise modulo-4 counters.
An exemplary embodiment of the invention will be further explained hereinafter with reference to the drawing Figures, in which:
Fig. 1 gives a diagrammatic representation of the STM-1 frame 30 comprising a VC-4 container, Fig. 2 shows a transmission system in which the invention may be utilized, Fig. 3 shows an exemplary embodiment of a circuit arrangement PHD 92.023 6 27.01.1993 according to the invention to be used in a system as claimed in Claim 2.
Transmission systems transmitting signals of the synchronous digital S hierarchy comprise, for example, transmitting and receiving circuits (terminal devices), in which frequency andtor phase variations between an incoming and an outgoing signal are equalized by circuit arrangements. The incoming signal is then matched with a local clock signal or a read clock signal. For example, an STM-1 signal is transmitted by such a transmission system. This STM-1 signal is structured in frames and further 10 explained in CCITT Recommendation G709. In the following the parts of the STM-1 frame structure essential to the invention will be explained.
The structure of an STM-1 frame is shown diagrammatically in Fig. la.
The frame comprises 270 columns and 9 rows (270 bytes per row). The rows 1 to 3 and 5 to 9, in each of the columns 1 to 9 carries the what is commonly referred to as 15 Section Overhead (SOH) for control system and error detection information, the fourth row of columns 1 to 9 carries an Administrative Unit denoted AU Pointer (AU-P), and the remaining columns and rows the actual useful information, the STM-1 Payload (P).
As shown in Fig. Ib the STM-1 Payload carries, for example, a Virtual Container VC-4 (in an Administrative Unit AU-4) which consists of a useful information structure and a 20 control system structure POH (Path Overhead). For example, three Administrative Units AU-3 may alternatively be inserted into the STM-1 frame. A container in this case is understood to be the basic container for useful signals. Such a container may carry further containers.
In Fig. 2 a signal generated by a transmitter 20 is transmitted to a 25 receiver 40 over a channel 30. In the receiver 40 the input signal of the receiver having an input data signalling rate is converted into an output signal having an output data signalling rate which may be larger or smaller than the input signalling rate.
An exemplary embodiment of a circuit arrangement (40) according to the invention to be used in a system shown in Fig. 2 will be further explained in the 30 following with reference to Fig. 3 which shows a pre-buffer 1, a control circuit 2, a synchronisation circuit 3 and a receiving frame counter 4. The data of the incoming STM-l signal are applied to the pre-buffer 1 and the synchronisation circuit 3.
The above elements 1 to 4 of Lhe circuit arrangement may be parts of an 2 l, ., .,, ~ ...~
PHD 92.023 7 27.01.1993 application-dependent integrated circuit or processor elements which are computer-designed by means of specific design languages. Therefore, the function of such a circuit is easier to explain by way of status runs or program runs.
The synchronisation circuit 3 may be described by the following status 5 run:
1. Determining the beginning of an STM-1 frame on the basis of the first six bytes (3*Al, 3*A2);
2. Generating a set signal when beginning of frame is detected;
3. Applying the set signal to the receiving frame counter 4.
In the STM-l frame the first six bytes in the first row are intended for identifying the beginning of the frame. The first three bytes are referenced A1 and the bytes 4 to 6 are referenced A2. Once the synchronisation circuit 3 has determined these bytes, the beginning of the STM-1 frame has been found. Thereafter, a set signal is generated which is applied to the receiving frame counter 4. The synchronisation circuit 15 3 additionally receives a write clock signal ST, generated by a circuit element (not shown) which has derived the write clock signal from the data stream of the STM-l signal.
The receiving frame counter 4 which also receives the write clock signal ST can be explained by way of the following status run:
20 1. When the set signal from the synchronisation circuit 3 occurs, the count of a main counter is set to an initial value;
2. The count of the main counter is incremented with each write clock;
3. When SOH information occurs, a release signal is blocked;
In the STM-l frame the first six bytes in the first row are intended for identifying the beginning of the frame. The first three bytes are referenced A1 and the bytes 4 to 6 are referenced A2. Once the synchronisation circuit 3 has determined these bytes, the beginning of the STM-1 frame has been found. Thereafter, a set signal is generated which is applied to the receiving frame counter 4. The synchronisation circuit 15 3 additionally receives a write clock signal ST, generated by a circuit element (not shown) which has derived the write clock signal from the data stream of the STM-l signal.
The receiving frame counter 4 which also receives the write clock signal ST can be explained by way of the following status run:
20 1. When the set signal from the synchronisation circuit 3 occurs, the count of a main counter is set to an initial value;
2. The count of the main counter is incremented with each write clock;
3. When SOH information occurs, a release signal is blocked;
4. An AU pointer code is generated when the beginning of the AU pointer is recognized;
5. A structure counter (modulo-3 counter) is set to an initial value when the set signal is received from the synchronisation circuit 3;
6. The count (structure code) of the structure counter is incremented with each write clock.
Once a set signal has been received from the synchronisation circuit 3, the count of a main counter is set to an initial value. With each write clock the count of the main counter is then incremented by unity. This count denotes the number of a byte in STM-l frames. A release signal for the control circuit 2 is generated by the receiving fg ,~
PHD 92.023 8 27.01.1993 frame counter 4 only if no SOH information Is available. Otherwise the release signal is blocked. Furthermore, the receiving frame counter 4 generates an AU pointer codewhen the beginning of the AU pointer (row 4, columns 1 to 9) is recognized. This A~J
pointer code is applied to the pre-buffer 1.
The Administrative Unit AU-3 and dedicated AU pointers are each alternately mapped into the STM-1 frames. Consequently, there are three structures available which alternately show up in the STM-1 frame. For identifying a structure, a structure counter is present in the receiving frame counter 4 which is a modulo-3 counter and is set to an initial value when the set signal from the synchronisation circuit 10 3 is received. With each write clock the count of the structure counter is incremented.
The count of the structure counter is also applied to the pre-buffer 1. These data are buffered in pre-buffer 1 and may be used in a matching circuit 14 following in the circuit arrangement.
The control circuit 2 comprises a write address generator 8, a read 15 address generator 9, a subtracter circuit 10, a comparator 11, a register 12 and an error evaluation circuit 13. The write address generator 8 and the read address generator 9 comprise each modulo-4 counters counting up from zero. The write clock signal isapplied to the write address generator 8 and the read clock signal is applied to the read address generator 9. The contents of the write address generator 8 and read address 20 generator 9 respectively, are incremented by unity with each write clock and read clock respectively. The write addresses of the write address generator 8 and the read addresses of the read address generator 9 are applied to the pre-buffer 1 and to the subtracter circuit 10. The pre-buffer 1 is further supplied with the write clock signal for the writing operation and with the read clock signal for the reading operation. With 25 each write clock the data of the STM-1 signal, the AU pointer code and the structure code are written in the pre-buffer if a write address is available. A write address is generated by the write address generator 8 only if the generation is defined by the release signal produced by the receiving frame counter 4. The data, the AU pointer code and the structure code are read from the pre-buffer 1 when a read clock and a read 3û address are available. The pre-buffer 1 is structured such that it comprises four memory locations for data, four memory locations for the AU pointer code and four memory locations for the structure code.
The subtracter circuit 10 subtracts the read address from the write address 2 `~
PHD 92.023 9 27.01.1993 and forms a difference value which is applied to the comparator 11. The comparator l l produces a release signal for the read address generator 9, which signal is blocked if the difference value reaches a threshold value or falls below that value. This threshold value is "1" in the exemplary embodiment. If the release signal which is applied to the read 5 address generator 9 is inhibited, the read address generator 9 does not generate a read address. As a result of the read address generator 9 being inhibited, no data are read from the pre-buffer 1 during a read clock period. This is equivalent to a positive justification operation.
A negative justification operation may only be carried out when SOH
10 information occurs. When SOH information occurs, the write address generator 8 is inhibited by the receiving frame counter 4. The write address generator 8 will not be inhibited when the AU pointer (row 4, columns 1 to 9) occurs. Consequently, no data will be written in the pre-buffer 1 any longer, and the pre-buffer will be emptied. As a result of the emptying of the pre-buffer 1, the threshold value is reached and, 15 subsequently, a blocking signal is generated by the comparator 11 and the read address generator 9 is stopped. After the end of the SOH information the write address generator 8 will be released via the release signal coming from the receiving frame counter 4. The pre-buffer 1 can then be filled with data. If the comparator 11 detects that the threshold value is exceeded, the comparator releases the read address generator.
The pre-buffer 1 can only store a specific number of data. If the data are written at a higher rate than the one at which they are read out (write clock signal has a higher frequency than the read clock signal), the pre-buffer 1 will present an overflow if the write address generator is not stopped. Since the write address generator 8 can only be stopped when the SOH information occurs, the pre-buffer 1 is to be dimensioned 25 such that no overflow can occur with the perrnissible frequency variations between a read clock and a write clock signal. A negative justification operation may thus only be carried out when a data gap occurs (when SOH information occurs). In contrast, apositive justification operation tfrequency of the write clock signal is smaller than the frequency of the read clock signal) can be carried out during the presence of data.
In the case of a negative justification operation the pre-buffer 1 is prevented from being written for nine write clock periods and prevented from being read out for eight clock periods. Thus, there is one more reading operation than in the normal case.
PHD 92.023 10 27.01.1993 The read clock signal is produced by a local oscillator included in the regenerator circuit. When this oscillator is defective, for example, the read clock signal may have a totally different frequency, so that such a data loss may occur. Thishappens, for example, when the pre-buffer 1 presents an overflow or underflow. For S detecting such an overflow or underflow, the register 12 and the error evaluation signal 13 are provided. The difference value is stored in the register 12 during a read clock period. The error evaluation circuit 13 receives from the register 12 the actualdifference value and the difference value delayed by one read clock period. In the error evaluation circuit 13 these signals are compared with each other by means of a 10 comparator circuit. If these signals exceed specific threshold values, a pre-buffer overflow or underflow is detected and a signal is issued accordingly. The two circuit elements 12 and 13 still receive the read clock signal LT.
Once a set signal has been received from the synchronisation circuit 3, the count of a main counter is set to an initial value. With each write clock the count of the main counter is then incremented by unity. This count denotes the number of a byte in STM-l frames. A release signal for the control circuit 2 is generated by the receiving fg ,~
PHD 92.023 8 27.01.1993 frame counter 4 only if no SOH information Is available. Otherwise the release signal is blocked. Furthermore, the receiving frame counter 4 generates an AU pointer codewhen the beginning of the AU pointer (row 4, columns 1 to 9) is recognized. This A~J
pointer code is applied to the pre-buffer 1.
The Administrative Unit AU-3 and dedicated AU pointers are each alternately mapped into the STM-1 frames. Consequently, there are three structures available which alternately show up in the STM-1 frame. For identifying a structure, a structure counter is present in the receiving frame counter 4 which is a modulo-3 counter and is set to an initial value when the set signal from the synchronisation circuit 10 3 is received. With each write clock the count of the structure counter is incremented.
The count of the structure counter is also applied to the pre-buffer 1. These data are buffered in pre-buffer 1 and may be used in a matching circuit 14 following in the circuit arrangement.
The control circuit 2 comprises a write address generator 8, a read 15 address generator 9, a subtracter circuit 10, a comparator 11, a register 12 and an error evaluation circuit 13. The write address generator 8 and the read address generator 9 comprise each modulo-4 counters counting up from zero. The write clock signal isapplied to the write address generator 8 and the read clock signal is applied to the read address generator 9. The contents of the write address generator 8 and read address 20 generator 9 respectively, are incremented by unity with each write clock and read clock respectively. The write addresses of the write address generator 8 and the read addresses of the read address generator 9 are applied to the pre-buffer 1 and to the subtracter circuit 10. The pre-buffer 1 is further supplied with the write clock signal for the writing operation and with the read clock signal for the reading operation. With 25 each write clock the data of the STM-1 signal, the AU pointer code and the structure code are written in the pre-buffer if a write address is available. A write address is generated by the write address generator 8 only if the generation is defined by the release signal produced by the receiving frame counter 4. The data, the AU pointer code and the structure code are read from the pre-buffer 1 when a read clock and a read 3û address are available. The pre-buffer 1 is structured such that it comprises four memory locations for data, four memory locations for the AU pointer code and four memory locations for the structure code.
The subtracter circuit 10 subtracts the read address from the write address 2 `~
PHD 92.023 9 27.01.1993 and forms a difference value which is applied to the comparator 11. The comparator l l produces a release signal for the read address generator 9, which signal is blocked if the difference value reaches a threshold value or falls below that value. This threshold value is "1" in the exemplary embodiment. If the release signal which is applied to the read 5 address generator 9 is inhibited, the read address generator 9 does not generate a read address. As a result of the read address generator 9 being inhibited, no data are read from the pre-buffer 1 during a read clock period. This is equivalent to a positive justification operation.
A negative justification operation may only be carried out when SOH
10 information occurs. When SOH information occurs, the write address generator 8 is inhibited by the receiving frame counter 4. The write address generator 8 will not be inhibited when the AU pointer (row 4, columns 1 to 9) occurs. Consequently, no data will be written in the pre-buffer 1 any longer, and the pre-buffer will be emptied. As a result of the emptying of the pre-buffer 1, the threshold value is reached and, 15 subsequently, a blocking signal is generated by the comparator 11 and the read address generator 9 is stopped. After the end of the SOH information the write address generator 8 will be released via the release signal coming from the receiving frame counter 4. The pre-buffer 1 can then be filled with data. If the comparator 11 detects that the threshold value is exceeded, the comparator releases the read address generator.
The pre-buffer 1 can only store a specific number of data. If the data are written at a higher rate than the one at which they are read out (write clock signal has a higher frequency than the read clock signal), the pre-buffer 1 will present an overflow if the write address generator is not stopped. Since the write address generator 8 can only be stopped when the SOH information occurs, the pre-buffer 1 is to be dimensioned 25 such that no overflow can occur with the perrnissible frequency variations between a read clock and a write clock signal. A negative justification operation may thus only be carried out when a data gap occurs (when SOH information occurs). In contrast, apositive justification operation tfrequency of the write clock signal is smaller than the frequency of the read clock signal) can be carried out during the presence of data.
In the case of a negative justification operation the pre-buffer 1 is prevented from being written for nine write clock periods and prevented from being read out for eight clock periods. Thus, there is one more reading operation than in the normal case.
PHD 92.023 10 27.01.1993 The read clock signal is produced by a local oscillator included in the regenerator circuit. When this oscillator is defective, for example, the read clock signal may have a totally different frequency, so that such a data loss may occur. Thishappens, for example, when the pre-buffer 1 presents an overflow or underflow. For S detecting such an overflow or underflow, the register 12 and the error evaluation signal 13 are provided. The difference value is stored in the register 12 during a read clock period. The error evaluation circuit 13 receives from the register 12 the actualdifference value and the difference value delayed by one read clock period. In the error evaluation circuit 13 these signals are compared with each other by means of a 10 comparator circuit. If these signals exceed specific threshold values, a pre-buffer overflow or underflow is detected and a signal is issued accordingly. The two circuit elements 12 and 13 still receive the read clock signal LT.
Claims (10)
1. Transmission system comprising a circuit arrangement for equalizing frequency and/or phase variations between an incoming signal and an outgoing signal which contains data and data gaps, which arrangement includes a main buffer (14) and a pre-buffer (1) for buffering the data of the incoming signal and includes a control circuit (2) provided for inserting positive justification data into the signal coming from the pre-buffer (1) when a predetermined lower justification level of the pre-buffer (1) is reached, and for supplying justification indication information.
2. Transmission system as claimed in Claim 1, characterized in that the control circuit (2) comprises a write address generator (8), a read address generator (9), a subtracter circuit (10) and a comparator (11), in that the write address generator (8) is used for producing write addresses with each write clock and the read address generator (9) is used for producing read addresses with each read clock, in that the write and read address generators (8,9) are provided for producing addresses in a cyclic order, in that the subtracter circuit (10) is used for forming a difference value by subtracting the read address from the write address, and in that the comparator (11) is provided for inhibiting the read address generator (9) for one read clock period once the difference value has fallen below a threshold value.
3. Transmission system as claimed in Claim 2, characterized in that the pre-buffer (1) is used for supplying data of an STM-1 signal and in that a receiving frame counter (4) is provided for inhibiting the write address generator (8) when SOH
information of the STM-1 signal occurs, with the exception of the AU pointers.
information of the STM-1 signal occurs, with the exception of the AU pointers.
4. Transmission system as claimed in Claim 2 or 3, characterized in that the comparator (11) is provided for supplying justification indication information if the read address generator (9) is inhibited.
5. Transmission system as claimed in one of the preceding Claims 2 to 4, characterized in that a register (12) is intended for buffering the difference values to be supplied by the comparator (11) during a read clock period, and in that an errorevaluation circuit (13) is provided for detecting a pre-buffer overflow or a pre-buffer PHD 92.023 12 27.01.1993 underflow on the basis of the difference value to be supplied by the comparator (11) and the difference value to be supplied by the register (12).
6. Transmission system as claimed in one of the Claims 2 to 5, characterized in that the pre-buffer (1) comprises four memory locations for one-byte-long data signals and in that the read and write address generators (8, 9) comprise modulo-4 counters.
7. Circuit arrangement for equalizing frequency and/or phase variations between an incoming signal and an outgoing signal which contains data and data gaps, which arrangement includes a pre-buffer (1) for buffering the data of the incoming signal and includes a control circuit (2) provided for inserting positive justification data into the signal coming from the pre-buffer (I) when a predetermined lower justification level of the pre-buffer (1) is reached, and for supplying justification indication information.
8. Circuit arrangement as claimed in Claim 7, characterized in that the control circuit (2) comprises a write address generator (8), a read address generator (9), a subtracter circuit (10) and a comparator (11), in that the write address generator (8) is used for producing write addresses with each write clock and the read address generator (9) is used for producing read addresses with each read clock, in that the write and read address generators (8,9) are provided for producing addresses in a cyclic order, in that the subtracter circuit (10) is used for forming a difference value by subtracting the read address from the write address, and in that the comparator (11) is provided for inhibiting the read address generator (9) for one read clock period once the difference value has fallen below a threshold value.
9. Circuit arrangement as claimed in Claim 8, characterized in that the pre-buffer (1) is used for supplying data of an STM-1 signal and in that a receiving frame counter (4) is provided for inhibiting the write address generator (8) when SOH
information of the STM-1 signal occurs, with the exception of the AU pointers.
information of the STM-1 signal occurs, with the exception of the AU pointers.
10. Circuit arrangement as claimed in Claim 8 or 9, characterized in that the comparator (l l) is provided for supplying justification indication information if the read address generator (9) is inhibited.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP4205959.3 | 1992-02-27 | ||
| DE4205959A DE4205959A1 (en) | 1992-02-27 | 1992-02-27 | CIRCUIT ARRANGEMENT FOR COMPENSATING FREQUENCY AND / OR PHASE VARIATIONS BETWEEN AN INCOMING AND OUTPUT SIGNAL |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2090270A1 true CA2090270A1 (en) | 1993-08-28 |
Family
ID=6452670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002090270A Abandoned CA2090270A1 (en) | 1992-02-27 | 1993-02-24 | Circuit arrangement for equalizing frequency and/or phase variations between an incoming and an outgoing signal |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0558136B1 (en) |
| JP (1) | JPH0621929A (en) |
| CA (1) | CA2090270A1 (en) |
| DE (2) | DE4205959A1 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0578315A1 (en) * | 1992-07-09 | 1994-01-12 | Philips Patentverwaltung GmbH | Synchronous transmission system |
| DE4326771A1 (en) * | 1993-08-10 | 1995-02-16 | Philips Patentverwaltung | Transmission system |
| DE4332761A1 (en) | 1993-09-25 | 1995-03-30 | Philips Patentverwaltung | Transmission system with an adaptation circuit |
| DE19732943A1 (en) * | 1997-07-31 | 1999-02-04 | Alsthom Cge Alcatel | Method and component to compensate for frequency and phase fluctuations |
| JP3417392B2 (en) * | 2000-09-08 | 2003-06-16 | ヤマハ株式会社 | Synchronous control device |
| US6807638B1 (en) * | 2000-12-29 | 2004-10-19 | Cisco Systems O.I.A. (1988) Ltd. | Apparatus for and method of in-band clock compensation |
| DE10231648B4 (en) * | 2002-07-12 | 2007-05-03 | Infineon Technologies Ag | Method and device for stuffing control |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2450008A1 (en) * | 1979-02-21 | 1980-09-19 | Portejoie Jean Francois | CIRCUIT FOR SYNCHRONIZING PLESIOCHRONOUS DIGITAL SIGNALS BY JUSTIFICATION |
| DE3920391A1 (en) * | 1989-06-22 | 1991-01-10 | Philips Patentverwaltung | CIRCUIT ARRANGEMENT FOR ADJUSTING THE BITRATES OF TWO SIGNALS |
-
1992
- 1992-02-27 DE DE4205959A patent/DE4205959A1/en not_active Withdrawn
-
1993
- 1993-02-19 DE DE59308595T patent/DE59308595D1/en not_active Expired - Fee Related
- 1993-02-19 EP EP93200481A patent/EP0558136B1/en not_active Expired - Lifetime
- 1993-02-24 CA CA002090270A patent/CA2090270A1/en not_active Abandoned
- 1993-02-26 JP JP5038262A patent/JPH0621929A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| DE4205959A1 (en) | 1993-09-02 |
| JPH0621929A (en) | 1994-01-28 |
| EP0558136B1 (en) | 1998-05-27 |
| EP0558136A1 (en) | 1993-09-01 |
| DE59308595D1 (en) | 1998-07-02 |
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