KR100280203B1 - Bit leaking device - Google Patents

Abstract

The present invention relates to the improvement of jitter characteristics in the synchronous digital hierarchy (SDH) of a transmission system. The bit leaking apparatus of the present invention for reducing jitter generated when demultiplexing from an SDH signal to a PDH signal generates a minimum jitter according to a leak state of the incoming data and a decoder according to the incoming clock. A leak control unit selectively providing a predetermined leak frame pattern, a write operation according to a gap clock of the decoder, a read operation according to the leak frame pattern, and output data of the elastic storage unit according to the leak frame pattern And a clock generator which detects the phase difference between the read / write addresses of the buffer unit and generates a smooth clock to provide the buffer unit.

The present invention has a leak control unit that selectively provides a predetermined leak frame pattern that generates the least jitter in accordance with the pointer state of the incoming data, thereby simplifying hardware implementation and improving performance as compared with the prior art.

Description

BIT LEAKING APPARATUS

The present invention relates to the improvement of the jitter characteristic in the synchronous digital hierarchy (SDH) of a transmission system. More particularly, the present invention relates to a bit leaking device for reducing jitter generated during demultiplexing from a synchronous digital hierarchy (SDH) signal to a pleiochronous digital hierarchy (PDH) signal.

SDH is a Network Node Interface (NNI) standard that enables the construction of a global communication network by interconnecting the world's communication networks (for example, North American, European, and Japanese). SDH is derived from the North American synchronous synchronous optical network (SONET) connection standard but is mixed, but there are some differences in the basic data rate and frame format.

SDH is based on the 9B × 270 frame structure and 155.520Mbps bit rate Synchronous Transfer Module STM-1 signals based on ITU-T Recommendations G.707 to 709. The SDH transmission system performs a multiplexing process for mapping North American and European DS-1 to DS-4 level signals into an STM-n signal and vice versa. These transmission devices using SDH are much more effective for network management and provide a convenient function for monitoring transmission errors such as bit errors from user to other users. In addition, detailed standardization down to communication protocol levels, such as overhead capabilities, can support interoperability with other equipment providers' products without compromising functional efficiency.

In the STM-n frame signal, a pointer (PTR) is a TU (or AU) frame when the virtual box (VC) is aligned with a tributary unit (TU) or an administrative unit (AU). It points to the address where the VC starts and also shows the change relationship when the starting point changes. In other words, the pointer provides a means of synchronization due to the difference in clock speeds (between VC and TU (or AU)) between transmit and receive frames produced by different clocks.

Synchronization by pointer technique, one of the typical features of synchronous transmission network, enables synchronization without repetition of frame retrieval process and copes with similar synchronous environment even with small elastic store. This allows for wide area synchronization. However, SDH is associated with a 125μ frame, resulting in low frequency and high amplitude jitter. As a method of attenuating pointer adjustment jitter due to the use of the pointer technique, a direct attenuation method that designs a desynchronizer phase-locked loop (PLL) in a narrow band, and a bit processing interval in bytes There is a bit leaking control method that is divided into units or less. Here, jitter is a value obtained by dividing the reference clock by the speed of the current clock, and a value of 1 means that the reference clock is equal to the speed of the current clock.

SDH's transmission system compensates for the clock offset between signals by using the 'Pointer Justification' synchronization technique to prevent the loss of the transmission signal due to clock degradation or loss of clock source. However, this pointer adjustment synchronization method causes a large jitter in the demultiplexed dependent signal.

For example, the bit-leakning technique for extracting the 45H DS3 signal, the PDH signal, from the 51M AU3 signal, the SDH signal, is as follows. In fact, this bit-leaking technique is the most important part of the DS3 Mapper, and it can be said that the performance of the mapper is judged according to the performance of this part.

The 51M AU3 signal consists of DS3 data, stuff bits, and overhead bits. Deselecting the 45M DS3 signal from these signals is called destuffing. This de-storing method is judged to be good and bad only by performance and no exact algorithm exists. Of course, extracting only the DS3 signal from the incoming AU3 signal is not difficult, but the problem is jitter caused by the pointer. The occurrence of a pointer means that one frame of AU3 contains more or less 8 bits of data (one frame of AU3 must contain 5592 bits, which is normal, and AU3 contains 8000 frames per second). If all the data is processed within the frame in which the error occurs, it is easy to lose valid data because it generates a large amount of jitter. Thus, a possible solution is to hold the data in the elastic buffer and send all 8 bits until the next pointer occurs over several frames, bit by bit, using bit-leaking techniques. Bit-leaking is necessary for this slow export (for smoothing output).

As shown in FIG. 1, the conventional bit leaking control device 10 includes a decoder 120, an elastic buffer 130, a bit leak control unit 140, an overhead gap redistribution unit 150, and a phase detection unit 160. And the like.

The decoder 120 receives a AU3 signal (IN_SN) coming from the destination 100 and a 51 MHz clock and frame synchronization signals (CLK & FP) coming from the destination clock source 110 to perform pointer analysis, and It is composed of a part that detects whether a pointer is generated by pointer analysis and extracts pure 45M DS3 data from a 51M signal (AU3 or TU).

The bit leak control unit 140 counts the number of pointers by using its counter every time a pointer is generated and outputs a leak enable signal when a certain number is reached, and determines whether to read one bit or less. .

The overhead gap redistribution unit 150 spreads the STS-1 Synchronous Transport Signal (STS) -1 overhead bit to be leaked by the leak enable (LEAK_ENA), and determines which subframe is to be caused to leak the bit. Here, the first divider 151 divides the incoming clock (51 MHz) into M ± 1 (720, 721, 719) according to the leak signal LEAK_T to make a reference clock. The second divider 152 receives the output of the DCO 180 (45 MHz) and divides it with N (621) normally. When stuff occurs, the second divider 152 divides the output with N + 1 (622).

The phase detector 160 detects the phase difference between the two clock signals coming from the two dividers 151 and 152 of the overhead gap redistributor 150, and the sequential filter 170 obtains an average value of the detected phase differences, and digitalizes only the DC level thereof. It is provided to a digital controlled oscillator (DCO) 180 and generates a smooth clock signal SM_RD_CLK of the elastic buffer 130.

The elastic buffer 130 is for eliminating the difference between the light clock (51 MHz) and the lead clock (45 MHz), and stores the data DATA received by the write enable WR_ENA and the gap clock GAP_CLK. The data stored by the read enable RD_ENA and the smoothed clock SM_RD_CLK are read. That is, it buffers data until a read clock comes.

The operation of the conventional apparatus 10 will be briefly described below.

In the pointer analysis portion of the decoder 120, when a positive justification (PJ) or a negative justification (NJ) occurs, the type PTR is transmitted to the bit leakage controller 140. The data extraction part extracts the overhead R bits, C bits, O bits, etc. from the 51M data (IN_SN) and interprets the S bits to generate a 'high' signal only at the pure data position. By combining the indication signals from these two parts, it is possible to know whether the STUFF is generated and how many bits of data are present in the current subframe. For reference, the R bit is a meaningless value in the remaining space, the C bit is a value indicating the number of incoming data (622 bits / 621 bits) of the corresponding subframe, the O bit is a value for communication between users, The S bit is allocated one bit per subframe and indicates that the DS3 data is high when the stuff is high.

The bit leak controller 140 calculates the number of bits to be leaked by using the pointer PTR and the STUFF signal and provides the leak enable signal LEAK_ENA to the overhead gap redistributor 150. .

Then, the overhead gap redistribution unit 150 spreads the STS-1 overhead bits to be leaked, and determines which subframe is to be leaked, and provides the information to the phase detection unit 160.

The phase detector 160 measures how much the phase difference between the two signals input to the input is, averages the signals through the sequential filter 170, and inputs only the DC level to the DCO 180 to determine the elastic buffer 130. The smoothed clock SM_RD_CLK is generated.

When a pointer or stuffing occurs through the above series of processes, the gapped clock for determining whether or not to read one more bit in the subframe by combining the flow of the pointer and the level of the elastic buffer 130 while checking the number of these ( A bit leaking control circuit is completed that minimizes the effects of GAP_CLK) to reduce jitter.

However, the prior art is invented to operate only by the value of the bit leaking control device without a predetermined pattern. So, every detail of the enable pattern needs to be handled automatically, so the overall throughput is significant and the hardware area or volume is large. In addition, there is a problem of unconditionally outputting the data regardless of whether or not the data is congested.

Accordingly, the present invention is to solve the conventional problems as described above, an object of the present invention by using a predetermined pattern to have the least jitter when bit leaking, thereby minimizing the jitter generated during demultiplexing in SDH transmission The hardware implementation is to provide a simplified bit leaking device.

The present invention for achieving the above object is a synchronization system for calculating the output data according to the incoming data according to the incoming clock according to the incoming clock,

Means for decoding the incoming data according to the incoming clock; Leak control means for selectively providing a predetermined leak frame pattern which generates a minimum of jitter in accordance with the leak state of the incoming data; Elastic storage means for performing a write operation according to the gap clock of the decoding means and a read operation according to the leak frame pattern; Buffer means for writing the output data of the elastic storage means according to the leak frame pattern; And means for detecting a phase difference between the read / write addresses of the buffer means and generating a smooth read clock to the buffer means.

1 is a block diagram of a conventional bit leaking device,

2 is a block diagram of a bit leaking apparatus according to the present invention.

<Explanation of symbols for the main parts of the drawings>

200: caller 210: caller

220: decoder 230: leakage control circuit

240: elastic buffer 250: buffer

260: phase detector 270: sequential filter

280: voltage controlled crystal oscillator (VCXO) 290: filter

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

An embodiment of the present invention relates to a bit leaking apparatus for performing demultiplexing of a 51M AU3 (TU-3) signal into a 45M DS3 signal.

2 is a block diagram of a bit leaking apparatus according to an embodiment of the present invention, in which the apparatus 20 is a decoder 220 that decodes an AU3 signal into a DS3 signal, and generates a least jitter according to a pointer state. The leak control circuit unit 230 for generating a frame pattern, the elastic buffer 240 for reading and the buffer 250 for reading and the read / write of the buffer 250 according to the leak frame pattern of the leak control circuit 230. And clock generators 260, 270, 280, and 290 which detect the phase difference between the write addresses and generate the smoothed clock SM_RD_CLK.

Characteristically different from the configuration of FIG. 1 is that the leak control circuit 230 creates a predetermined leak frame pattern according to the incoming speed of the DS3 signal. The leak frame pattern is configured to generate the least jitter. The remaining components are configured and function the same as or similar to that of FIG. 1.

The leak control circuit 230 includes a leak interval determining unit 231 for determining an interval of a frame to be leaked, and a leak frame determining unit 232 for determining a frame to be leaked and determining a compensation value COM_VAL based on a pointer value. A buffer controller 233 which receives the address value LEVEL of the elastic buffer 230 and combines it with the output values COM_VAL and LEAK_FR_ENA of the leak frame determiner 232 to determine whether to read one more bit in the next subframe; The leak state determination unit 234, which raises the current state of the elastic buffer 240 to an appropriate value when the level of the elastic buffer 240 is not at an appropriate value, the control signal PAT_CTRL of the leak state determination unit 234 and the buffer control unit ( And a leak frame pattern generator 235 for outputting the leak frame pattern LEAK_FR_PAT selected according to the stuff signal STUFF.

In addition, various counters are used. The leak interval determiner 231 includes a pointer interval counter for counting the number of frames entered between the pointer and the pointer, and the leak frame determiner 232 includes a leak average. AU3 frame counter for generating a 'high' signal is provided, and the leak frame pattern generator 235 has a counter used to generate a predetermined leak frame pattern (LEAK_FR_PAT) according to the stuff signal by a 51M clock. It is provided.

The present invention is to determine an optimum leak frame pattern that generates the least jitter, and the optimum leak frame pattern according to the present embodiment will be described below.

First, the leak frame pattern generation unit 235 stores two types of leak frame patterns, and provides the patterns as lead enable signals of the elastic buffer 240 and write enable signals of the buffer 250. . In the two kinds of patterns, when 621 bits are read in one subframe: "6161617161616171616171" is repeated, and when 622 bits are read in one subframe: "616171616171616171616171616171616171616171617161 61716161716161716161716161716161716161716161716171" is repeated. Here, '6' is a lead enabled state for 6 clocks, '7' is a lead enabled state for 7 clocks, and '1' is a lead disabled state for 1 clock.

The reason why two 621/622 bit patterns are needed is as follows.

To make the DS3 signal a VC3 signal, because of the difference in data, six subframes in one frame will have 621 bits of data, and three subframes will have 622 bits of data. Since a normal DS3 signal moves at 44.736MHz ± 20PPM, the number of bits in the DS3 signal is (44.736M ± 894.72) bits.

If the DS3 signal has an incoming speed of + 20PPM, it is about 111 more data in one frame, and thus, 5 621 bits and 4 622 bits are read once every almost 9 frames. As a result, reading 621 bits is basically the same, but in some cases, reading 622 bits also occurs.

If the DS3 signal comes in slower than the reference, in case of -20PPM, seven 621 bits are read every nine frames and two 622 bits are read.

On the other hand, it is not necessary to make 620 pattern. Because if the data comes in so slowly, it's not already DS3 data.

The reason why the pattern of the read enable signal has the same shape as above during bit leaking is as follows.

Calculating the optimal bitstream when the DS3 signal has 621 data, the size of one AU3 subframe signal is 720 bits. Here, assuming that the pure data is 621 bits, 99 non-data exists in one subframe. Since these non-data contain jitter components, if they are inserted smoothly between the data, the jitter is reduced and this is in line with the goal of bit-leaking.

If the lead enable signal and the read disable signal are generated at intervals of 621 bits in one subframe, the most ideal value is calculated.

6X + 7Y = 621, X + Y = 99 (X: number of 6, Y: number of 7)

Solving the above equation gives X = 72 and Y = 27.

Since 621/99 = 6.272727, a combination of 6 and 7 is necessary.

Since 72: 27 = 8: 3, the 11-block enable signal has the smallest standard deviation in the order of "66676667667". Therefore, the bitstream of "6161617161616171616171" is the stream which produces the least jitter.

Computing the bitstream at 622 bits,

At 6X + 7Y = 622, X + Y = 98, X = 64 and Y = 34.

The value of 6 requires 64 and the value of 7 requires 34, so the pattern of “6161716161716161716161716161 716161716161716171616171616171616171616171616171616171616171616171616171” is ideal. The above pattern is selected by the control signal received from the outside.

That is, the subframe counter determines whether to count 621 or 622 according to a control signal, and drives the leak frame pattern unit 235 according to the value to output the leak pattern of the corresponding subframe.

In the leak interval determiner 231, the pointer interval counter receives a pointer generation signal PTR indicating the type of pointer from the decoder 220, and when a pointer is generated in one frame, several frames are stored until the next pointer generation frame. Count if you passed. When the pointer is generated, the previous frame count divided by 8 is printed and the rest are discarded. If you count the frames from the rest using the initial value without discarding the rest, even if there is 71, which can leak in 8 times when there is no rest, even if the rest is only 1, it can leak in 9 times. to be. This may result in not being able to exhaust all the pointers in a given frame.

The leak interval determiner 231 includes an adder and a divider which calculate an interval in which pointer adjustment occurs by an arithmetic mean, and which frame is to be leaked in which frame by using the value of the pointer interval counter. Output the average value (P_INT_CNT) to the output.

The adder is composed of eight series-connected registers. The count unit receives the count value of the pointer interval counter and stores the count value in the register and shifts it once when the next count value is received. When eight shifted registers are accumulated, the sum of these values is divided by 8 through the divider to determine the average leaking time. For reference, the reason why the adder stores up to the previous eight pointers is to find a more smooth leak time in total with the pointer generation pattern up to now rather than directly giving the current pointer effect to the next frame.

The division of the divider is a value indicating how many frames are generated, including the previous pointer occurrence. Since this value is based on the past pattern, it serves to buffer the sudden appearance of pointers.

For example, if the pointer generation frequency before the average is 80 frames so that one bit leak interval was 10 frames, but this time pointer generation occurred only 4 frames, 1 bit if there is no adder and divider. Since the leak interval is 0.5 frames, there may be a sudden change of data and a sudden increase in jitter.

In the leak frame determination unit 232, the AU3 frame counter receives the 51M-AU3 frame pulse to generate an enable signal for driving the entire bit leaking control circuit, and calculates a value to compensate the address of the elastic buffer 240. do. In general, the movement is based on the 51M-AU3 frame pulse, and this value affects the operation of the leak frame pattern generator 235.

The leak frame determiner 232 receives a count value of the AU3 frame counter and a pointer average value P_INT_CNT of the leak interval determiner 231 to determine which frame is a 1-bit leak frame to enable a leak frame enable signal. Outputs (LEAK_FR_ENA). The leak frame enable signal LEAK_FR_ENA is maintained at a 'high' level for one entire frame to be leaked, and the output leak frame enable signal LEAK_FR_ENA is provided to the next buffer controller 233. The leak frame determiner 232 also determines a value (-8, -5, 8) to be compensated for each time a pointer is generated and sends it to the buffer controller 233.

The buffer control unit 233 reads the level (difference between the lead address and the write address) LEVEL of the elastic buffer 240 at the end of each subframe, and compensates the compensation value COM_VAL from the leak frame determination unit 232. And the leak frame enable (LEAK_FR_ENA) are inputted, and the counter value (622/621 counter) to be used for the next frame is determined by comparing the level value, the number of pointers, the type of pointer, and the number of leaking bits of the previous pointer. The stuff enable (STUFF) is provided to the leak frame pattern generator 235.

In addition, the buffer controller 233 further leaks the number of bits remaining by adding '8' to the number of remaining bits if the pointer is generated again before all the numbers determined when the previous pointer is generated are leaked. For example, if a negative pointer (NP) now occurs, 8 more bits are coming in, and if the latched value in the buffer is 50 and stuff enable occurs from 51, the buffer value is now 58, so From the subframe, a stuff enable must be generated unconditionally.

This creates a lot of jitter, so you need to get rid of it and slowly lick it bit by bit. Accordingly, the present invention further includes a buffer level compensator (not shown) in the buffer controller 233 to take the following measures.

The buffer control unit 233 uses the buffer level compensator to have a virtual buffer level (second level) separate from the actual buffer level (first level), so as to hold data to be leaked. In the buffer level compensation process, when the NJ is executed when the pointer is generated, the second level has values of '-8' and '-5', and when the PJ is executed, '8'. Has a value. Then, when the leak frame enable signal LEAK_FR_ENA is generated from the leak frame determination unit 232, the second level maintains a value of adding or subtracting 1, respectively. In this case, the second level value of '0' means that all eight bits are leaked. If the pointer was generated before it became '0', the second level value would have its own value plus or minus the value according to the pointer type (NJ, PJ). Thus, combining the first level value of the actual buffer with the virtual second level value, it is possible to know the level of the pure buffer unaffected by the pointer. If the buffer level is not compensated, the data entered by the PJ and NJ will be removed from the buffer at once, so as to compensate for this. (I.e., a lot of jitter occurs because one subframe escapes by one bit. This must be done by one bit over multiple frames.)

For example, suppose that when using a 128-stage buffer, the actual first elastic buffer level is 72 and PJ occurs a few clocks ago in the very subframe. Then, in PJ, data is 8 bits more, so if the actual buffer level is 72, but the compensation is determined as 64 minus 8 (virtual buffer second level), the buffer is at the average point. The result is not. Here, if the leak frame enable (LEAK_FR_ENA) signal is generated, 1 should be added or subtracted from the second buffer, so if the NJ, the buffer level is lowered, so the STUFF signal will be generated, and if the PJ, the STUFF signal will be slower than usual. .

The stuff signal STUFF from the buffer controller 233 is provided to the leak frame pattern generator 235 to influence the lead enable signal for the next subframe. In particular, if the number of leaks is determined outside the buffer, pointers that are released earlier than expected can be processed.

The leak state determination unit 234 determines whether to use the method of quickly approaching the center point of the buffer by looking at the current buffer level. That is, the leak frame pattern generator 235 provides a pattern control signal PAT_CTRL indicating whether to generate a pattern for reading 621 data or a pattern for reading 622 data in the next subframe.

The leak frame pattern generator 235 selectively outputs the aforementioned 621 enable pattern or 622 enable pattern according to the pattern control signal PAT_CTRL of the leak state determination unit 234. The leak frame pattern LEAK_FR_PAT is provided as a read enable signal RD_ENA of the elastic buffer 240 and is also provided as a write enable signal WR_ENA of the buffer 250. That is, if stuff (STUFF) occurs in the buffer control unit 233, it outputs a 622 enable pattern. If stuff (STUFF) does not occur, it outputs a 621 enable pattern.

Now, the buffer 250 receives the leak frame pattern LEAK_FR_PAT generated through the leak control circuit 230 as the lead enable signal RD_ENA to store data output through the elastic buffer 240. The stored data is read and output according to the smoothing read clock SM_RD_CLK obtained from the output of the VCXO 280. Here, the difference between the read address RD_ADR and the write address WR_ADR of the buffer 250 is input to the phase detector 260, and the output of the phase detector 260 is input to the VCXO 280 to output the output data. Speed is controlled.

A brief summary of the bit leaking action of the present invention is as follows.

Whenever the pointer is generated in the leak interval determiner 231, the average number of frames is determined by counting the number of frames, and the frame is determined by the leak frame determiner 232, and at the same time, the number of compensations is determined. The buffer control unit 233 tells the leak frame pattern generation unit 235 which subframe to leak by one bit in consideration of the current level of the elastic buffer 240 and the generated pointer state. The leak state determination unit 234 is used to place data of the next incoming subframe in the center of the buffer. When the values from the buffer control unit 233 and the leak state determination unit 234 enter the leak frame pattern generation unit 235, The leak frame enable pattern LEAK_FR_ENA is determined. The leak frame enable pattern of the leak frame pattern generator 235 becomes a lead enable signal of the output terminal of the elastic buffer 240 and becomes a write enable signal of the input terminal of the buffer 250. When the leak frame enable pattern is determined, DS3 data with smooth and reduced jitter may be detected using the phase detector and the VCXO through the buffer 250.

As described above, the prior art has not been able to prevent variations in the output due to the control of the high speed analog system and is unstable. In addition, it is difficult to adjust parameters or evaluate performance in mass production, resulting in low production efficiency.

According to the present invention, the required enable pattern is stored, and the corresponding enable pattern is determined and bit-leaked for each subframe to be leaked, thereby simplifying hardware implementation. In addition, the enable pattern is configured to have the smallest standard deviation, thereby improving performance. In addition, the read clock value of the buffer can be predicted.

Claims (8)

In the synchronization system for calculating the output data according to the new output clock the incoming data transmitted in a frame unit consisting of a plurality of sub-frames coming in according to the incoming clock, Means for decoding the incoming data according to the incoming clock; Leak control means for selectively providing a predetermined leak frame pattern which generates a minimum of jitter in accordance with the pointer state of the incoming data; Elastic storage means for performing a write operation according to the gap clock of the decoding means and a read operation according to the leak frame pattern; Storage means for writing the output data of the elastic storage means according to the leak frame pattern; And And a means for detecting a phase difference between the read / write addresses of the storage means and generating a smooth read clock to the storage means. The method of claim 1, wherein the leak control means, A leak interval determining unit configured to determine an interval of a frame to be leaked; A leak frame determination unit determining a frame to be leaked and calculating a compensation value for compensating the level of the elastic storage means in dependence on a pointer value; A buffer control unit for determining the number of stuffs of a next subframe depending on a level (lead-write address) of the current elastic storage means, the frame to be leaked and the compensation value; A leak state determination unit for generating a control signal for setting to an appropriate value when the level of the current elastic storage means is not at an appropriate value; And And a leak frame pattern generation unit configured to output a leak frame pattern selected according to the control signal of the leak state determining unit and the stuff signal of the buffer control unit. The method of claim 2, wherein the leak interval determination unit, A pointer interval counter for counting the number of frames entered between the pointer and the pointer; And And means for calculating an average leaking time using a count value of the pointer interval counter, and determining which frame to leak one bit in. The method of claim 2, wherein the leak frame determination unit, A frame counter for counting the number of pure data frames of an incoming frame; Means for determining which frame is a 1-bit leak frame by using the count value of the frame counter and the average leak time of the leak interval determining unit, and enabling leak frames over the entire frame to be leaked according to the determination result. Bit-leaking device, characterized in that to activate the signal. The method of claim 2, wherein the buffer control unit, The leak frame pattern is determined by determining a counter to be used for the next frame using information such as the level value of the elastic storage means read from the end of each subframe, the number of pointers, the type of pointer, and the number of leaking bits of the previous pointer. And a bit leaking device instructing the generating unit. The method of claim 5, wherein the buffer control unit, If the pointer occurs again before all the number of leaks determined at the previous pointer occurrence are leaked, N is added to the remaining bits using a separate virtual buffer level (second level) corresponding to the actual buffer level (first level). Control to leak more by the number; The second level maintains a value of adding or subtracting '1' as the alignment or site alignment is executed and the leak frame enable signal is activated; And combining the first level value with the second level to determine a level of pure elastic storage means that is not influenced by a pointer, and as a result generate a stuff signal. The method of claim 2, wherein in the leak frame pattern generation unit, The predetermined leak frame pattern is determined according to the following definition. For data bits α and non-data bits β of the subframe: G≤ [α / β] ≤G + 1 = H, Gｘ + Hy = α, x + y = β, where x is the number of G, y is the number of H, The combined order of x G and y H is composed of a pattern having the smallest standard deviation, and a read disable period of 1 bit is inserted for each lead enable period of the pattern. The method of claim 7, wherein the leak frame pattern of the DS3 signal in the leak frame pattern generation unit, When the information data of one subframe is 621 bits: "6161617161616171616171" is repeated, If the information data of one subframe is 622 bits: "6161716161716161716161716161716161716161716171616171616171616171616171616171616171616171616171616171" is repeated. Here, '6' is a lead enabled state for 6 clocks, '7' is a lead enabled state for 7 clocks, and '1' is a lead disabled state for 1 clock.