JP3921814B2 - Multiplexer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multiplexing device that inputs serial data and supplies it to any one of a plurality of channels.
[0002]
[Prior art]
FIG. 1 is a block diagram illustrating an example of a conventional multiplexing apparatus.
The multiplexing apparatus 100 includes an encoding / decoding circuit (CODEC) 11 and 12, a selection circuit 13, a buffer 14, a detection circuit 15, a counting circuit 16, and a phase locked loop (PLL). Circuit 17. The PLL circuit 17 has a voltage controlled oscillation circuit 18.
Multiplexer 100 receives serial data IBCH and supplies serial data IBCH to any one of a plurality of channels CH0 to CH31 to which an order has been assigned.
[0003]
Multiplexer 100 detects buffer 14 to which serial data IBCH is input, designation signal SCH for specifying a channel from serial data IBCH, and data for dividing serial data IBCH into fixed lengths, for example, every 8 bits. A detection circuit 15 that detects a synchronization signal; a voltage controlled oscillation circuit (VCO) 18 that generates an oscillation signal having a cycle shorter than a detection interval KP at which the detection circuit 15 detects the data synchronization signal; And a selection circuit 13 that selects each of the channels CH0 to CH30 before the last channel CH31 among the plurality of channels CH0 to CH31 within the detection interval KP according to the order.
[0004]
The buffer 14 is connected to an integrated services digital network (ISDN) 35 via a network termination device 30. Reference numeral 31 is a channel, reference numerals 32 and 33 are B channels, and reference numeral 34 is a D channel.
When detecting the data synchronization signal from the serial data IBCH, the detection circuit 15 outputs a detection signal ISYNC to the PLL circuit 17.
The PLL circuit 17 has a frequency dividing circuit (not shown) that divides the clock signal from the voltage controlled oscillation circuit 18 by 256 (= 8 × 32), and the frequency of the frequency-divided signal matches the detection signal ISYNC. Has been.
The oscillation signal from the voltage controlled oscillation circuit 18 is supplied as a clock signal PCMCLK to the counting circuit 16 and the CODECs 11 and 12.
[0005]
The counting circuit 16 is a 256-ary counter, counts pulses of the clock signal PCMCLK, and outputs a count signal PCMA corresponding to the count value to the selection circuit 13.
The counting circuit 16 outputs a count signal indicating 0 when the count value is 0 to 7, outputs a count signal indicating 1 when the count value is 8 to 15, and outputs a count signal indicating 16 when the count value is 16 to 23. The same applies to the case where the count signal indicating 2 is output and the count value is another value. When the count value is 248 to 255, the count signal indicating 31 is output. The counting circuit 16 outputs a count signal indicating a quotient obtained by dividing the count value by 8.
The selection circuit 13 inputs the serial data IBCH from the buffer 14 from the terminal IN, inputs the designation signal SCH from the detection circuit 15 from the terminal SC, and inputs the count signal PCMA from the counting circuit 16 from the terminal CNT.
Terminals T0 to T31 of the selection circuit 13 are connected to the plurality of channels CH0 to CH31, respectively.
[0006]
The selection circuit 13 outputs the serial data IBCH supplied to the terminal IN to the channel during a period in which the count value indicated by the count signal PCMA matches the channel number indicated by the designation signal SCH.
In this way, the serial data IBCH from the buffer 14 is supplied to the channel selected by the selection circuit 13 and indicated by the designation signal SCH at regular intervals. The serial data IBCH is composed of, for example, 48 bits and one frame.
[0007]
A CODEC 11 is connected to the channel CH 0, and serial data PCMIN and a synchronization signal PCMSYNC are supplied from the selection circuit 13 to the CODEC 11.
The CODEC 11 decodes the serial data PCMIN and outputs it to the telephone line 2. A telephone 1 is connected to the telephone line 2.
A transmission signal from the telephone 1 is encoded by the CODEC 11 and supplied to the selection circuit 13 as serial data PCMOUT. The serial data PCMOUT is supplied to the service integrated digital network 35 via the network termination circuit 30.
A CODEC 12 is connected to the channel CH1, and the CODEC 12 decodes the serial data from the selection circuit 13 and outputs it to the telephone line 6. A facsimile 5 is connected to the telephone line 6.
A personal computer may be connected to the other channel via the CODEC.
The CODECs 11 and 12 operate in synchronization with the clock signal PCMCLK.
[0008]
2 and 3 are time charts for explaining the operation of the multiplexing apparatus 100 of FIG. In FIG. 2, symbols P0 to P14 are pulses of the clock signal PCMCLK, and eight periods of the clock signal PCMCLK are represented by a period t.
Symbols D1 to D8 and E1 to E8 each indicate 1-bit data, and 8-bit data is transferred in a period t.
The CODEC 11 is supplied with a clock signal PCMCLK from the PLL circuit 17, and is supplied with serial data PCMOUT and its synchronization signal PCMSYNC from the selection circuit 13.
The CODEC 11 inputs serial data PCMOUT from the selection circuit 13 using the clock signal PCMCLK, and outputs serial data PCMIN to the selection circuit 13 using the clock signal PCMCLK.
The terminals T0 to T31 of the selection circuit 13 may be configured to be wired and connected so as to be in an open state after the supply of the serial data PCMIN is completed.
[0009]
In FIG. 3, when the count signal PCMA has a value of 0 to 31, it is represented as CH0 to CH31 corresponding to the plurality of channels.
The detection signal ISYNC and the 8-bit data of the serial data IBCH are synchronized. A symbol KP is a detection interval at which the detection circuit 15 detects the data synchronization signal.
[0010]
[Problems to be solved by the invention]
In the multiplexing apparatus 100 of FIG. 1, since the phase synchronization is performed using the PLL circuit 17, the configuration is complicated and the cost is high.
An object of the present invention is to provide a multiplexing device that does not require the PLL circuit 17.
[0011]
[Means for Solving the Problems]
According to the present invention, in a multiplexing device that inputs serial data and supplies the serial data to any one of a plurality of channels that have been given a sequence in advance, a buffer that inputs the serial data, and the serial data A detection circuit that detects a designation signal that designates a channel, and further detects a data synchronization signal that divides the serial data into fixed lengths; and a constant cycle shorter than a detection interval at which the detection circuit detects the data synchronization signal An oscillation circuit that generates a clock signal, and a selection circuit that selects each of the plurality of channels prior to the last channel within the detection interval according to the order, the selection circuit comprising: , At the first rise or rise of the clock signal after the detection of the data synchronization signal by the detection circuit. Select the first channel from the time Ri, wherein the predetermined period for each switch the selection of each channel, following the each channel selects the last channel, the first channel when the first rising time or falling And the buffer outputs the serial data input to the buffer to the selection circuit, and the serial data output to the selection circuit is a channel selected by the selection circuit and the designation signal is Is supplied to the indicated channel at every fixed length.
[0012]
In the multiplexing apparatus according to the present invention , preferably, the detection interval is larger than a multiplication value obtained by multiplying the constant period by a value smaller by 1 from the plurality, and the constant period is multiplied by a value larger by 1 from the plurality. Smaller than the multiplied value.
[0013]
The selection circuit selects the first channel from the first rising edge or falling edge of the clock signal after the detection of the data synchronization signal by the detection circuit.
Then, the selection circuit switches the selection of each channel at the certain period. Each channel is selected according to a predetermined order.
The serial data from the buffer is supplied to the channel selected by the selection circuit and indicated by the designation signal at regular intervals.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 4 is a block diagram showing an example of the multiplexing apparatus of the present invention.
The multiplexing apparatus 10 receives the serial data IBCH and supplies the serial data IBCH to any one of a plurality of channels CH0 to CH31 to which an order has been assigned.
[0015]
Multiplexer 10 detects buffer 14 for inputting serial data IBCH, designation signal SCH for designating a channel from serial data IBCH, and further detects a data synchronization signal for dividing serial data IBCH into fixed lengths Detecting circuit 15 that generates the clock signal PCMCLK having a constant period T shorter than the detection interval KP at which the detection circuit 15 detects the data synchronization signal, and the last of the plurality of channels CH0 to CH31. And a selection circuit 13 that selects each of the channels CH0 to CH30 before the channel CH31 within the detection interval KP according to the order.
The selection circuit 13 selects the first channel CH0 from the first rising edge or falling edge of the clock signal PCMCLK after the detection of the data synchronization signal by the detection circuit 13, and each of the above-mentioned each cycle T Switches the selection of channels CH0 to CH30.
The buffer 14 outputs the serial data IBCH to the selection circuit 13, and the serial data IBCH output to the selection circuit 13 is a channel selected by the selection circuit 13 and indicated by the designation signal SCH. For example, every 8 bits are supplied for each fixed length.
[0016]
The selection circuit 13 selects the last channel CH31 following the channels CH0 to CH30, and switches the selection to the first channel CH0 at the time of the first rising or falling.
The quotient obtained by dividing the detection interval KP by the fixed period T is a value smaller than the plurality or one or more than the plurality. The quotient is, for example, 32 or 31.
The detection interval KP is larger than a multiplication value obtained by multiplying the constant period T by a value smaller by 1 from the plurality, and smaller than a multiplication value obtained by multiplying the constant period T by a value larger by 1 from the plurality.
The serial data IBCH has a frame structure, and the designation signal SCH is incorporated for each frame in the serial data IBCH. The serial data IBCH may constitute one frame with 48 bits.
[0017]
The multiplexing device 10 decodes the serial data IBCH output from the selection circuit 13 and supplies it to the telephone lines 2 and 6, and encodes serial data from the telephone lines 2 and 6 to the selection circuit 13. Coding / decoding circuits (CODEC) 11 and 12 are provided.
The frequency of the clock signal PCMCLK is, for example, 2048 kHz.
Multiplexer 10 receives serial data IBCH from integrated service digital network 35.
[0018]
The buffer 14 is connected to an integrated services digital network (ISDN) 35 via a network termination device 30. Reference numeral 31 is a channel, reference numerals 32 and 33 are B channels, and reference numeral 34 is a D channel. The buffer 14 inputs / outputs serial data IBCH every 8 bits.
When the detection circuit 15 detects a data synchronization signal from the serial data IBCH, the detection circuit 15 outputs a detection signal ISYNC to the counting circuit 22.
The oscillation signal from the oscillation circuit 21 is supplied as a clock signal PCMCLK to the counting circuit 22 and the CODECs 11 and 12.
[0019]
The counting circuit 22 has a 256-ary counter, counts pulses of the clock signal PCMCLK, and outputs a count signal PCMB corresponding to the count value to the selection circuit 13.
The counting circuit 22 outputs a count signal indicating 0 when the count value is 0 to 7, outputs a count signal indicating 1 when the count value is 8 to 15, and outputs a count signal indicating 16 when the count value is 16 to 23. The same applies to the case where the count signal indicating 2 is output and the count value is another value. When the count value is 248 to 255, the count signal indicating 31 is output. The counting circuit 22 outputs a count signal indicating a quotient obtained by dividing the count value by 8.
The selection circuit 13 inputs the serial data IBCH from the buffer 14 from the terminal IN, inputs the designation signal SCH from the detection circuit 15 from the terminal SC, and inputs the count signal PCMB from the counting circuit 22 from the terminal CNT.
Terminals T0 to T31 of the selection circuit 13 are connected to the plurality of channels CH0 to CH31, respectively.
[0020]
The selection circuit 13 outputs the serial data IBCH supplied to the terminal IN to the channel during a period in which the count value indicated by the count signal PCMB matches the channel number indicated by the designation signal SCH.
In this way, the serial data IBCH from the buffer 14 is supplied to the channel selected by the selection circuit 13 and indicated by the designation signal SCH at regular intervals.
[0021]
A CODEC 11 is connected to the channel CH 0, and serial data PCMIN and a synchronization signal PCMSYNC are supplied from the selection circuit 13 to the CODEC 11.
The CODEC 11 decodes the serial data PCMIN and outputs it to the telephone line 2. A telephone 1 is connected to the telephone line 2.
A transmission signal from the telephone 1 is encoded by the CODEC 11 and supplied to the selection circuit 13 as serial data PCMOUT. The serial data PCMOUT is supplied to the service integrated digital network 35 via the network termination circuit 30.
A CODEC 12 is connected to the channel CH1, and the CODEC 12 decodes the serial data from the selection circuit 13 and outputs it to the telephone line 6. A facsimile 5 is connected to the telephone line 6.
The CODECs 11 and 12 operate in synchronization with the clock signal PCMCLK.
[0022]
5 and 6 are time charts for explaining the operation of the multiplexing apparatus 10 of FIG.
PCMB {circle around (1)} in the figure indicates a count signal PCMB in an ideal case where 32 times the fixed period T is equal to the detection interval KP.
PCMB (2) in the figure indicates a count signal PCMB in a practical case where the detection interval KP is different from 32 times the fixed period T, and 32 × T> KP.
PCMB (3) in the figure indicates a count signal PCMB in a practical case where the detection interval KP is different from 32 times the fixed period T, and 32 × T <KP.
The detection interval KP may vary due to factors such as season and time.
[0023]
5 and 6, when the value of the count signal PCMB is 0 to 31, they are represented as CH0 to CH31 corresponding to the plurality of channels, respectively.
The detection signal ISYNC and the 8-bit data of the serial data IBCH are synchronized.
[0024]
In FIG. 5, the period TS in which the value of the count signal PCMB is 31 is shorter than the certain period T.
Further, the value of the count signal PCMB is reset to 0 from the rising edge of the detection signal ISYNC.
This is a case where the rising edge of the detection signal ISYNC coincides with the rising edge of the clock signal PCMCLK.
When the rising edge of the detection signal ISYNC does not coincide with the rising edge of the clock signal PCMCLK, the value of the count signal PCMB is reset to 0 at the first rising edge of the clock signal PCMCLK after the rising edge of the detection signal ISYNC.
After that, the value of the count signal PCMB is incremented by 1 every fixed period T.
[0025]
In FIG. 6, the period TL in which the value of the count signal PCMB is 31 is longer than the certain period T.
Further, the value of the count signal PCMB is reset to 0 from the rising edge of the detection signal ISYNC.
This is a case where the rising edge of the detection signal ISYNC coincides with the rising edge of the clock signal PCMCLK.
When the rising edge of the detection signal ISYNC does not coincide with the rising edge of the clock signal PCMCLK, the value of the count signal PCMB is reset to 0 at the first rising edge of the clock signal PCMCLK after the rising edge of the detection signal ISYNC.
After that, the value of the count signal PCMB is incremented by 1 every fixed period T.
[0026]
The configuration of the counting circuit 22 includes a logical product circuit that calculates a logical product (AND) of a signal that is high when the value of the count signal PCMB is 31, a detection signal ISYNC, and a clock signal PCMCLK. When the output of the product circuit is at a high level, the value of the count signal PCMB may be reset to 0 and the count value of the counting circuit 22 may be reset to 0. As an example, the detection signal ISYNC is set to a high level only about twice the fixed period T.
[0027]
Thus, in the multiplexing apparatus 10, the channel CH31 is used for phase adjustment.
When serial data is input from the B channels 32 and 33 of the integrated service digital network 35, the communication speed is 64 kbps (64000 bits / second), and the transmission integrated device connected to the integrated service digital network 35 or 64 kHz is 64 kHz. It operates using the clock signal.
On the other hand, the multiplexing apparatus 10 has a communication speed of 2048 kbps on the channels CH0 to CH31, and operates using a 2048 kHz clock signal PCMCLK.
The two clock signals have different oscillation circuits as oscillation sources.
[0028]
For this reason, as shown in the time charts of FIGS. 5 and 6, there may occur a case where the detection interval KP and 32 times the fixed period T do not coincide with each other. Can reliably allocate a fixed time T, and can allocate eight pulses of the clock signal PCMCLK to each of the channels CH0 to CH30.
In this way, it is possible to form the multiplexing apparatus 10 that does not require a PLL circuit for synchronizing the phase with the clock signal used in the service integrated digital network 35.
[0029]
In the multiplexing apparatus 10 of the present embodiment, the frequency of the clock signal PCMCLK is set to 2048 kHz and 32 times the frequency of the clock signal used in the integrated service digital network 35 or the like, which is 32 times, so that a total of 31 data transfer channels are secured. can do.
Another frequency may be used as the frequency of the clock signal PCMCLK, and the number of channels may be set to another value.
For example, the frequency of the clock signal PCMCLK may be 1536 kHz, a plurality of channels may be 24 channels, the counting circuit 22 may be provided with a 192-ary counter, and the 24th channel may be used for phase adjustment.
[0030]
As an example, the serial data IBCH from the integrated service digital network 35 may be pulse code modulated (PCM) audio data for the telephone set 1.
As an example, the serial data IBCH from the service integrated digital network 35 may be pulse code modulated image data for the facsimile 5.
A facsimile may be connected to the telephone line 2 instead of the telephone 1.
In addition, the said embodiment is an example of this invention and this invention is not limited to the said embodiment.
[0031]
【The invention's effect】
According to the present invention, it is possible to provide a multiplexing device that does not require a PLL circuit.
The PLL circuit requires a voltage-controlled oscillation circuit, a phase comparison circuit, a low-pass filter, and the like. However, the multiplexing device of the present invention can use an oscillation circuit with a simple configuration that outputs an oscillation signal with a constant period. Therefore, the cost of the multiplexing device can be reduced, and the multiplexing device can be reduced in size.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an example of a conventional multiplexing device.
FIG. 2 is a time chart for explaining the operation of the multiplexing device of FIG. 1;
FIG. 3 is a time chart for explaining the operation of the multiplexing device of FIG. 1;
FIG. 4 is a block diagram illustrating an example of a multiplexing device according to the present invention.
FIG. 5 is a time chart for explaining the operation of the multiplexing device of FIG. 4;
6 is a time chart for explaining the operation of the multiplexing device of FIG. 4;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Telephone (T), 2, 6 ... Telephone line, 5 ... Facsimile (F), 10, 100 ... Multiplexer, 11, 12 ... Coding / decoding circuit (CODEC), 13 ... Selection circuit (SEL) , 14 ... buffer (BF), 15 ... detection circuit, 16, 22 ... counting circuit, 17 ... phase-locked loop circuit (PLL circuit), 18 ... voltage controlled oscillation circuit (VCO), 21 ... oscillation circuit (CLK), 30 Network termination device (NT), 31 ... Channel, 32, 33 ... B channel, 34 ... D channel, 35 ... Integrated service digital network (ISDN), CH0 to CH31 ... Channel, IBCH ... Serial data, ISYNC ... Detection signal, KP: detection interval, PCMCLK: clock signal, PCMSYNC: synchronization signal, SCH: designation signal.

Claims (5)

In a multiplexing device that inputs serial data and supplies the serial data to any one of a plurality of channels that have been given an order in advance,
A buffer for inputting the serial data;
A detection circuit that detects a designation signal that designates a channel from the serial data, and further detects a data synchronization signal that divides the serial data into predetermined lengths;
An oscillation circuit that generates a clock signal having a fixed period shorter than a detection interval at which the detection circuit detects the data synchronization signal;
A selection circuit that selects each channel prior to the last channel among the plurality of channels within the detection interval according to the order;
The selection circuit selects a first channel from the first rising edge or falling edge of the clock signal after the detection of the data synchronization signal by the detection circuit, and switches the selection of each channel at each predetermined period. Selecting the last channel following each channel, switching the selection to the first channel at the first rising or falling edge,
The buffer outputs the serial data input by the buffer to the selection circuit, and the serial data output to the selection circuit is the channel selected by the selection circuit and the channel indicated by the designation signal Multiplexer supplied for each length. 2. The multiplex according to claim 1, wherein the detection interval is larger than a multiplication value obtained by multiplying the constant period by a value smaller by 1 from the plurality, and smaller than a multiplication value obtained by multiplying the constant period by a value larger by 1 from the plurality. Device. The multiplexing apparatus according to claim 1, wherein the serial data has a frame structure, and the designation signal is incorporated in the serial data for each frame. The multiplexing device decodes the serial data output from the selection circuit and supplies it to the telephone line, and encodes and decodes the serial data from the telephone line and supplies the serial data to the selection circuit The multiplexing device according to claim 1. The plurality is 32;
The fixed length is 8 bits;
The frequency of the clock signal is 2048 kHz,
The serial data is pulse code modulated data,
The buffer receives serial data from the integrated services digital network,
The multiplexing apparatus according to claim 1, wherein a communication speed of the integrated service digital network is different from a communication speed of the plurality of channels.

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