JP3434769B2 - Digital multiplex transmission device, digital multiplex transmission system, and digital multiplex transmission method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital multiplex transmission apparatus and method, and more particularly, to a digital multiplex transmission apparatus and a digital multiplex transmission for assigning transmission slots to a plurality of digital streams having arbitrary and different digital information rates. The present invention relates to a system and a digital multiplex transmission method.

[0002]

2. Description of the Related Art Conventionally, as a typical example of such a method of allocating transmission slots of a multiplexing frame to a plurality of digital streams and performing multiplexing, TDM (Time Division Multiplexing) and A so-called time division multiplex transmission system is known.

That is, in the time division multiplex transmission system, time slots for transmitting each digital stream are set in advance in a multiplexed frame, and each digital stream is transmitted after being multiplexed in the set time slot. Then, the receiving side carries out transmission of digital data between transmission and reception by a procedure of taking out a desired digital stream from a preset time slot.

Here, a signal set in advance for multiplexing each of the digital streams in each time slot is multiplexed in a part of a multiplexed frame or uses another signaling transmission channel. Is transmitted to the receiving side. Since there are many documents and examples of the technical contents described above, the citation of specific technical documents is omitted.

On the other hand, in addition to such a time division multiplex transmission system called TDM, there is a packet multiplex transmission system, and in recent years, it has been known as one of its applied technical fields such as digital television broadcasting service and digital video / audio. For services, etc., MPEG-2 standard (ISO / IEC
MPE which is a digital stream of 13818-1)
G-2 transport stream (hereinafter referred to as transport stream) is used in digital multiplex transmission, in which digitally compressed video /
Digital information such as voice is transmitted by 188-byte fixed-length transport packets (hereinafter referred to as TS packets).

A PID field for identifying a packet is arranged in the header portion of the TS packet, and video, audio, data, etc. carried in the payload portion of the TS packet,
By assigning different PID values depending on the information to be carried, such as section data of a table showing the association between TS packets transmitting the element streams that make up a digital television broadcast program and PID values, one transport stream It is possible to selectively receive a desired program from one or more digital television broadcast programs that are multiplexed together.

When one digital stream containing a plurality of digital television broadcast programs is organized and distributed or broadcast by a service provider as one service unit, the plurality of digital streams are Digitally multiplex the data into a single digital stream, which is shared by a single satellite repeater or a digital modulator for wired transmission. At the receiving side, the digital service of the desired service is selected from the multiple multiplexed digital streams. Separation and reception of streams are required for efficient use of frequency resources and economicization.

A method for meeting the above social demands is
A specific example thereof is disclosed in Japanese Patent Application Laid-Open No. 6-276169. In this conventional technique, a transmission path for transmitting digital information is divided into a plurality of transmission slots, and when transmitting digital information such as video / audio / data in the form of packets, digital information belonging to the same service is used. The constructed packet is multiplexed only in one or a plurality of specific transmission slots in the transmission path and transmitted to the receiving side.

In the above-mentioned prior art document in which this conventional technique is described, for the purpose of providing the technique, when a large number of various relatively low speed information are integrally transmitted, a receiving process is performed even by a low speed receiver. Although it is described that it provides a method for enabling it, it also discloses one method for the above request. Hereinafter, the method for the above request disclosed in the prior art document will be specifically described.

As shown in FIG. 21, in the method disclosed in the above-mentioned prior art document, the transmitting device 102b takes in a digital stream of video data, audio data or other data to be transmitted, and an error correction encoder circuit. Each packet output from the error correction encoder circuit 105 based on slot information preset in the slot encoder circuit 106 or slot information input from the outside by adding an error correction check bit at 105. Data is assigned to slots corresponding to each service and multiplexed.

Here, the packet encoder circuit 115 takes in the previously set slot information and slot information inputted from the outside, packetizes it, and outputs it to the error correction encoder circuit 105. That is,
The error correction encoder circuit 105 outputs the packet data in which the error correction check bit is added to the slot information, and the frame encoder circuit 107 outputs the packet data multiplexed for each slot in the slot encoder circuit 106. After loading, adding a synchronization signal for frame synchronization, or further adding a synchronization signal for synchronizing in packet units to the header of each packet, the data in each slot is sequentially and cyclically selected and the modulation circuit 8 The frame data sequentially output from the frame encoder circuit 107 is digitally modulated by the modulation circuit 108 according to a preset modulation method, and is sent to the digital information transmission path 103 to the receiving device 104b. To transmit.

In the receiving device 104b, the demodulation circuit 109 performs digital demodulation to reproduce the received data, and the frame decoder circuit 110 captures the above synchronization signal in the received data output from the demodulation circuit 109. The received data is separated based on the capture result, the packet data for each slot is reproduced, and the packet decoder circuit 116
First, by controlling the slot decoder circuit 111, the packet data multiplexed in the slot in which the slot information is transmitted is selected, and this packet data is input to the error correction decoder 112 for error correction.

Thereafter, the packet decoder circuit 116 takes in the packet data output from the error correction decoder circuit 112 and reproduces the slot information, and thereafter the slot decoder circuit 11 is based on this slot information.
1 is controlled so that the slot decoder circuit 111 takes in the packet data for each slot sequentially output from the frame decoder circuit 110, and becomes the reception target based on the slot information input from the slot decoder circuit 111. The slot containing the packet data is limited and the packet data is selected and supplied to the error correction decoder circuit 112. The error correction decoder circuit 112 corrects an error in the data based on the error correction check bit included in the packet data output from the slot decoder circuit 111 and then outputs the error.

[0014]

However, in the above-mentioned conventional technique, a plurality of digital streams having different digital information speeds and having different digital information speeds depending on the service content and the parameter of the information source compression coding are flexibly provided. It cannot be multiplexed efficiently and with high quality. The reason is that in each of these multiplex transmission systems, the slot to be transmitted for each digital stream is set in advance, or is set and specified by the slot information input from the outside.

Therefore, assuming a situation in which the digital information rate changes in a multiplexed digital stream, for example, when the digital information rate increases, the allocation of transmission slots is changed by presetting or setting by external input. Therefore, the number of transmission slots must be increased, and on the other hand, if the number of transmission slots is set in advance to cope with the situation in which the digital information rate has decreased, the digital information rate will actually decrease. During this period, there is a problem that the digital stream cannot be transmitted because it cannot be accommodated in the transmission slot. Furthermore, if the number of transmission slots is used as it was before the reduction of the digital information rate, the transmission slots are used for other digital streams. Since it cannot be assigned to a stream, the multiplexing efficiency becomes poor. There is a problem that.

Also, when a new digital stream is added and transmitted, or when the previously multiplexed digital stream is removed from the multiplexing organization, reassignment / deletion of transmission slots or setting by external input is performed. There is a problem that the change of must be made each time.

When the digital information rate of each digital stream does not completely match the transmission rate according to the set number of transmission slots, the stuffing data is inserted to match the transmission rate and then set. However, there is a problem that the circuit scale becomes large and the cost becomes high in order to prepare for the case where such processing needs to be performed for each digital stream, for example. is there.

Since the transmission slot in the multiplexed frame is set and specified, the delay time from the input of a packet until the packet is multiplexed in the transmission slot is the set transmission slot. When the packet is input immediately before and when the packet is input immediately after the transmission slot is transmitted, there is a time difference of one cycle of the multiplexed frame between them.

In addition to the above-mentioned problems, in the above-mentioned prior art, in the case of a digital stream such as digital television broadcasting for transmitting and servicing MPEG-2 standard video / audio coded data in real time, a receiver is used. A large amount of jitter is added to the transmission delay time of the program clock reference (PCR) that is being transmitted to recover the system time clock, which is the standard for the video / audio display time, so that the receiver recovers a stable system time clock. There is a problem that it becomes difficult to do.

In the MPEG-2 standard, PCR is a sampling of the system time in the encoder system on the transmitter side at a cycle of 100 milliseconds or less. The system time is a value indicated by a system clock counter driven by a system clock having a frequency of 27 MHz, the lower digit is represented by 9 bits, the upper digit is represented by 33 bits, and the lower digit is a base 300 system. . That is, every 300 cycles of the system clock, the lower digit becomes 0 and the value of the upper digit advances by 1. PCR is a PC
A packet identifier PID indicating that R is included is transmitted in a TS packet (hereinafter referred to as a PCR_PID packet) having a header part.

In the decoder system on the receiver side, the PC included in the PCR_PID packet is received every time the PCR_PID packet is received from the encoder system.
The contents of R are compared with the system time built in the decoder system at the time of receiving the PCR_PID packet. In the decoder system, a system time recovery operation of synchronizing the built-in system time and the frequency of the system clock with the encoder system is performed based on the comparison result. On the other hand, the presentation time information PST (Presentation Time Stamp) is attached to each presentation unit of the video / audio encoded data transmitted from the encoder system, and the presentation of the video / audio is performed by the restored system. Since it is performed with reference to the time, the video and audio are correctly reproduced and output in synchronization.

Such a system time recovery function is based on the assumption that the transmission delay time from the sampling time of the system time in the encoder system to the time when the transmitted PCR_PID packet is received by the decoder system is constant. Is. If the transmission delay time fluctuates, the PCR contained in the received PCR_PID packet is equivalent to the fluctuation of the system time information for the system time recovery function. It is difficult to perform an accurate and stable system time recovery.

Therefore, in the MPEG-2 standard, the error (hereinafter referred to as PCR jitter) added to the PCR is ± 500 nanoseconds or less in consideration of the performance of the phase-locked loop processing for the system time recovery in the decoder system. It is stipulated that

For example, when a plurality of MPEG-2 standard TS packet format digital streams are multiplexed and transmitted, the multiplexing delay time fluctuates in this multiplexing, so that the PCR received by the receiver is multiplexed. The PCR jitter equivalent to the variation amount of the delay time is included equivalently.

MPEG-2 standard Annex D (ISO / IEC138
18-1 Annex D), in the case of re-multiplexing operation for generating one new transport stream from one or more transport streams, PCR correction is necessary, and the following (Equation 7) is required on the transmitter side. It is noted that the correction calculated in (1) is added to the PCR. ΔPCR = delact−delconst (Equation 7)

Here, delact is the actual delay time added to one PCR_PID packet by the re-multiplexing operation, and delconst is the PCR_PI concerned.
It is a constant used for all PCR_PID packets that are periodically transmitted in the program (program) to which the D packet belongs, and is the average value of the delay times added to all the TS packets constituting the program by the re-multiplexing operation. It is an offset term considered.

However, since this is a general concept, those skilled in the art will understand that the system time information PCR in multiplexing.
PCR in light of the mechanism of delay time
It is necessary to realize the correction method of.

FIG. 22 is a block diagram showing a schematic configuration of a conventional digital multiplex transmission apparatus. In this conventional example, a plurality of programs are selected from three input streams in the transport stream format and multiplexed. It shows a case where one transport stream is generated and transmitted.

This digital multiplex transmission apparatus comprises a digital multiplex circuit 220, a PCR correction amount generation circuit 280, a PC.
R correction circuit 291, PSI insertion circuit 292, and PS
It is composed of an I memory 293. In the digital multiplexing circuit 220, the PID filter / conversion circuit 21
1a is connected to the input stream A, PID filter / conversion circuit 211b is connected to the input stream B,
An input stream C is connected to the PID filter / conversion circuit 211c.

Of the TS packets transmitted in the input stream A, the PID filter / conversion circuit 211a passes only the TS packets with the packet identifier PID of the program to be multiplexed, and the other packet identifiers. The attached TS packet is blocked and output to the buffer memory 221a. At this time, the PID filter / conversion circuit 211a passes TSs that do not overlap with the packet identifiers PID of TS packets input to the other buffer memories 221b and 221c.
The value of the packet identifier PID of the packet is rewritten and output.

Similarly, the PID filter / conversion circuit 211
b is a packet identifier P of a program to be multiplexed among TS packets transmitted in the input stream B.
Only the TS packets to which the ID is attached are passed, and the TS packets to which the other packet identifiers are attached are blocked and output to the buffer memory 221b. At this time, the PID filter / conversion circuit 211b uses the other buffer memory 22
The value of the packet identifier PID of the TS packet to be passed is rewritten and output so as not to overlap with the packet identifier PID of the TS packet input to the 1a and the buffer memory 221c.

Similarly, the PID filter / conversion circuit 211
c is a packet identifier P of a program to be multiplexed among TS packets transmitted in the input stream C.
Only the TS packets to which the ID is attached are passed, and the TS packets to which the other packet identifiers are attached are blocked and output to the buffer memory 221c. At this time, the PID filter / conversion circuit 211c determines that the other buffer memory 22
The value of the packet identifier PID of the TS packet to be passed is rewritten and output so as not to overlap with the packet identifier PID of the TS packet input to the 1a and the buffer memory 221b.

The output of the PID filter / conversion circuit 211a is connected to the PCR packet input detection circuit 281a,
The output of the PID filter / conversion circuit 211b is connected to the PCR packet input detection circuit 281b, and the output of the PID filter / conversion circuit 211c is connected to the PCR packet input detection circuit 281c.

For example, the buffer memories 221a to 221
Both c are FIFO (First-In FIRs).
t-Out) type memory. The buffer memory 221a stores the TS packets that have passed through the PID filter / conversion circuit 211a, and stores the TS packets in the buffer memory 221b.
Is the TS that has passed through the PID filter / conversion circuit 211b.
The packets are accumulated, and the buffer memory 221c stores the PID
The TS packets that have passed through the filter / conversion circuit 211c are accumulated.

The output of the buffer memory 221a is connected to the multiplexing circuit 229 and the PCR packet output detection circuit 288a, and the output of the buffer memory 221b is the multiplexing circuit 2
29 and the PCR packet output detection circuit 288b, and the output of the buffer memory 221c is the multiplexing circuit 229.
And a PCR packet output detection circuit 288c. In addition, the stuffing packet memory 226 stores null packets in advance.

The multiplexing circuit 229 is provided in the buffer memory 221.
The TS packets stored in a, 221b, and 221c are extracted, multiplexed, and output to the PCR correction circuit 291. In addition, the buffer memories 221a, 221b, and 2
When no TS packet is stored in any of 21c, the multiplexing circuit 229 reads the null packet from the stuffing packet memory 226 and multiplexes it, and the
Output to the R correction circuit 291. PCR correction circuit 291
Outputs the output of the selector 19 by arithmetically adding the output of the selector 19 to the PCR field value of the PCR_PID packet input from the multiplexing circuit 229.

The PSI memory 293 stores in advance a plurality of TS packets for transmitting PSI (program specific information). The PSI includes the correspondence between the organization of each program that is multiplexed and output and the program number, and the TS packet that transmits the number of each program that is multiplexed and output and the element stream such as video / audio that constitutes the program. The correspondence with the packet identifier PID of the PCR_PID packet is shown.

The PSI insertion circuit 292 is used by the PSI memory 2
The TS packets are sequentially read from 93, inserted into the output of the PCR correction circuit 291, and output. At this time, the PSI insertion circuit 292 reads the TS packet from the PSI memory 293 every time a fixed time has elapsed, and the null packet included in the output of the PCR correction circuit 291 is set to the PSI memory 2.
The TS packet read from 93 is replaced and output.

The PCR packet input detection circuit 281a is
It is detected that the PCR_PID packet is input to the buffer memory 211a, and the PCR input detection signal is output to the delay measurement counter 286a. The PCR packet input detection circuit 281b detects that the PCR_PID packet is input to the buffer memory 211b, and outputs a PCR input detection signal to the delay measurement counter 286b. The PCR input detection circuit 281c detects that the PCR_PID packet is input to the buffer memory 211c, and outputs a PCR input detection signal to the delay measurement counter 286c.

The delay measurement counter 286a sets the count value to an initial value each time a PCR input detection signal is input from the PCR packet input detection circuit 281a, and
Start counting 27 MHz clock pulses. The delay measurement counter 286b sets the count value to the initial value and starts counting the 27 MHz clock pulse each time the PCR input detection signal is input from the PCR packet input detection circuit 281b. Delay measurement counter 28
6c is a PC from the PCR packet input detection circuit 281c.
Each time the R input detection signal is input, the count value is set to the initial value and counting of 27 MHz clock pulses is started.

The PCR packet output detection circuit 288a is
The output of the PCR_PID packet is detected from the buffer memory 221a, and the PCR output detection signal is output to the register 287a and the selector 283. The PCR packet output detection circuit 288b detects that the PCR_PID packet is output from the buffer memory 221b,
The CR output detection signal is sent to the register 287b and the selector 28.
Output to 3. PCR packet output detection circuit 288c
Detects that a PCR_PID packet has been output from the buffer memory 221c, and outputs a PCR output detection signal to the register 287c and the selector 283.

The register 287a holds the count value of the delay measurement counter 286a at the time when the PCR output detection signal is input every time the PCR output detection signal output from the PCR packet output detection circuit 288a is input, and the selector 283 stores the count value. Output. Each time the PCR output detection signal output from the PCR packet output detection circuit 288b is input, the register 287b holds the count value of the delay measurement counter 286b at the time when the PCR output detection signal is input, and outputs it to the selector 283. The register 287c is
P output from the PCR packet output detection circuit 288c
Each time the CR output detection signal is input, the count value of the delay measurement counter 286c at the time when the PCR output detection signal is input is held and output to the selector 283.

When the PCR output detection signal output from the PCR packet output detection circuit 288a is input, the selector 283 selects the count value held in the register 287a and outputs it to the PCR correction circuit 291 for PCR.
When the PCR output detection signal output from the packet output detection circuit 288b is input, the count value held in the register 287b is selected and output to the PCR correction circuit 291 and output from the PCR packet output detection circuit 288c. When the PCR output detection signal is input, the count value held in the register 287c is selected and output to the PCR correction circuit 291. In addition, P from any of the PCR packet output detection circuits 288a, 288b, and 288c.
When no CR output detection signal is input, the selector 283
Outputs a zero value to the PCR correction circuit 291.

Next, the operation of the digital multiplex transmission apparatus according to this conventional example will be described.

Among the programs included in each of the input streams A, B and C, the TS packet of the program to be multiplexed is the PID filter / conversion circuit 211a, 211.
b, 211c, and the respective buffer memories 22
After being written in 1a, 221b and 221c, they are taken out by the multiplexing circuit 229 and packet-multiplexed.

Each buffer memory 221a, 221b, 2
21c absorbs the speed difference between the TS packet input speed and the multiplexing speed of each program, and the TS packet input speed and the multiplexing output speed of each program are asynchronous and different from each other. Permissible. Also,
Even if the TS packet input speed of each program varies, the buffer memories 221a, 221b, 221c
Absorbs the speed difference from the multiplexed output speed.

The multiplexing circuit 229 is provided in each buffer memory 22.
1a, 221b, 221c monitor the storage amount of TS packets, and when the input TS packet is not stored in any of the buffer memories 221a to 221c,
Null packets are read from the stuffing memory 226 and multiplexed, and at least one buffer memory 2 is provided.
When the inputted TS packets are accumulated in 21a to 221c, the inputted TS packets are taken out from the buffer memory and multiplexed.

Each buffer memory 221a, 211b, 2
When a TS packet is extracted from 21c and multiplexed, any method can be used for the multiplexing control performed in the multiplexing circuit 229, but the multiplexing delay jitter is as small as possible for stable operation of the decoder system. In addition, the buffer memories 221a to 221c are controlled to perform multiplexing so that TS packet loss due to overflow does not occur.

In the digital multiplex transmission apparatus as in this prior art example, the multiplexing delay jitter is different from each buffer memory 22.
It occurs in 1a, 221b, and 221c. In order to cope with such a multiplexing delay jitter, in this conventional example, the PCR packet input detection circuits 281a to 281c are provided on the input side of each buffer memory 221a, 221b, 221c, and the PCR packet output detection circuit 288a is provided on the output side. ~ 288
It is configured to include c. As a result, in this conventional example, the PCR_PID packet is transmitted to the buffer memory 221a.
˜221c and the buffer memory 221a
~ 221c and the time point output from each are detected, and P
The CR_PID packet is stored in the buffer memories 221a to 221a.
The time to pass 1c is measured.

For example, when the PCR_PID packet is input to the buffer memory 221a, the input is detected by the PCR packet input detection circuit 281a, and the PCR input detection signal is output to the delay measurement counter 286a. After that, the PCR_PID packet is transferred to the buffer memory 221.
When output from a, the output is detected by the PCR packet output detection circuit 288a, and the PCR output detection signal is output to the register 287a. In this conventional example, the time taken for the PCR_PID packet to pass through the buffer memories 221a to 221c is measured based on these detection signals. Details of this PCR_PID packet transit time measurement operation will be described later.

When the PCR input detection signal is input, the delay measurement counter 286a sets the count value to an initial value and starts counting 27 MHz clock pulses. When this initial value is a negative number of the average value of the delay times added to all TS packets to be multiplexed, this initial value becomes a value corresponding to the term -delconst in (Equation 7). Each delay measurement counter 286a, 286
b and 286c are composed of a 300-ary counter that outputs the lower digit in a 9-bit binary representation, and the upper digit has a maximum of 33.
By configuring a binary counter of bits, P
A count value having the same data format as CR is output.

When the PCR_PID packet is output from the buffer memory 221a, it is detected by the PCR packet output detection circuit 288a and the PCR output detection signal is output to the register 287a and the selector 283. At this time, the register 287a has the delay measuring counter 286a.
Read and hold the count value of. Therefore, the count value held at this time is calculated from the time required for the PCR_PID packet to pass through the buffer memory 221a.
It is a value showing the time obtained by subtracting the average delay time added to all the TS packets to be multiplexed, and shows the variation of the delay time, that is, the multiplexing delay jitter. This corresponds to ΔPCR in (Equation 7).

At the same time, the selector 283 selects the count value held by the register 287a and outputs it to the PCR correction circuit 291. On the other hand, the PCR correction circuit 291 receives the multiplexed PCR_PID packet extracted from the buffer memory 221a by the multiplexing circuit 229. Therefore, in the PCR correction circuit 291, the PCR_PID packet is stored in the buffer memory 221a.
The amount of multiplexing delay jitter generated when passing through the PCR
Is added and output. Similarly, for the PCR_PID packet in the input stream B and the PCR_PID packet in the input stream C, the multiplexing delay jitter equivalent amount that occurs when passing through the buffer memory 221b or the buffer memory 221c is added to the PCR, and P
It is output from the CR correction circuit 291.

However, in the packet multiplex transmission apparatus in the above conventional example, when there are a plurality of programs to be multiplexed and output in one input stream,
Since the PCR of the PCR_PID packet included in each program is corrected, there is a problem that the circuit scale is significantly increased.

The reason is that in one input stream,
It is possible to include multiple programs, each with an independent time base, and each program may have different PCR_PID packets. From this, it is necessary to equip one input stream with the same number of circuits for measuring the multiplexing delay time as the number of programs to be multiplexed.

The PCR_PID packet is usually several 10
Ms to 100 ms (upper limit is MPEG-2
Specified) time interval. For example, by making the transit time of the buffer memory smaller than 1
If only one program is selected and multiplexed from each input stream, the PCR detection circuits that should be provided on the input side and the output side of the buffer memory are 1 each.
The number of delay measurement counters may be one, and one delay measurement counter may be provided for each input stream.

However, when a plurality of programs are selected from one input stream to be multiplexed, these plurality of program contents are multiplexed in one input stream through different production processes or transmission paths. There is a possibility that it has been entered as In that case, the PCR_PID packets included in different programs have indefinite transmission time points and transmission time intervals, so that one buffer memory may have PCR_PID packets of different programs at the same time. .

Therefore, for one buffer memory,
The input side and the output side respectively have a PCR input detection circuit, P
If the CR output detection circuits are provided one by one, it is not possible to accurately detect the input time point of the same PCR_PID packet into the buffer memory and the output time point from the buffer memory.

Therefore, depending on the number of programs to be multiplexed from one input stream, PCR_PID
Circuits for detecting packets and delay measurement counters must be provided in the same number as the number of programs. Therefore, in this conventional example, there arises a problem that the circuit scale required for PCR correction increases in proportion to the multiplexing program per input stream.

In the case of operating multi-channel digital broadcasting, the number of programs to be selected and multiplexed from one input stream is changed according to the change or switching of the broadcast channel organization or broadcast program organization. Alternatively, the number of input streams may be changed. For this reason, assuming the maximum value of the number of programs to be multiplexed, it is necessary to preliminarily equip the number of PCR correction circuits capable of supporting the maximum number of programs. However, when the number of programs to be actually multiplexed is small, there is a problem that a part of a circuit for correcting the PCR, which is installed in advance according to the maximum number of programs, is wasted.

Further, as in the case where a plurality of programs are selected from one input stream to be multiplexed as described above, the input interval of the PCR_PID packet of one program is the time during which it passes through the buffer memory. Even when inputting at a shorter interval than the PCR, the PCR is configured with one PCR input detection circuit and one PCR output detection circuit on each of the input side and the output side of one buffer memory.
When trying to detect a PID packet, the same PCR_
There is a problem in that it is not possible to accurately detect the time when the PID packet is input to the buffer memory and the time when the PID packet is output from the buffer memory. Furthermore, if the buffer memory size is reduced in order to avoid this, next, a new problem arises in that there is a risk of overflow.

The present invention has been made in view of the above problems, and flexibly and efficiently multiplexes a plurality of digital streams having different digital information rates and varying digital information rates with less delay jitter. An object of the present invention is to provide a digital multiplex transmission device, a digital multiplex transmission system, and a digital multiplex transmission method that can be converted and transmitted.

Further, according to the present invention, the circuit scale is not increased according to the number of multiplexed programs per input stream, that is, different PCR_PID packet types.
An object of the present invention is to provide a digital multiplex transmission device capable of correcting PCR jitter generated by a multiplexing operation.

[0064]

In order to achieve such an object, according to the invention of claim 1 of the present invention, digital multiplex transmission in which a plurality of digital streams are multiplexed and transmitted in respective transmission slots of a multiplexed frame In the device,
Slot allocation information generating means for generating allocation information for each transmission slot of digital data forming each digital stream according to the transmission rate of each digital stream, and input data for each digital stream.
Amount of data transmitted in one transmission slot of digital data
Data amount detecting means for detecting the time when the data reaches
And the slot allocation information generating means is
The digital stream whose time point has been detected by the data amount detecting means.
It is characterized in that the slot allocation information of the program is generated, each digital stream is multiplexed according to the generated slot allocation information, the slot allocation information is added to the multiplexed frame, and the multiplexed frame is transmitted to the receiving side.

[0065] According to the second aspect of the invention, wherein
In the digital multiplex transmission apparatus according to item 1 , the slot allocation information is generated based on the detected time.

Further, according to the third aspect of the present invention, wherein
In the digital multiplex transmission apparatus according to item 2 , the slot allocation information generating means generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot whose time point was detected by the digital data amount detecting means. It is characterized by doing.

[0067] According to the fourth aspect of the present invention, wherein
In the digital multiplex transmission apparatus according to the item 2 or 3 , the slot allocation information generating means is multiplexed when the digital data amount detecting means detects no time point for any digital stream within one cycle of the transmission slot. The number of slot allocation information generated within one cycle of the transmission slot in which the time point was not detected is greater than the number of transmission slots transmitted within the one cycle of the transmission slot in which the time point was not detected If the number is small, the stuffing data allocation information is generated for the immediately following transmission slot.

[0068] According to the invention described in claim 5, wherein
In the digital multiplex transmission apparatus according to any one of Items 2 to 4 , when the slot allocation information generating means detects time points for a plurality of digital streams within one cycle of the transmission slot by the digital data amount detecting means. , Slot generation information for the same number of consecutive transmission slots immediately after the transmission slot is generated.

Further, according to the invention described in claim 6, wherein
In the digital multiplex transmission device according to any one of items 2 to 5 , the slot allocation information generating means is configured to detect the digital data amount detecting means within one cycle of the transmission slot immediately before the transmission slot in which the slot allocation information has been generated. The slot allocation information of the digital stream whose time point is detected is
The slot allocation information is generated immediately after the transmission slot for which the slot allocation information has been generated, for the transmission slot for which the slot allocation information has not been generated.

[0070] According to the invention described in claim 7, wherein
In the digital multiplex transmission apparatus according to any one of items 2 to 6 , when the slot assignment information generating means generates the slot assignment information for each transmission slot for one cycle of the multiplexing frame, In addition, when the time point is detected for the digital stream, the allocation information of the digital stream is generated for the transmission slot of the multiplexed frame immediately after the multiplexed frame.

[0071] Further, according to the invention of claim 8, wherein
In the digital multiplex transmission apparatus according to any one of Items 2 to 7 , the slot assignment information generating means assigns a slot to a transmission slot that transmits slot assignment information among the transmission slots forming the multiplexed frame. It is characterized by not generating information.

According to the invention described in claim 9, in a digital multiplex transmission apparatus for multiplexing and transmitting a plurality of digital streams in each transmission slot of a multiplexed frame, the input digital data is located in each digital stream. A data amount detecting means for detecting that the fixed quantity is reached and outputting a detection signal for each detected digital stream, and a retiming means for retiming and outputting each detection signal with a clock signal synchronized with a transmission slot cycle. A pulse generating means for generating a plurality of pulse signals having different phases for each cycle of the clock signal, and re-timing the passage of each pulse signal corresponding to the digital stream among the plurality of pulse signals by the pulse generating means. Each digital stream controlled by the input of the detected signal First pulse signal passage control means provided for each, and slot assignment information generation means for generating assignment information for transmission slots of a digital stream corresponding to the pulse signal passed through the first pulse signal passage control means, Write address value setting means for advancing and setting the write address value by one each time slot allocation information is generated, transmission slot counting means for counting the number of transmission slots transmitted in one cycle of the multiplexing frame, and transmission. If the lower write address value in the same write address value as the count value by the slot counting means and the count value are compared, and the result of the comparison is that the lower address value is smaller than the count value, it is true. Corresponding to the digital stream of the plurality of pulse signals generated by the magnitude comparing means for outputting a value and the pulse generating means. Second pulse signal passage control means for controlling passage of one pulse signal other than the loose signal by inputting a true value, and transmission of stuffing data by inputting the pulse signal passing through the second pulse signal passage control means. Slot allocation information generating means for generating allocation information for slots, write address value setting means for advancing and setting a write address value by one each time the slot allocation information is generated, and a lower part of the write address value. A means for generating a signal indicating that the write address value has reached a value equal to the number of transmission slots in one multiplexing frame, and a write setting for advancing the write address value by one each time the signal is generated. The built-in address value setting means and slot allocation information for the transmission slots of the digital stream and the stuffing data are set as the write address value. Storage means for storing and holding at an address according to the write address value set by the storage means, and transmission slot allocation information for one multiplexed frame during one cycle of the multiplexed frame stored by the storage means And the allocation information reading means for holding and storing the write address value set to the slot, and reading and outputting the slot allocation information stored at the address of the storage means indicated by the write address value. A digital multiplex transmission device characterized in that each digital stream and stuffing data are multiplexed according to the slot allocation information, the slot allocation information is added to the multiplexed frame, and the multiplexed frame is transmitted to the receiving side.

According to the invention of claim 10, the contract
The digital multiplex transmission device according to claim 9 is characterized in that the predetermined amount is the amount of data transmitted in one transmission slot.

According to the invention of claim 11, the contract
In the digital multiplex transmission device according to claim 9 or 10, the range of the write address value set by the write address value setting means is set to be twice the number of the transmission slots of one multiplexed frame. And

According to the twelfth aspect of the present invention, in a digital multiplex transmission apparatus for multiplexing a plurality of packet-format digital streams in each transmission slot of a multiplexed frame and transmitting the multiplexed streams, the digital multiplex transmission apparatus is arranged according to the transmission rate of each digital stream. , Slot allocation information generating means for generating allocation information for each transmission slot of a packet forming each digital stream, and for each digital stream,
A packet in which the input packet is transmitted in one transmission slot.
Packet number detection means for detecting the time when the number of packets reaches
The slot allocation information generating means has a packet number detecting means.
Slot of the digital stream whose time point was detected
It is characterized in that the slot allocation information is generated , each digital stream is multiplexed according to the generated slot allocation information, the slot allocation information is added to the multiplexed frame, and the multiplexed frame is transmitted to the receiving side.

According to the invention of claim 13, the contract
In the digital multiplex transmission apparatus Motomeko 12 wherein the slot allocation information, and generating based on the detected time point.

According to the invention of claim 14, the contract
In the digital multiplex transmission device according to claim 13 , the slot allocation information generation means generates allocation information of the corresponding digital stream for the transmission slot immediately after the transmission slot whose time point was detected by the packet number detection means. It is characterized by doing.

According to the invention of claim 15, the contract
In the digital multiplex transmission device according to claim 13 or 14 , the slot allocation information generating means is a multiplexing means when the packet number detecting means detects no time point for any digital stream within one cycle of the transmission slot. The number of slot allocation information generated within one cycle of the transmission slot in which the time point was not detected is greater than the number of transmission slots transmitted within one cycle of the transmission slot in which the time point was not detected If the number is small, the stuffing packet allocation information for the immediately following transmission slot is generated.

According to the invention of claim 16, the contract
In the digital multiplex transmission apparatus according to any one of claims 13 to 15 , when the slot allocation information generating means detects time points for a plurality of digital streams within one cycle of the transmission slot by the packet number detecting means, It is characterized by generating slot allocation information for the same number of consecutive transmission slots immediately after the transmission slot.

According to the invention of claim 17, the contract
In the digital multiplex transmission apparatus according to any one of claims 13 to 16 , the slot allocation information generating means is configured to detect the packet number within one cycle of the transmission slot immediately before the transmission slot for which the slot allocation information has been generated. The slot allocation information of the digital stream of which the time point is detected is generated for the transmission slot immediately after the transmission slot for which the slot allocation information has been generated and for which the slot allocation information has not been generated.

According to the invention of claim 18, the contract
In the digital multiplex transmission apparatus according to any one of claims 13 to 17 , the slot allocation information generating means, when the slot allocation information for each transmission slot for one cycle of the multiplexing frame is generated, Further, in the cycle, when the time point is detected for the digital stream, the allocation information of the digital stream is generated for the transmission slot of the multiplexed frame immediately after the multiplexed frame.

According to the invention of claim 19, the contract
In the digital multiplex transmission apparatus according to any one of claims 13 to 18 , the slot allocation information generating means is a slot for the transmission slot for transmitting the slot allocation information among the transmission slots forming the multiplexed frame. It is characterized in that the allocation information is not generated.

According to the twentieth aspect of the invention, in a digital multiplex transmission apparatus for multiplexing a plurality of packet-format digital streams in respective transmission slots of a multiplexed frame and transmitting the packets, a packet input for each digital stream is inputted. Has reached a predetermined amount and outputs a detection signal for each detected digital stream, and a re-timing means for retiming each detection signal with a clock signal synchronized with the transmission slot cycle. Of the timing means, the pulse generation means for generating a plurality of pulse signals having different phases for each cycle of the clock signal, and the plurality of pulse signals by the pulse generation means,
First pulse signal passage control means provided for each digital stream for controlling passage of each pulse signal corresponding to a digital stream by inputting a retimed detection signal, and first pulse signal passage control Slot allocation information generating means for generating allocation information for transmission slots of a digital stream corresponding to a pulse signal passing through the means, and writing for advancing and setting a write address value by one each time the slot allocation information is generated. Address value setting means, transmission slot counting means for counting the number of transmission slots transmitted in one cycle of the multiplexing frame,
When the lower write address value in the write address value having the same digit as the count value by the transmission slot counting means is compared with the count value, and as a result of the comparison, the lower address value is smaller than the count value, A second comparator for controlling the passage of one pulse signal other than the pulse signal corresponding to the digital stream among the plurality of pulse signals generated by the magnitude comparing means for outputting the true value and the pulse generating means by inputting the true value. By inputting the pulse signal passing control means and the pulse signal passed through the second pulse signal passing control means, slot allocation information generating means for generating allocation information for the transmission slot of the stuffing packet, and each time slot allocation information is generated. , Write address value setting means for advancing and setting the write address value by one, and Means for generating a signal indicating that the write address value of the highest order has reached a value equal to the number of transmission slots of one multiplexed frame, and each time the signal is generated, the write address value is further advanced by 1 and set. Write address value setting means, storage means for storing and holding the slot allocation information for the transmission slots of the digital stream and the stuffing packet at an address corresponding to the write address value set by the write address value setting means, ,
The address of the storage means, which holds the write address value set when the allocation information of the transmission slot for one multiplexed frame is stored by the storage means in one cycle of the multiplexed frame, and which is indicated by the write address value The slot allocation information stored in the slot allocation information is read out and output, the packet and the stuffing packet of each digital stream are multiplexed according to the slot allocation information read out by the allocation information reading means, and the slot is multiplexed into the multiplexed frame. It is characterized in that a packet containing allocation information is added and transmitted to the receiving side.

According to the invention of claim 21, the contract is made.
The digital multiplex transmission device according to claim 20 is characterized in that the predetermined amount is the amount of data transmitted in one transmission slot.

According to the invention of claim 22, the contract
In the digital multiplex transmission device according to claim 20 or 21, the range of the write address value set by the write address value setting means is set to 2 of the number of transmission slots of one multiplexed frame.
It is characterized by being doubled.

According to the twenty-third aspect of the present invention, in a digital multiplex transmission apparatus for multiplexing a plurality of packet-format digital streams in each transmission slot of a multiplexed frame and transmitting the stuffing packets included in each digital stream. The stuffing packet removing means for removing and the allocation information for each transmission slot of the effective packet forming each digital stream is generated according to the transmission rate of the effective packet of each digital stream from which the stuffing packet has been removed by the stuffing packet removing means. Slot allocation information generating means, each digital stream is multiplexed according to the generated slot allocation information, the slot allocation information is added to the multiplexed frame, and the multiplexed frame is transmitted to the receiving side.

According to the invention of claim 24, the contract
In the digital multiplex transmission apparatus according to claim 23 , the digital multiplex transmission apparatus further includes, for each digital stream, a valid packet number detecting means for detecting a time point at which the number of input valid packets reaches a predetermined number, and slot allocation is performed. The information generating means is characterized by generating slot allocation information of the digital stream of which the time point is detected by the effective packet number detecting means.

Further, according to the invention of claim 25 ,
The digital multiplex transmission device according to claim 24 is characterized in that the predetermined number is the number of effective packets transmitted in one transmission slot.

According to the invention of claim 26, the contract
The digital multiplex transmission device according to claim 24 or 25 is characterized in that the slot allocation information is generated based on the detected time.

Further, according to the invention of claim 27 ,
In the digital multiplex transmission device according to claim 26 , the slot allocation information generation means generates allocation information of the corresponding digital stream for the transmission slot immediately after the transmission slot whose time point is detected by the packet number detection means. It is characterized by doing.

Further, according to the invention of claim 28 ,
In the digital multiplex transmission apparatus according to claim 26 or 27 , the slot allocation information generating means, when the effective packet number detecting means detects no time point for any digital stream within one cycle of the transmission slot, If the number of slot allocation information generated by one transmission slot whose time is not detected within one cycle of the multiplexing frame is less than the number of transmission slots transmitted by that time, the next transmission slot It is characterized in that it generates allocation information of a stuffing packet for.

Further, according to the invention of claim 29 ,
In the digital multiplex transmission apparatus according to any one of claims 26 to 28 , when the slot allocation information generating means detects the time points for a plurality of digital streams within one cycle of the transmission slot by the effective packet number detecting means. , Slot generation information for the same number of consecutive transmission slots immediately after the transmission slot is generated.

According to the invention of claim 30, the contract
30. In the digital multiplex transmission apparatus according to any one of claims 26 to 29 , the slot allocation information generation means is means for detecting the number of effective packets within one cycle of the transmission slot immediately before the transmission slot for which the slot allocation information has been generated. The slot allocation information of the digital stream of which the time point is detected is generated for the transmission slot immediately after the transmission slot for which the slot allocation information has been generated and for which the slot allocation information has not been generated.

According to the invention of claim 31, the contract
In the digital multiplex transmission apparatus according to any one of claims 26 to 30 , the slot allocation information generating means, when the slot allocation information for each transmission slot for one cycle of the multiplexing frame is generated, the multiplexing frame Further, in the cycle, when the time point is detected for the digital stream, the allocation information of the digital stream is generated for the transmission slot of the multiplexed frame immediately after the multiplexed frame.

According to the invention of claim 32, the contract
In the digital multiplex transmission apparatus according to any one of claims 26 to 31 , the slot allocation information generating means is a slot for the transmission slot for transmitting the slot allocation information among the transmission slots forming the multiplexed frame. It is characterized in that the allocation information is not generated.

According to a thirty-third aspect of the invention, in a digital multiplex transmission apparatus for multiplexing a plurality of packet format digital streams in respective transmission slots of a multiplexing frame and transmitting the stuffing packets included in each digital stream. A stuffing packet removing means for removing and a valid packet for detecting that a predetermined number of valid packets of each digital stream from which the stuffing packet has been removed by the stuffing packet removing means have been input and outputting a detection signal for each detected digital stream. Number detecting means, retiming means for retiming and outputting each detection signal with a clock signal synchronized with the transmission slot cycle, and pulse generating means for generating a plurality of pulse signals having different phases for each cycle of the clock signal. And a first pulse provided for each digital stream for controlling passage of each of the pulse signals corresponding to the digital stream among the plurality of pulse signals by the pulse generating means by inputting the retimed detection signal. Signal pass control means, slot assignment information generation means for generating assignment information for transmission slots of the digital stream corresponding to the pulse signal passed through the first pulse signal pass control means, and each time slot assignment information is generated, Write address value setting means for advancing the write address value by one, transmission slot counting means for counting the number of transmission slots transmitted in one cycle of the multiplexing frame, and the same digit as the count value by the transmission slot counting means The lower write address value of the write address value of is compared with the count value, As a result of the comparison, when the lower address value is smaller than the count value, the magnitude comparing means for outputting a true value and the pulse signal corresponding to the digital stream among the plurality of pulse signals generated by the pulse generating means To the transmission slot of the stuffing packet by the second pulse signal passage control means for controlling the passage of one pulse signal other than the above by a true value input and the input of the pulse signal passed through the second pulse signal passage control means. Slot allocation information generating means for generating allocation information, and each time slot allocation information is generated,
Further, it indicates that the write address value setting means for advancing the write address value by one, and that the lower write address value in the write address value has reached a value equal to the number of transmission slots of one multiplexed frame. A means for generating a signal, a write address value setting means for advancing and setting a write address value by one each time a signal is generated, and slot allocation information for transmission slots of a digital stream and a stuffing packet are written. Storage means for storing and holding at an address according to the write address value set by the address value setting means, and further, storage means for storing transmission slot allocation information for one multiplexing frame during one cycle of the multiplexing frame. The slot that holds the write address value that was set when it was stored, and is stored at the address of the storage means indicated by the write address value And an assignment information reading means reads and outputs those information, a valid packet and stuffing packets for each digital stream are multiplexed in accordance with the slot allocation information read out by the assignment information reading means,
It is characterized in that a packet containing slot allocation information is added to the multiplexed frame and transmitted to the receiving side.

Further, according to the invention of claim 34 ,
The digital multiplex transmission apparatus according to claim 33 is characterized in that the predetermined number is the number of effective packets transmitted in one transmission slot.

According to the invention of claim 35, the contract
In the digital multiplex transmission device according to claim 33 or 34, the range of the write address value set by the write address value setting means is set to 2 of the number of transmission slots of one multiplexed frame.
It is characterized by being doubled.

According to a thirty-sixth aspect of the present invention, in a digital multiplex transmission method for multiplexing a plurality of digital streams in respective transmission slots of a multiplexed frame for transmission, the digital multiplex transmission method is performed according to the transmission rate of each digital stream.
A slot allocation information generating step of generating allocation information for each transmission slot of digital data forming each digital stream, and an input for each digital stream.
Digital data that is transmitted in one transmission slot.
Data amount detection to detect when the data amount is reached
And the slot allocation information generation step,
Digit whose time point was detected in the digital data amount detection process
Slot allocation information for each stream, multiplex each digital stream according to the generated slot allocation information, add slot allocation information to the multiplexed frame,
It is characterized in that it is transmitted to the receiving side.

According to a thirty-seventh aspect of the present invention, in the digital multiplex transmission method according to the thirty- sixth aspect, the slot allocation information is generated based on the detected time point.

Further, according to the invention of claim 38 ,
In the digital multiplex transmission method according to claim 37 , in the slot allocation information generating step, in the digital data amount detecting step, the allocation information of the corresponding digital stream is assigned to the transmission slot immediately after the transmission slot in which the time point is detected. It is characterized by generating.

Further, according to the invention of claim 39 ,
In the digital multiplex transmission method according to claim 37 or 38 , in the slot allocation information generating step, when the time point is not detected for any digital stream in one cycle of the transmission slot in the digital data amount detecting step, If the number of slot allocation information generated by one transmission slot whose time is not detected within one cycle of the multiplexing frame is less than the number of transmission slots transmitted by that time, the next transmission slot It is characterized by generating stuffing data allocation information for.

Further, according to the invention of claim 40 ,
40. In the digital multiplex transmission method according to any one of claims 37 to 39 , the slot allocation information generating step includes the step of detecting the digital data amount within one cycle of the transmission slot.
When time points are detected for a plurality of digital streams, slot allocation information for the same number of consecutive transmission slots immediately after the transmission slot is generated.

Further, according to the invention of claim 41 ,
40. In the digital multiplex transmission method according to any one of claims 37 to 40 , the slot allocation information generating step is performed by the digital data amount detecting means within one cycle of the transmission slot immediately before the transmission slot for which the slot allocation information has been generated. The slot allocation information of the digital stream whose time point has been detected is generated for the transmission slot immediately after the transmission slot for which the slot allocation information has been generated and for which the slot allocation information has not been generated.

Further, according to the invention of claim 42 ,
42. In the digital multiplex transmission method according to any one of claims 37 to 41 , the slot allocation information generating step includes: when the slot allocation information for each transmission slot for one cycle of the multiplexing frame is generated, one cycle of the multiplexing frame is generated. In addition, when the time point is detected for the digital stream, the allocation information of the digital stream is generated for the transmission slot of the multiplexed frame immediately after the multiplexed frame.

According to the invention of claim 43, the contract
43. In the digital multiplex transmission method according to any one of claims 37 to 42 , the slot allocation information generating step includes a slot for the transmission slot for transmitting the slot allocation information among the transmission slots forming the multiplexed frame. It is characterized in that the allocation information is not generated.

According to the 44th aspect of the present invention, in a digital multiplex transmission method of multiplexing a plurality of digital streams in respective transmission slots of a multiplexed frame and transmitting the multiplexed digital streams, the input digital data is stored in each digital stream. A data amount detection step of detecting that a fixed amount has been reached and outputting a detection signal for each detected digital stream, and a retiming step of retiming and outputting each detection signal with a clock signal synchronized with the transmission slot cycle. A pulse generating step of generating a plurality of pulse signals having different phases for each cycle of the clock signal, and re-timing the passage of each pulse signal corresponding to the digital stream among the plurality of pulse signals in the pulse generating step. Each digital stream controlled by the input of the detected signal A first pulse signal passage control step provided for each system, and a slot assignment information generation step of generating assignment information for transmission slots of a digital stream corresponding to the pulse signal passed through the first pulse signal passage control step. A write address value setting step of advancing and setting a write address value by one each time slot allocation information is generated, and a transmission slot counting step of counting the number of transmission slots transmitted in one cycle of the multiplexing frame, When the lower write address value in the same write address value as the count value in the transmission slot counting step is compared with the count value, and as a result of the comparison, the lower address value is a value smaller than the count value. , Of the multiple pulse signals generated from the magnitude comparison process that outputs the true value and the pulse generation process, Of the stuffing data by the second pulse signal passage control step of controlling the passage of one pulse signal other than the pulse signal to be controlled by the input of the true value and the input of the pulse signal passed through the second pulse signal passage control step. A slot allocation information generating step of generating allocation information for a transmission slot, a write address value setting step of advancing and setting a write address value by one each time the slot allocation information is generated, and a lower order of the write address value. Generating a signal indicating that the write address value has reached a value equal to the number of transmission slots of one multiplexed frame, and each time the signal is generated, the write address value is further advanced by 1 and set. The write address value setting process and slot allocation information for the transmission slots of the digital stream and the stuffing data are written in the write address. The storage step of storing and holding at an address according to the write address value set by the step value setting step, and the transmission slot allocation information for one multiplexing frame during one cycle of the multiplexing frame are stored by the storing step. An allocation information reading step of holding the write address value set at the time of reading, and reading and outputting the slot allocation information stored at the address of the storage step indicated by the write address value. It is characterized in that each digital stream and stuffing data are multiplexed according to the read slot allocation information, the slot allocation information is added to the multiplexed frame, and the multiplexed frame is transmitted to the receiving side.

Further, according to the invention of claim 45 ,
The digital multiplex transmission method according to claim 44 is characterized in that the predetermined amount is the amount of data transmitted in one transmission slot.

Further, according to the invention of claim 46 ,
In the digital multiplex transmission method according to claim 44 or 45, the range of the write address value set in the write address value setting step is set to 2 of the number of transmission slots of one multiplexed frame.
It is characterized by being doubled.

According to the forty-seventh aspect of the present invention, in a digital multiplex transmission method for multiplexing a plurality of packet-format digital streams in respective transmission slots of a multiplexed frame for transmission, the digital multiplex transmission method is performed according to the transmission rate of each digital stream. , A slot allocation information generating step of generating allocation information for each transmission slot of a packet forming each digital stream, and for each digital stream,
A packet in which the input packet is transmitted in one transmission slot.
Packet number detection step for detecting the time when the number of packets reaches
In the slot allocation information generation process, the number of packets is detected.
Slot of digital stream whose time point was detected in the process
The present invention is characterized in that the slot allocation information is generated , each digital stream is multiplexed according to the generated slot allocation information, the slot allocation information is added to the multiplexed frame, and the multiplexed frame is transmitted to the receiving side.

Further, according to the invention of claim 48 ,
The digital multiplex transmission method according to claim 47 is characterized in that the slot allocation information is generated based on the detected time.

Further, according to the invention of claim 49 ,
In the digital multiplex transmission method according to claim 48 , the slot allocation information generating step generates corresponding digital stream allocation information for a transmission slot immediately after the transmission slot in which the time point is detected in the packet number detecting step. It is characterized by doing.

Further, according to the invention of claim 50 ,
In the digital multiplex transmission method according to claim 48 or 49 , the slot allocation information generating step is performed when the time point of any digital stream is not detected within one cycle of the transmission slot in the packet number detecting step. The number of slot allocation information generated within one cycle of the transmission slot in which the time point was not detected is greater than the number of transmission slots transmitted within one cycle of the transmission slot in which the time point was not detected If the number is small, the stuffing packet allocation information for the immediately following transmission slot is generated.

Further, according to the invention of claim 51 ,
50. In the digital multiplex transmission method according to any one of claims 48 to 50 , when the slot allocation information generating step detects the time points for a plurality of digital streams within one cycle of the transmission slot in the packet number detecting step, It is characterized by generating slot allocation information for the same number of consecutive transmission slots immediately after the transmission slot.

Further, according to the invention of claim 52 ,
52. In the digital multiplex transmission method according to any one of claims 48 to 51 , the slot allocation information generating step includes a packet number detecting step in a cycle immediately before a transmission slot in which the slot allocation information has been generated. The slot allocation information of the digital stream of which the time point is detected is generated for the transmission slot immediately after the transmission slot for which the slot allocation information has been generated and for which the slot allocation information has not been generated.

Further, according to the invention of claim 53 ,
52. In the digital multiplex transmission method according to any one of the items 48 to 52 , the slot allocation information generating step comprises: when the slot allocation information for each transmission slot for one cycle of the multiplexing frame is generated, one cycle of the multiplexing frame is generated. In addition, when the time point is detected for the digital stream, the allocation information of the digital stream is generated for the transmission slot of the multiplexed frame immediately after the multiplexed frame.

Further, according to the invention of claim 54 ,
54. In the digital multiplex transmission method according to any one of claims 48 to 53 , the slot assignment information generating step assigns a slot to a transmission slot for transmitting slot assignment information among the transmission slots forming the multiplex frame. It is characterized by not generating information.

According to the 55th aspect of the present invention, in the digital multiplex transmission method of multiplexing a plurality of packet format digital streams in each transmission slot of a multiplexed frame and transmitting the multiplexed packets, the packet input for each digital stream is inputted. Has reached a predetermined number and outputs a detection signal for each detected digital stream, and outputs each detection signal by retiming with a clock signal synchronized with the transmission slot cycle. The retiming step, the pulse generation step of generating a plurality of pulse signals having different phases for each cycle of the clock signal, and the passage of each pulse signal corresponding to the digital stream among the plurality of pulse signals generated by the pulse generation step , Controlled by input of retimed detection signal, each digit The provided for each Le stream 1
Pulse signal passing control step, slot allocation information generating step for generating allocation information for transmission slots of the digital stream corresponding to the pulse signal passed through the first pulse signal passing control step, and each time slot allocation information is generated. , A write address value setting step of advancing and setting the write address value by one, a transmission slot counting step of counting the number of transmission slots transmitted in one cycle of the multiplexing frame, and a count value by the transmission slot counting step. The lower write address value in the same write address value and the count value are compared, and if the result of the comparison is that the lower address value is smaller than the count value, the true value is output. Of the multiple pulse signals generated in the comparison step and pulse generation step, the pulse signal corresponding to the digital stream Of the stuffing packet to the transmission slot by the second pulse signal passage control step of controlling the passage of one pulse signal of the above by a true value input and the input of the pulse signal passed through the second pulse signal passage control step. A slot allocation information generating step of generating information, a write address value setting step of further advancing the write address value by 1 each time the slot allocation information is generated, and a lower write address in the write address value. A step of generating a signal indicating that the value has reached a value equal to the number of transmission slots of one multiplexing frame, and a write address value set by advancing the write address value by one each time the signal is generated. Setting step and setting write address value for slot allocation information for transmission slots of digital stream and stuffing packet A storage step of storing and holding at an address according to the set write address value, and set when the storage step stores transmission slot allocation information for one multiplexing frame during one cycle of the multiplexing frame An assignment information reading step of reading the slot assignment information stored at the address of the storage step indicated by the write address value and outputting the slot assignment information read step. It is characterized in that the packet of each digital stream and the stuffing packet are multiplexed according to the allocation information, the packet containing the slot allocation information is added to the multiplexed frame, and the packet is transmitted to the receiving side.

[0119] According to the invention of claim 56, claim
55. The digital multiplex transmission method of 55 is characterized in that the predetermined number is the number of packets transmitted in one transmission slot.

Further, according to the invention of claim 57 ,
In the digital multiplex transmission method according to claim 55 or 56, the range of the write address value set in the write address value setting step is set to 2 of the number of transmission slots of one multiplexed frame.
It is characterized by being doubled.

Further, according to the invention described in Item 58, in a digital multiplex transmission method of multiplexing a plurality of packet format digital streams into respective transmission slots of a multiplexing frame and transmitting the multiplexed stuffing packets included in each digital stream. The stuffing packet removing step for removing and the allocation information for each transmission slot of the effective packet forming each digital stream is generated according to the transmission rate of the effective packet of each digital stream from which the stuffing packet has been removed by the stuffing packet removing step. Slot allocation information generating step, each digital stream is multiplexed according to the generated slot allocation information, the slot allocation information is added to the multiplexed frame, and the multiplexed frame is transmitted to the receiving side.

Further, according to the invention of claim 59 ,
In the digital multiplex transmission method according to claim 58 , the digital multiplex transmission method further includes a valid packet number detection step of detecting a time point when the number of input valid packets reaches a predetermined number for each digital stream. The information generation step is characterized in that slot allocation information of the digital stream whose time point is detected in the effective packet number detection step is generated.

Further, according to the invention of claim 60 ,
The digital multiplex transmission method according to claim 59 is characterized in that the predetermined number is the number of effective packets transmitted in one transmission slot.

Further, according to the invention of claim 61 ,
The digital multiplex transmission method according to claim 59 or 60 is characterized in that slot allocation information is generated based on the detected time.

Further, according to the invention of claim 62 ,
In the digital multiplex transmission method according to claim 61 , in the slot allocation information generating step, the allocation information of the corresponding digital stream is allocated to the transmission slot immediately after the transmission slot whose time point is detected in the effective packet number detecting step. It is characterized by generating.

Further, according to the invention of claim 63 ,
In the digital multiplex transmission method according to claim 61 or 62 , in the slot allocation information generating step, when the time point is not detected for any digital stream within one cycle of the transmission slot in the valid packet number detecting step, If the number of slot allocation information generated up to that time within one cycle of the multiplexing frame is smaller than the number of transmission slots transmitted up to that time, allocation information of the stuffing packet for the next transmission slot is generated. It is characterized by

Further, according to the invention of claim 64 ,
64. In the digital multiplex transmission method according to any one of claims 61 to 63 , the slot allocation information generating step detects the time points of a plurality of digital streams within one cycle of the transmission slot in the valid packet number detecting step. , Slot generation information for the same number of consecutive transmission slots immediately after the transmission slot is generated.

Further, according to the invention of claim 65 ,
65. In the digital multiplex transmission method according to any one of claims 61 to 64 , the slot allocation information generating step is performed by the effective packet number detecting means within one cycle of the transmission slot immediately before the transmission slot in which the slot allocation information has been generated. The slot allocation information of the digital stream whose time point has been detected is generated for the transmission slot immediately after the transmission slot for which the slot allocation information has been generated and for which the slot allocation information has not been generated.

According to the invention of claim 66, the contract
In the digital multiplex transmission method according to any one of claims 61 to 65 , the slot allocation information generating step, when the slot allocation information for each transmission slot for one cycle of the multiplexing frame is generated, In addition, when the time point is detected for the digital stream, the digital stream allocation information is generated for the transmission slot of the multiplexed frame immediately after the multiplexed frame.

Further, according to the invention of claim 67, the contract
67. In the digital multiplex transmission method according to any one of items 61 to 66 , the slot assignment information generating step assigns a slot to a transmission slot that transmits slot assignment information among the transmission slots forming the multiplex frame. It is characterized by not generating information.

According to the sixty-eighth aspect of the present invention, in a digital multiplex transmission method for multiplexing a plurality of packet-format digital streams in respective transmission slots of a multiplexing frame and transmitting the multiplexed stuffing packets included in each digital stream. A stuffing packet removal process for removing and a valid packet for detecting that a predetermined number of valid packets of each digital stream from which the stuffing packet has been removed by the stuffing packet removal process have been input and outputting a detection signal for each detected digital stream Number detection step, a retiming step of retiming and outputting each detection signal with a clock signal synchronized with the transmission slot cycle, and a pulse generation step for generating a plurality of pulse signals having different phases for each cycle of the clock signal. And a first pulse provided for each digital stream for controlling the passage of each of the pulse signals corresponding to the digital stream among the plurality of pulse signals in the pulse generation step by inputting the retimed detection signal. A signal passing control step, a slot assignment information generating step of generating assignment information for transmission slots of a digital stream corresponding to the pulse signal passed through the first pulse signal passing control step, and each time slot assignment information is generated, The write address value setting step of advancing the write address value by one, the transmission slot counting step of counting the number of transmission slots transmitted in one cycle of the multiplexing frame, and the same digit as the count value of the transmission slot counting step The lower write address value of the write address value of is compared with the count value, If the lower address value is smaller than the count value as a result of the comparison, among the plurality of pulse signals generated from the magnitude comparison process that outputs the true value and the pulse generation process, except the pulse signal corresponding to the digital stream. The passage of one pulse signal of
A second pulse signal passage control step of controlling by inputting a true value, and a slot assignment information generating step of generating assignment information for a transmission slot of a stuffing packet by input of a pulse signal passed through the second pulse signal passage control step And a write address value setting step of further advancing and setting the write address value by one each time slot allocation information is generated, and a lower write address value in the write address value is transmitted in one multiplexed frame. A step of generating a signal indicating that a value equal to the number of slots has been reached, a step of setting a write address value to increment the write address value by one each time the signal is generated, a digital stream and a stuffing packet The slot allocation information for each transmission slot is set to the write address value set in the write address value setting step. A storage step of storing and holding at a corresponding address and a write address value set when the transmission slot allocation information for one multiplexing frame during one cycle of the multiplexing frame is stored by the storing step , An assignment information reading step of reading and outputting the slot assignment information stored at the address of the storage step indicated by the write address value, and valid packets of each digital stream according to the slot assignment information read in the assignment information reading step. And stuffing packets are multiplexed, a packet containing slot allocation information is added to the multiplexed frame, and the multiplexed frame is transmitted to the receiving side.

Further, according to the invention of claim 69 ,
The digital multiplex transmission method according to claim 68 is characterized in that the predetermined number is the number of effective packets transmitted in one transmission slot.

Further, according to the invention of claim 70 ,
In the digital multiplex transmission method according to claim 68 or 69, the range of the write address value set in the write address value setting step is set to 2 of the number of transmission slots of one multiplexed frame.
It is characterized by being doubled.

According to the seventy-first aspect of the invention, in a digital multiplex transmission apparatus for multiplexing and transmitting a plurality of digital streams in each transmission slot of a multiplexed frame, according to the transmission rate of each digital stream,
Slot allocation information generation means for generating allocation information for each transmission slot of digital data forming each digital stream, and input for each digital stream
Digital data that is transmitted in one transmission slot.
Data amount detection to detect when the data amount is reached
Means leaving, each digital stream to have a multiplexing means for multiplexing in accordance with the generated slot allocation information, Ro
The bit allocation information generating means is a digital data amount detecting means.
Slot of digital stream whose time point was detected at
Generates allocation information and multiplexes the generated slot allocation information.
Multiple digital streams are multiplexed by digitalization means.
It is characterized in that it is added to the duplicated frame and transmitted .

Further, according to the invention of claim 72 ,
In the digital multiplex transmission device according to claim 71 , the slot allocation information generating means is characterized in that the slot allocation information is generated based on the detected time point.

Further, according to the invention of claim 73 ,
In the digital multiplex transmission device according to claim 72 , the slot allocation information generating means generates the allocation information of the corresponding digital stream for the transmission slot immediately after the transmission slot whose time point was detected by the digital data amount detecting means. It is characterized by generating.

Further, according to the invention of claim 74 ,
In the digital multiplex transmission apparatus according to any one of claims 71 to 73 , when the digital data amount detecting means detects a time point for a plurality of digital streams within one cycle of a transmission slot, slot allocation information is generated. The means is characterized in that the slot allocation information is generated for the same number of transmission slots that are consecutive immediately after the transmission slot as detected by the digital data amount detecting means.

Further, according to the invention of claim 75 ,
In the digital multiplex transmission apparatus according to any one of claims 71 to 74 , when the digital data amount detecting means does not detect a time point for any of the digital streams within one cycle of the transmission slot,
The slot allocation information generating means is characterized by generating stuffing data allocation information for a transmission slot immediately after the transmission slot.

According to the invention of claim 76, the contract
In the digital multiplex transmission apparatus according to claim 75 , when the digital data amount detection means detects no time point for any digital stream within one cycle of the transmission slot, and within one cycle of the multiplexing frame. In the case where the number of slot allocation information generated within one period of the transmission slot in which the time point was not detected is smaller than the number of transmission slots transmitted in one period of the transmission slot in which the time point was not detected, The slot allocation information generating means is characterized by generating stuffing data allocation information for a transmission slot immediately after the transmission slot.

Further, according to the invention of claim 77 ,
In the digital multiplex transmission apparatus according to any one of claims 71 to 76, when the time is detected by the digital data amount detection means within one cycle of one transmission slot, and immediately after the transmission slot. When the slot allocation information for the transmission slot has already been generated, the slot allocation information generating means, the slot allocation information generation means, immediately after the transmission slot, the digital stream of which time point is detected for the transmission slot for which the slot allocation information has not been generated. It is characterized in that the slot allocation information is generated.

According to the invention of claim 78, the contract
In the digital multiplex transmission apparatus according to any one of claims 71 to 77 , when the slot allocation information generating means has already generated the slot allocation information for each transmission slot for one cycle of one multiplexed frame. If the digital data amount detecting means detects the time point of the digital stream within one cycle of the multiplexing frame, the slot allocation information generating means determines that the multiplexing data immediately following the multiplexing frame. It is characterized in that allocation information of a digital stream is generated for a transmission slot of a digitized frame.

According to the invention of claim 79, the contract
In the digital multiplex transmission device according to any one of claims 71 to 78 , the digital data amount detecting means detects a plurality of times for one digital stream or each of a plurality of digital streams within one cycle of one transmission slot. In this case, the slot allocation information generating means generates the slot allocation information for the same number of transmission slots as the time point detected by the digital stream amount detecting means immediately after the transmission slot. .

According to the invention of claim 80, the contract
In the digital multiplex transmission apparatus according to claim 71 to 79 , the slot allocation information generating means generates slot allocation information for a transmission slot that transmits the slot allocation information among the transmission slots forming the multiplexed frame. Characterized by not doing.

Further, according to the invention described in Item 81, in a digital multiplex transmission apparatus for multiplexing a plurality of digital streams of a plurality of packet formats into respective transmission slots of a multiplexing frame and transmitting the same, a transmission rate for each digital stream According to the above, slot allocation information generating means for generating allocation information for each transmission slot of a packet forming each digital stream, multiplexing means for multiplexing each digital stream according to the generated slot allocation information, and each digital stream Enter the package
Reach the number of packets transmitted in one transmission slot.
And a packet number detecting means for detecting the
The packet allocation information generating means determines the time point by the packet number detecting means.
The slot allocation information of the detected digital stream
It is characterized by generating information.

According to the invention described in Item 82, in a digital multiplex transmission apparatus for multiplexing a plurality of digital streams of a plurality of packet formats into respective transmission slots of a multiplexing frame and transmitting the stuffing included in each digital stream. The stuffing packet removing means for removing the packet and the allocation information for each transmission slot of the packet included in each digital stream according to the packet transmission speed of each digital stream after the stuffing packet is removed by the stuffing packet removing means. It is characterized in that it has slot generation information generating means for generating and multiplexing means for multiplexing each digital stream according to the generated slot allocation information.

Further, according to the invention of claim 83 ,
In the digital multiplex transmission apparatus according to claim 81 or 82 , the slot allocation information generated by the slot allocation information generating means is added to a multiplexed frame in which each digital stream is multiplexed by the multiplexing means and transmitted. Characterize.

Further, according to the invention of claim 84 ,
In the digital multiplex transmission apparatus according to claim 81 , the slot allocation information generating means is characterized by generating the slot allocation information based on the detected time point.

Further, according to the invention of claim 85 ,
In the digital multiplex transmission device according to claim 84 , the slot allocation information generating means generates allocation information of the corresponding digital stream for the transmission slot immediately after the transmission slot whose time point was detected by the packet number detecting means. It is characterized by doing.

Further, according to the invention described in claim 86 ,
In the digital multiplex transmission apparatus according to claim 81 to 85 , when the packet number detecting means detects a time point for a plurality of digital streams within one cycle of the transmission slot, the slot allocation information generating means causes the transmission slot It is characterized in that the slot allocation information is generated for the same number of transmission slots as the time points detected by the packet number detecting means, which are continuous immediately after.

Further, according to the invention of claim 87, the contract
In the digital multiplex transmission apparatus according to claim 86 , when the packet number detection means detects no time point for any digital stream within one cycle of the transmission slot, and within one cycle of the multiplexing frame. , If the number of slot allocation information generated within one cycle of the transmission slot whose time is not detected is smaller than the number of transmission slots transmitted within one cycle of the transmission slot whose time is not detected, The allocation information generating means is characterized by generating allocation information of a stuffing packet for a transmission slot immediately after the transmission slot.

According to the 88th aspect of the present invention, there is provided a digital multiplex transmission system in which a transmitter multiplexes a plurality of digital streams into respective transmission slots of a multiplexed frame, and the multiplexed frame is transmitted to a receiver. The transmitting device generates slot allocation information generating means for generating allocation information for each transmission slot of digital data forming each digital stream according to the transmission rate of each digital stream, and each digital stream according to the generated slot allocation information. Means to multiplex the input digital signal for each digital stream.
Total amount of data transmitted in one transmission slot
A digital data amount detecting means for detecting the time when it reaches,
Digital data generated by the slot allocation information generation means
Digital stream whose time point is detected by the data amount detection means
The slot allocation information added to the received multiplex frame, and the sending unit sending the additional slot allocation information to the multiplexed frame in which the digital streams are multiplexed by the multiplexing unit. Based on the information
It is characterized in that a desired digital stream is taken out from the multiplexed frame and outputted.

According to the eighty-ninth aspect of the invention, the receiving device separates the slot allocation information from the multiplexed frame, and the desired digital signal from the multiplexed frame based on the separated slot allocation information. And a means for selecting a transmission slot in which stream digital data is multiplexed and outputting the selected digital data.

Further, according to the invention of claim 90 ,
In the digital multiplex transmission system according to claim 88 ,
The slot allocation information generating means is characterized by generating the slot allocation information based on the detected time point.

Further, according to the invention of claim 91 ,
In the digital multiplex transmission system according to claim 90 ,
The slot allocation information generating means is characterized in that the digital data amount detecting means generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot whose time point is detected.

Further, according to the invention of claim 92 ,
In the digital multiplex transmission system according to any one of claims 88 to 91 , when the digital data amount detecting means detects a time point for a plurality of digital streams within one cycle of a transmission slot, slot allocation information is generated. The means is characterized in that the slot allocation information is generated for the same number of transmission slots that are consecutive immediately after the transmission slot as detected by the digital data amount detecting means.

Further, according to the invention of claim 93 ,
In the digital multiplex transmission system according to any one of claims 88 to 92 , when the digital data amount detecting means does not detect a time point for any digital stream within one cycle of the transmission slot, slot allocation information is obtained. The generation means is characterized in that it generates stuffing data allocation information for a transmission slot immediately after the transmission slot.

According to the invention of claim 94, the contract
In the digital multiplex transmission system according to claim 93 ,
When the digital data amount detecting means detects no time point in any one of the digital streams within one cycle of the transmission slot, and within one cycle of the multiplexing frame, the time slot is not detected. When the number of slot allocation information generated within the period is less than the number of transmission slots transmitted within one period of the transmission slot in which the time point was not detected, the slot allocation information generating means immediately after the transmission slot. It is characterized in that stuffing data allocation information is generated for each transmission slot.

Further, according to the invention of claim 95, the contract
In the digital multiplex transmission system according to any one of claims 88 to 94, when the time is detected by the digital data amount detecting means within one cycle of one transmission slot, and immediately after the transmission slot. When the slot allocation information for the transmission slot has already been generated, the slot allocation information generating means, the slot allocation information generation means, immediately after the transmission slot, the digital stream of which time point is detected for the transmission slot for which the slot allocation information has not been generated. It is characterized in that the slot allocation information is generated.

Further, according to the invention of claim 96, the contract
In the digital multiplex transmission system according to any one of Claims 88 to 95 , the slot allocation information generating means,
When the slot allocation information for each transmission slot for one cycle of one multiplexed frame has already been generated, and within one cycle of the multiplexed frame, the digital data amount detecting means further provides the digital stream. When the time point is detected, the slot allocation information generating means generates the digital stream allocation information for the transmission slot of the multiplexed frame immediately after the multiplexed frame.

According to the invention of claim 97, the contract
In the digital multiplex transmission system according to any one of claims 88 to 96 , the digital data amount detecting means detects a plurality of time points for one digital stream or each of a plurality of digital streams within one cycle of one transmission slot. In this case, the slot allocation information generating means generates the slot allocation information for the same number of transmission slots as the time point detected by the digital stream amount detecting means immediately after the transmission slot. .

Further, according to the invention of claim 98 ,
In the digital multiplex transmission system according to claim 88 , the slot allocation information generating means generates slot allocation information for a transmission slot that transmits the slot allocation information among the transmission slots forming the multiplexed frame. Characterized by not doing.

According to the invention described in Item 99, a transmitter multiplexes a plurality of digital streams in a plurality of packet formats into respective transmission slots of a multiplexed frame,
In a digital multiplex transmission system that transmits a multiplexed frame to a receiving device, a transmitting device generates slot allocation information for generating allocation information for each transmission slot of a packet forming each digital stream according to a transmission rate of each digital stream. Generating means, multiplexing means for multiplexing each digital stream according to the generated slot allocation information , and input for each digital stream
The number of packets that can be transmitted in one transmission slot
And a packet number detecting means for detecting the time when the packet arrives,
Detecting the number of packets generated by the slot allocation information generation means
A means for adding slot allocation information of the digital stream whose time point is detected by the means to the multiplexed frame in which the respective digital streams are multiplexed by the multiplexing means, and transmitting the added information. The receiving device is characterized in that it extracts a desired digital stream from the multiplexed frame and outputs it based on the slot allocation information added to the received multiplexed frame.

According to the invention of claim 100,
In a digital multiplex transmission system in which a transmitter multiplexes a plurality of digital streams of a plurality of packet formats into respective transmission slots of a multiplexed frame and transmits the multiplexed frame to a receiver, the transmitter is included in each digital stream. Stuffing packet removing means for removing the stuffing packet and allocation information for each transmission slot of the packet included in each digital stream are generated according to the transmission rate of the packet of each digital stream from which the stuffing packet has been removed by the stuffing packet removing means. Slot allocation information generating means, multiplexing means for multiplexing each digital stream according to the generated slot allocation information, and slot allocation information generated by the slot allocation information generating means by the multiplexing means. And a sending means for sending the digital streams by adding them to the multiplexed frame, and the receiving device selects a desired one from the multiplexed frame based on the slot allocation information added to the received multiplexed frame. It is characterized in that a digital stream is taken out and outputted.

Further, according to the invention of claim 101,
The digital multiplex transmission system according to claim 99 or 100, wherein the receiving device separates the slot allocation information from the multiplexed frame, and a desired digital stream from the multiplexed frame based on the separated slot allocation information. And output means for selecting a transmission slot in which packets are multiplexed and outputting the selected digital data.

According to the invention of claim 102,
102. The digital multiplex transmission system according to claim 101, wherein the receiving device further comprises means for multiplexing the stuffing packet with the output of the digital data from the output means, based on the slot allocation information separated by the separating means. Is characterized by.

Further, according to the invention of claim 103,
The digital multiplex transmission system according to claim 99, wherein the slot allocation information generating means generates the slot allocation information based on the detected time point.

Further, according to the invention of claim 104,
104. The digital multiplex transmission system according to claim 103, wherein the slot allocation information generating means generates allocation information of the corresponding digital stream for the transmission slot immediately after the transmission slot whose time point is detected by the packet number detecting means. It is characterized by doing.

Further, according to the invention of claim 105,
In the digital multiplex transmission system according to any one of claims 102 to 104 , the packet number detecting means,
When the time points are detected for a plurality of digital streams within one cycle of the transmission slot, the slot allocation information generating means transmits the same number of transmissions immediately after the transmission slot as the time point detected by the packet number detecting means. It is characterized in that slot allocation information is generated for each slot.

According to the invention of claim 106,
In the digital multiplex transmission system according to any one of claims 102 to 105 , the packet number detecting means,
When no time point is detected for any of the digital streams within one cycle of the transmission slot, the slot allocation information generating means generates stuffing packet allocation information for the transmission slot immediately after the transmission slot. And

Further, according to the invention of claim 107,
107. The digital multiplex transmission system according to claim 106, wherein when the packet number detecting means detects no time point for any digital stream within one cycle of the transmission slot, and within one cycle of the multiplexing frame. , If the number of slot allocation information generated within one cycle of the transmission slot in which the time is not detected is less than the number of transmission slots transmitted within one cycle of the transmission slot in which the time is not detected, The allocation information generating means is characterized by generating allocation information of a stuffing packet for a transmission slot immediately after the transmission slot.

According to the invention of claim 108,
The digital multiplex transmission system according to any one of claims 102 to 107, wherein when the time point is detected by the packet number detecting means within one cycle of one transmission slot, and the transmission immediately following the transmission slot. When the slot allocation information for the slot has already been generated, the slot allocation information generating means, for the transmission slot immediately after the transmission slot, for which the slot allocation information has not been generated, of the digital stream whose time point has been detected. It is characterized in that slot allocation information is generated.

Further, according to the invention of claim 109,
In the digital multiplex transmission system according to any one of claims 102 to 108 , when the slot assignment information generating means has already generated slot assignment information for each transmission slot for one cycle of one multiplexing frame. If the packet number detecting means detects the time point of the digital stream within one cycle of the multiplexing frame, the slot allocation information generating means determines that the multiplexing immediately following the multiplexing frame. It is characterized in that the allocation information of the digital stream is generated for the transmission slot of the frame.

According to the invention of claim 110,
The digital multiplex transmission system according to any one of claims 102 to 109 , wherein the packet number detection means detects a plurality of times for one digital stream or each of a plurality of digital streams within one cycle of one transmission slot. In this case, the slot allocation information generating means generates the slot allocation information for any one of the transmission slots immediately after the transmission slot, the number of which is the same as the time point detected by the packet number detecting means. To do.

Further, according to the invention of claim 111,
In the digital multiplex transmission system according to any one of claims 99 to 110 , the slot allocation information generating means, for the transmission slots transmitting the slot allocation information among the transmission slots forming the multiplexed frame,
It is characterized in that the slot allocation information is not generated.

According to the invention of claim 112,
In a digital multiplex transmission method in which a plurality of digital streams are multiplexed and transmitted in each transmission slot of a multiplexed frame, allocation information for each transmission slot of digital data forming each digital stream is provided in accordance with the transmission rate of each digital stream. The slot allocation information generation step to generate and for each digital stream,
Input digital data is transmitted through the one transmission slot
Digital data that detects when the amount of data
Data amount detection process and slot allocation information generation process
The time point was detected in the digital data amount detection process.
And a multiplexing step of generating slot allocation information of the digital stream and multiplexing each digital stream according to the generated slot allocation information.

According to the invention of claim 113,
The digital multiplex transmission method according to claim 112 ,
It is characterized in that the slot allocation information generated in the slot allocation information generating step is added to a multiplexed frame in which each digital stream is multiplexed in the multiplexing step and transmitted.

Further, according to the invention of claim 114,
The digital multiplex transmission method according to claim 112 ,
In the slot allocation information generation process, the slot allocation information is
It is characterized in that it is generated based on the time of detection.

According to the invention of claim 115,
The digital multiplex transmission method according to claim 114 ,
In the slot allocation information generating step, the allocation information of the corresponding digital stream is generated for the transmission slot immediately after the transmission slot in which the time point was detected in the digital data amount detecting step.

According to the invention of claim 116,
The digital multiplex transmission method according to any one of claims 112 to 115, wherein in the digital data amount detecting step, when time points are detected for a plurality of digital streams within one cycle of the transmission slot, slot allocation information is generated. In the step, slot allocation information is generated for the same number of transmission slots as the time points detected in the digital data amount detecting step, which are continuous immediately after the transmission slot.

According to the invention of claim 117,
The digital multiplex transmission method according to any one of claims 112 to 116, wherein in the digital data amount detecting step, when the time is not detected for any digital stream within one cycle of the transmission slot, the slot allocation information generating step is performed. , Stuffing data allocation information is generated for a transmission slot immediately after the transmission slot.

According to the invention of claim 118,
The digital multiplex transmission method according to claim 117 ,
In the digital data amount detecting step, when the time point is not detected for any digital stream within one cycle of the transmission slot, and the time point is not detected within one cycle of the multiplexing frame, the transmission slot In the case where the number of slot allocation information generated within the period is less than the number of transmission slots transmitted within one period of the transmission slot in which the time point was not detected, the transmission slot It is characterized in that stuffing data allocation information is generated for the immediately following transmission slot.

According to the invention of claim 119,
The digital multiplex transmission method according to any one of claims 112 to 118, wherein a time slot is detected in the digital data amount detecting step within one cycle of one transmission slot, and the slot for the transmission slot immediately following the transmission slot. If the allocation information has already been generated, in the slot allocation information generation step, the slot allocation of the digital stream whose time point has been detected is assigned to the transmission slot immediately after the transmission slot for which the slot allocation information has not been generated. It is characterized by generating information.

Further, according to the invention of claim 120,
The digital multiplex transmission method according to any one of claims 112 to 119, wherein when the slot assignment information generating step has already generated slot assignment information for each transmission slot for one cycle of one multiplexing frame. If, and within one cycle of the multiplexing frame, the digital data amount detecting step, and when the time point of the digital stream is detected, the slot allocation information generating step continues immediately after the multiplexing frame. It is characterized in that the digital stream allocation information is generated for the transmission slot of the multiplexed frame.

Further, according to the invention of claim 121,
121. The digital multiplex transmission method according to any one of claims 112 to 120 , wherein a time point is detected a plurality of times for one digital stream or each of a plurality of digital streams in a digital data amount detecting step within one cycle of one transmission slot. When I did,
The slot allocation information generating step is characterized in that the slot allocation information is generated for the same number of transmission slots immediately after the transmission slot as detected at the digital stream amount detecting step.

Further, according to the invention of claim 122,
The digital multiplex transmission method according to any one of claims 112 to 121, wherein, in the slot assignment information generating step, for a transmission slot for transmitting slot assignment information among the transmission slots forming the multiplexed frame,
It is characterized in that the slot allocation information is not generated.

Further, according to the invention of claim 123,
In a digital multiplex transmission method in which a plurality of digital streams of a plurality of packet formats are multiplexed into respective transmission slots of a multiplexed frame and transmitted, each transmission slot of packets constituting each digital stream is determined according to the transmission rate of each digital stream. Slot allocation information generation process for generating allocation information for each digital stream
The input packet is transmitted in one transmission slot for each
Packet count detection to detect when the number of packets
The output process and the slot allocation information generation process.
The digital stream whose time point was detected in the
And a multiplexing step of multiplexing each digital stream according to the slot allocation information of the ream .

According to the invention of claim 124,
In a digital multiplex transmission method of multiplexing a plurality of digital streams of a packet format into respective transmission slots of a multiplexed frame and transmitting the same, a stuffing packet removing step of removing a stuffing packet included in each digital stream and a stuffing packet removing step are performed. According to the transmission rate of the packets of each digital stream after the stuffing packet is removed, a slot assignment information generating step of generating assignment information for each transmission slot of the packets included in each digital stream, and according to the generated slot assignment information. And a multiplexing step of multiplexing each digital stream.

According to the invention of claim 125,
The digital multiplex transmission method according to claim 123 or 124, wherein the slot allocation information generated in the slot allocation information generating step is added to a multiplexed frame in which each digital stream is multiplexed in the multiplexing step and transmitted. Characterize.

According to the invention of claim 126,
The digital multiplex transmission method according to claim 123 ,
In the slot allocation information generation process, the slot allocation information is
It is characterized in that it is generated based on the time of detection.

According to the invention of claim 127,
The digital multiplex transmission method according to claim 126 ,
In the slot allocation information generating step, the allocation information of the corresponding digital stream is generated for the transmission slot immediately after the transmission slot whose time point is detected in the packet number detecting step.

According to the invention of claim 128,
The digital multiplex transmission method according to any one of claims 123 to 127, wherein in the packet number detecting step, when the time points of a plurality of digital streams are detected within one cycle of the transmission slot, a slot allocation information generating step In, the slot allocation information is generated for the same number of transmission slots that are consecutive immediately after the transmission slot as detected at the packet number detecting step.

According to the invention of claim 129,
The digital multiplex transmission method according to any one of claims 123 to 128, wherein in the packet number detecting step, when no time point is detected for any digital stream within one cycle of the transmission slot, slot allocation information is generated. In the step, stuffing packet allocation information is generated for a transmission slot immediately after the transmission slot.

According to the invention of claim 130,
The digital multiplex transmission method according to claim 129 ,
In the packet number detection step, when no time point was detected for any digital stream within one cycle of the transmission slot, and within the one cycle of the multiplexing frame, no time point was detected during one cycle of the transmission slot. If the number of slot allocation information generated up to the number of transmission slots is less than the number of transmission slots transmitted within one cycle of the transmission slot whose time was not detected, immediately after the transmission slot in the slot allocation information generation step. It is characterized in that stuffing packet allocation information is generated for each transmission slot.

According to the invention of claim 131,
In a digital multiplex transmission method of multiplexing a plurality of digital streams in each transmission slot of a multiplexed frame by a transmission device and transmitting the multiplexed frame to a reception device, the transmission device, in accordance with the transmission rate of each digital stream, A slot allocation information generation step of generating allocation information for each transmission slot of digital data forming each digital stream, a multiplexing step of multiplexing each digital stream according to the generated slot allocation information , and an input for each digital stream Digital
The amount of data that can be transmitted in one transmission slot is reached
The digital data amount detection process to detect the
The slot allocation information generating step,
Digit whose time point was detected in the digital data amount detection process
And a sending step of sending the slot allocation information of the digital stream to the multiplexed frame in which each digital stream is multiplexed by the multiplexing step, and transmitting the slot. It is characterized in that a desired digital stream is extracted from the multiplexed frame and output based on the allocation information.

According to the invention of claim 132,
The digital multiplex transmission method according to claim 131 ,
The receiving device separates the slot allocation information from the multiplexed frame, and selects the transmission slot in which the digital data of the desired digital stream is multiplexed from the multiplexed frame based on the separated slot allocation information. , And outputting the selected digital data.

According to the invention of claim 133,
The digital multiplex transmission method according to claim 131 ,
In the slot allocation information generation process, the slot allocation information is
It is characterized in that it is generated based on the time of detection.

According to the invention of claim 134,
The digital multiplex transmission method according to claim 133 ,
In the slot allocation information generating step, the allocation information of the corresponding digital stream is generated for the transmission slot immediately after the transmission slot in which the time point was detected in the digital data amount detecting step.

According to the invention of claim 135,
The digital multiplex transmission method according to any one of claims 131 to 134, wherein in the digital data amount detecting step, when time points are detected for a plurality of digital streams within one cycle of the transmission slot, slot allocation information is generated. In the step, slot allocation information is generated for the same number of the transmission slots as the time points detected in the digital data amount detecting step, which are continuous immediately after the transmission slot.

In addition, according to the invention of claim 136,
The digital multiplex transmission method according to any one of claims 131 to 135, wherein in the digital data amount detecting step, when a time point is not detected for any digital stream within one cycle of the transmission slot, slot allocation information is obtained. In the generating step, the stuffing data allocation information is generated for the transmission slot immediately after the transmission slot.

According to the invention of claim 137,
The digital multiplex transmission method according to claim 136 ,
In the digital data amount detecting step, when the time point is not detected for any digital stream within one cycle of the transmission slot, and the time point is not detected within one cycle of the multiplexing frame, the transmission slot In the case where the number of slot allocation information generated within the period is less than the number of transmission slots transmitted within one period of the transmission slot in which the time point was not detected, the transmission slot It is characterized in that stuffing data allocation information is generated for the immediately following transmission slot.

According to the invention of claim 138,
The digital multiplex transmission method according to any one of claims 131 to 137, wherein the time is detected in the digital data amount detection step within one cycle of one transmission slot, and the time immediately follows the transmission slot. If the slot allocation information for the transmission slot has already been generated, in the slot allocation information generation step, the digital signal whose time point has been detected for the transmission slot immediately following the transmission slot for which the slot allocation information has not been generated. It is characterized in that the slot allocation information of the stream is generated.

According to the invention of claim 139,
The digital multiplex transmission method according to any one of claims 131 to 138 , when the slot assignment information generating step has already generated slot assignment information for each transmission slot for one cycle of one multiplexed frame. If, and within one cycle of the multiplexing frame, the digital data amount detecting step, and when the time point of the digital stream is detected, the slot allocation information generating step continues immediately after the multiplexing frame. It is characterized in that allocation information of a digital stream is generated for a transmission slot of a multiplexed frame.

According to the invention of claim 140,
The digital multiplex transmission method according to any one of claims 131 to 139 , wherein a time point is detected a plurality of times for one digital stream or each of a plurality of digital streams in a digital data amount detecting step within one cycle of one transmission slot. When I did,
The slot allocation information generating step is characterized in that the slot allocation information is generated for the same number of transmission slots immediately after the transmission slot as detected at the digital stream amount detecting step.

According to the invention of claim 141,
The digital multiplex transmission method according to any one of claims 131 to 140, wherein, in the slot assignment information generating step, for the transmission slot for transmitting the slot assignment information among the transmission slots forming the multiplexed frame,
It is characterized in that the slot allocation information is not generated.

[0205] According to the invention of claim 142,
In a digital multiplex transmission method in which a transmitter multiplexes a plurality of digital streams in a packet format into respective transmission slots of a multiplexed frame and transmits the multiplexed frame to a receiver, the transmitter transmits each digital stream. A slot allocation information generating step of generating allocation information for each transmission slot of a packet forming each digital stream according to a speed, a multiplexing step of multiplexing each digital stream according to the generated slot allocation information, and each digital stream Enter each
The number of packets that can be transmitted in one transmission slot
It has a packet number detection process to detect the arrival time,
Detection of the number of packets generated in the lot allocation information generation process
The slot allocation information of the digital stream whose time point is detected in the step, is added to the multiplexed frame in which each digital stream is multiplexed by the multiplexing step, and is transmitted. The receiving device is characterized in that it extracts a desired digital stream from the multiplexed frame and outputs it based on the slot allocation information added to the received multiplexed frame.

According to the invention of claim 143,
In a digital multiplex transmission method in which a transmitter multiplexes a plurality of digital streams in a packet format into respective transmission slots of a multiplexed frame and transmits the multiplexed frame to a receiver, the transmitter is included in each digital stream. Stuffing packet removal process to remove stuffing packets and generation of allocation information for each transmission slot of packets included in each digital stream according to the packet transmission rate of each digital stream from which stuffing packets have been removed by the stuffing packet removal process The slot allocation information generating step, the multiplexing step of multiplexing each digital stream according to the generated slot allocation information, and the slot allocation information generated in the slot allocation information generating step by the multiplexing step. And a transmitting step of transmitting each digital stream by adding it to the multiplexed frame, and the receiving device outputs the desired signal from the multiplexed frame based on the slot allocation information added to the received multiplexed frame. It is characterized in that a digital stream is taken out and outputted.

According to the invention of claim 144,
144. The digital multiplex transmission method according to claim 142 or 143, wherein the receiving device separates the slot allocation information from the multiplexed frame, and a desired digital stream from the multiplexed frame based on the separated slot allocation information. An output step of selecting a transmission slot in which packets are multiplexed and outputting the selected digital data.

According to the invention of claim 145,
145. The digital multiplex transmission method according to claim 144 ,
The receiving device is characterized by further including a step of multiplexing the stuffing packet with the output of the digital data from the output step based on the slot allocation information separated in the separating step.

According to the invention of claim 146,
The digital multiplex transmission method according to claim 142 ,
In the slot allocation information generation step, the slot allocation information is
It is characterized in that it is generated based on the time of detection.

According to the invention of claim 147,
The digital multiplex transmission method according to claim 146 ,
The slot allocation information generating step is characterized in that the allocation information of the corresponding digital stream is generated for the transmission slot immediately after the transmission slot whose time point was detected in the packet number detecting step.

According to the invention of claim 148,
The digital multiplex transmission method according to any one of claims 145 to 147, wherein when the packet number detecting step detects a time point for a plurality of digital streams within one cycle of a transmission slot, a slot allocation information generating step In the above, the slot allocation information is generated for the same number of transmission slots as that detected at the packet number detection step, which is continuous immediately after the transmission slot.

According to the invention of claim 149,
The digital multiplex transmission method according to any one of claims 145 to 148, wherein in the packet number detection step, when no time point is detected for any digital stream within one cycle of the transmission slot, slot allocation information is generated. In the step, stuffing packet allocation information is generated for a transmission slot immediately after the transmission slot.

According to the invention of claim 150,
The digital multiplex transmission method according to claim 149 ,
In the packet number detection step, when no time point was detected for any digital stream within one cycle of the transmission slot, and within the one cycle of the multiplexing frame, no time point was detected during one cycle of the transmission slot. If the number of slot allocation information generated up to the number of transmission slots is less than the number of transmission slots transmitted within one cycle of the transmission slot whose time was not detected, immediately after the transmission slot in the slot allocation information generation step. It is characterized in that stuffing packet allocation information is generated for each transmission slot.

Further, according to the invention of claim 151,
The digital multiplex transmission method according to any one of claims 145 to 150, wherein when a time point is detected in the packet number detection step within one cycle of one transmission slot, and the transmission immediately following the transmission slot is performed. If the slot allocation information for the slot has already been generated, in the slot allocation information generating step, the digital stream whose time point has been detected for the transmission slot immediately following the transmission slot for which the slot allocation information has not been generated. It is characterized in that the slot allocation information is generated.

According to the invention of claim 152,
The digital multiplex transmission method according to any one of claims 145 to 151, wherein when the slot assignment information generating step has already generated slot assignment information for each transmission slot for one cycle of one multiplexed frame. If the packet number is detected within the period of one multiplexed frame, and the time point is detected for the digital stream in the one cycle of the multiplexed frame, the slot allocation information generation step is performed to immediately after the multiplexed frame. It is characterized in that allocation information of a digital stream is generated for a transmission slot of a digitized frame.

According to the invention of claim 153,
The digital multiplex transmission method according to any one of claims 145 to 152 , wherein a time point is detected a plurality of times for one digital stream or each of a plurality of digital streams in a packet number detecting step within one cycle of one transmission slot. In this case, in the slot allocation information generating step, the slot allocation information is generated for the same number of transmission slots that immediately follow the transmission slots and the same number as the time point detected in the packet number detecting step. And

According to the invention of claim 154,
154. In the digital multiplex transmission method according to any one of claims 142 to 153, in the slot assignment information generating step, for the transmission slot for transmitting the slot assignment information among the transmission slots forming the multiplexed frame,
It is characterized in that the slot allocation information is not generated.

According to the invention of claim 155,
Based on the means for allocating the transmission slot of the packet according to the input time of the input packet, the means for multiplexing the packet in the transmission slot according to the allocation, and the transmission, and the multiplexing delay time of the packet including the system time information of the packet And a means for generating a correction amount of the system time information, and a means for correcting the system time information of the packet including the system time information by the correction amount.

According to the invention of claim 156,
The digital multiplex transmission apparatus according to claim 155 ,
The correction amount is assigned to the time from the input time of the packet containing the system time information to the end time of the transmission slot being sent at the input time, and the packet containing the system time information from the transmission slot immediately after the transmission slot. It is characterized in that it is generated based on the total time of the time to the transmission slot.

According to the invention of claim 157,
The digital multiplex transmission apparatus according to claim 155 ,
The correction amount includes a parameter indicating the time from the input time of the packet including the system time information to the end time of the transmission slot being sent at the input time, and the system time information from the transmission slot immediately after the transmission slot. It is generated based on a parameter representing the number of transmission slots up to the transmission slot assigned to the packet.

According to the invention of claim 158,
The digital multiplex transmission apparatus according to claim 155 ,
The correction amount is a parameter indicating the time from the input time of the packet containing the system time information to the end time of the transmission slot being sent at the input time, and the packet containing the time information from the transmission slot immediately after the transmission slot. It is generated based on a parameter indicating the number of transmission slots up to the transmission slot assigned to the parameter and a parameter indicating the multiplexing transmission rate.

According to the invention of claim 159,
A means for allocating the transmission slot of the packet according to the input time of the input packet, a means for multiplexing the packet in the transmission slot according to the allocation and transmitting the packet, and a parameter indicating the multiplexing delay time including the system time information of the packet. Generating means, means for storing parameters, means for reading the stored parameters at the time of multiplexing, means for generating a correction amount based on the read parameters, and correction of system time information with the correction amount. And means for doing so.

According to the invention of claim 160,
The digital multiplex transmission device according to claim 159 ,
The parameter indicates the time from the input time of the packet containing the system time information to the end time of the transmission slot being sent at the input time, and the packet containing the system time information from the transmission slot immediately after the transmission slot. And a parameter indicating the number of transmission slots up to the transmission slot assigned to the.

According to the invention of claim 161,
The digital multiplex transmission device according to claim 159 ,
The parameter includes a parameter indicating the time from the input time of the packet including the system time information to the end time of the transmission slot being transmitted at the input time, and the system time information from the transmission slot immediately after the transmission slot. It is characterized in that it is constituted by the number of transmission slots up to the transmission slot assigned to the packet and a parameter representing the multiplexing transmission rate.

According to the invention of claim 162,
The digital multiplex transmission device according to claim 159 ,
The means for generating the correction amount is configured by a read-only memory that inputs the parameter and outputs the correction amount.

According to the invention of claim 163,
In a digital multiplex transmission apparatus that selects a packet of a program to be multiplexed from at least one input digital stream, multiplexes the selected packet into a corresponding transmission slot, and outputs the multiplexed packet, depending on the packet input completion time, Digital multiplexing means for allocating a transmission slot to be multiplexed; when the packet is a packet containing system time information, when the input of the packet containing the system time information is completed, and in the packet containing the system time information in the packet multiplexing means A correction amount generation unit that generates a correction amount of delay jitter that occurs when a packet including system time information is multiplexed based on information indicating an assigned transmission slot, and a correction amount that is generated by the correction amount generation unit. Based on the And having a correction means for correcting the system time information of the packet including the system time information.

According to the invention of claim 164,
163. The digital multiplex transmission apparatus according to claim 163 ,
The correction amount is the first time from the completion of the input of the packet including the system time information to the end of the transmission of the transmission slot being transmitted from the digital multiplexing means at the completion of the input, and the transmission slot immediately after the transmission slot. The second time from the transmission start time to the transmission start time of the transmission slot assigned to the packet including the system time information is represented by the total time.

According to the invention of claim 165,
163 or 164. In the digital multiplex transmission apparatus according to claim 163 , the correction amount generating means is provided for at least one input digital stream, and a PCR for detecting the input completion time point of a packet including system time information and outputting a PCR detection signal. The packet input detection means, the PCR detection signal output from the PCR packet input detection means, which is provided for each PCR packet detection means, and the transmission slot being transmitted at the time of input of the packet including the system time information, For inputting the information indicating the transmission slot allocated to the packet including the system time information from the digital multiplexing means, and determining the first time and the second time for the packet including the system time information. Correction parameter generating means for generating various parameters of From the digital multiplexing means, the selection means for inputting and outputting the various parameters generated by the positive parameter generation means from the correction parameter generation means corresponding to the PCR packet input detection means that has detected the packet containing the system time information It is input from the selection means according to the information indicating the transmission slot that was being transmitted at the time of inputting the packet including the input system time information and the information indicating the transmission slot assigned to the packet including the system time information. It is characterized by including a parameter storage unit for writing and reading various parameters and a correction amount output unit for outputting the correction amount corresponding to the various parameters read from the parameter storage unit to the correction unit. And

According to the invention of claim 166,
The digital multiplex transmission apparatus according to any one of claims 163 to 165 , wherein the operation speed of slot allocation in the digital multiplexing means and the operation speed of generation of the correction amount in the correction amount generating means are the multiplexing output speed in the digital multiplexing means. 1 / of the slot clock signal that defines
It is characterized in that it is defined with a cycle of k (k is an integer) and using a 1 / k slot clock signal synchronized with the slot clock signal.

According to the invention of claim 167,
The digital multiplex transmission apparatus according to any one of claims 163 to 165 , wherein the operation speed of slot allocation in the digital multiplexing means and the operation speed of generation of the correction amount in the correction amount generating means are the multiplexing output speed in the digital multiplexing means. 1 / of the slot clock signal that defines
It is characterized in that it is defined by using a half slot clock signal having a period of 2 and synchronized with the slot clock signal.

According to the invention of claim 168,
The digital multiplex transmission apparatus according to claim 166 ,
The various parameters are the first parameter indicating the number of cycles of the system clock from the completion of the input of the packet including the system time information to the next rise of the 1 / k slot clock signal, and the 1 / k slot clock at the completion of the input. And a second parameter indicating the pulse position of the signal, and the correction amount output means outputs an amount representing the first time corresponding to the first parameter and the second parameter.

According to the invention of claim 169,
167. The digital multiplex transmission device according to claim 167 ,
The various parameters are the first parameter indicating the number of cycles of the system clock from the completion of input of the packet including the system time information to the next rising edge of the half slot clock signal, and the logic level of the half slot clock signal at the completion of the input. And a second parameter indicating that the correction amount output means outputs a quantity representing a first time corresponding to the first parameter and the second parameter.

According to the invention of claim 170,
The digital multiplex transmission apparatus according to any one of claims 166 to 169, wherein the various parameters are set from the transmission slot immediately after the transmission slot being transmitted from the digital multiplexing means at the time of completion of input of the packet including system time information, to the system. A third number indicating the number of transmission slots up to the transmission slot assigned to the packet including time information
And a second amount of time corresponding to the third parameter is output from the correction amount output means.

According to the invention of claim 171,
The digital multiplex transmission apparatus according to claim 170 ,
The correction parameter generating means outputs a correction valid signal relating to the timing at which the packet including the system time information is multiplexed in the transmission slot by the digital multiplexing means, and when the correction valid signal indicates the valid period, the selecting means. Outputs the first parameter, the second parameter, and the third parameter input from the correction parameter generation means to the parameter storage means.

According to the invention of claim 172,
The digital multiplex transmission apparatus according to any one of claims 163 to 171, wherein the correction means arithmetically adds a correction amount to the system time information of the packet including the system time information multiplexed and output from the digital multiplexing means. It is characterized by outputting as.

According to the invention of claim 173,
The digital multiplex transmission device according to any one of claims 170 to 172, wherein the correction amount output means is composed of a read-only memory that stores the correction amount for each address,
When the first parameter, the second parameter, and the third parameter are address-input, a correction amount corresponding to the first parameter, the second parameter, and the third parameter is output. To do.

According to the invention of claim 174,
The digital multiplex transmission apparatus according to any one of claims 170 to 173, wherein when a plurality of output rates are used as the multiplexing output rate in the digital multiplexing means, the first parameter, the second parameter, and the third parameter are used. An address in which a value indicating the multiplexed output speed is further attached to a bit different from the parameter is input to the correction amount output means,
The correction amount output means is characterized in that it outputs a correction amount according to the multiplexed output speed based on the input of an address to which a value indicating the multiplexed output speed is further added.

According to the invention of claim 175,
The digital multiplex transmission apparatus according to any one of claims 163 to 174, wherein the digital multiplexing means is provided for at least one input digital stream,
PID filter / conversion means for selectively passing only the packets of the program to be multiplexed from the input digital stream, and each PID filter / conversion means are provided.
A buffer memory for temporarily storing the packet that has passed through the PID filter / conversion means, a stuffing packet memory for storing null packets, and a PID filter / conversion means are provided for each PID filter / conversion means. Packet input detection means for detecting the time when the packet is completely input to the buffer memory and outputting an input detection signal, and for the packets input to the buffer memory based on the input detection signals output from the respective packet input detection means. Slot allocation information indicating allocation of transmission slots to be multiplexed is generated from the buffer memory based on the slot allocation information generating means for generating in one multiplexing group transmission time unit and the slot allocation information generated by the slot allocation information generating means. Read packet or stuffing packet memo It reads the null packets from, characterized in that it is configured to include a transmission slot multiplexing means for assigning transmission slots for multiplexing on packets or null packets.

According to the invention of claim 176,
The digital multiplex transmission apparatus according to claim 175 ,
The slot allocation information generating means is provided for each packet input detecting means, and includes an input detection signal from the packet input detecting means and a 1 / k slot clock signal as inputs,
A retiming means for converting the input detection signal into a signal having a pulse width of 1 cycle time of the 1 / k slot clock signal and outputting the 1 / k slot clock signal and the slot clock signal, and inputting the 1 / k slot clock signal Of 1
The first pulse signal, which has the same number of pulse generation positions as the retiming means in each cycle, and the pulse signal, which differs in each cycle of the slot clock signal, have different pulse generation positions than the first pulse signal. A pulse generating means for generating a rearward second pulse signal and each retiming means are provided, and the output of the retiming means and the output of the pulse generating means are input, and the pulse signal is input from the retiming means. A first AND gate that controls passage of the first pulse signal and an output of each first AND gate are included as inputs, and for each input of the first pulse signal from each first AND gate. A stream number encoder for generating information indicating a corresponding digital stream, an OR gate including as inputs the output of each first AND gate, and a slot The slot number counter that outputs the slot counter value that counts the pulse of the lock signal for each transmission time of one multiplexing group and outputs the carry signal each time the slot counter value returns from the maximum value to the initial value, and the slot number counter The slot number counter is composed of a counter with a large number of digits, and advances the write address value by 1 every time the first pulse signal is input through the OR gate and uses the write address value as a write address signal. A write address counter that outputs in the same format as
The slot counter value is compared with the lower digit of the write address value having the same digit as the slot counter value, and if the result of the comparison is that the lower digit of the write address value is smaller than the slot counter value, the true value 1 A second logical product for controlling the passage of the second pulse signal by inputting the true value 1 from the magnitude comparing means, and the magnitude comparing means for outputting And a pulse signal that has passed through the second AND gate and is supplied to the stream number encoder and the logical sum gate, and the second pulse signal is supplied to the stream number encoder. When the second pulse signal is applied to the logical sum gate, the second pulse signal is applied to the write address counter through the logical product gate. The write address counter counts the write address value by one, and the slot allocation information generating means further writes the information indicating the digital stream output from the stream number encoder or the information indicating the stuffing. It has a storage means to be written at the address indicated by the address signal, and a conversion means for performing a predetermined conversion on the carry signal output from the slot number counter, and reading out the signal output from the conversion means and the slot counter value. The address is input to the storage means, and the information indicating the digital stream or the information indicating the stuffing stored before the transmission time of one multiplexing group is read from the storage means.

According to the invention of claim 177,
The digital multiplex transmission apparatus according to claim 176 ,
The retiming means receives the 1 / k slot clock signal, the logic level 0 signal, and the input detection signal as input, presets the output value to 1 each time the input detection signal is input, and then outputs the 1 / k slot clock signal thereafter. The first flip-flop which reads in the logic level 0 signal and outputs it as the output value 0 by the rising input of the first flip-flop, and the output of the first flip-flop and the 1 / k slot clock signal are input, and the 1 / k slot clock is input. It is characterized by including a second flip-flop which reads the output value 1 from the first flip-flop by the input of the rising edge of the signal and outputs it as the output value 1 to the selecting means.

According to the invention of claim 178,
The digital multiplex transmission device according to claim 176 or 177, wherein the correction parameter generation means receives the PCR detection signal and a system clock of a predetermined frequency as input, and a PC
Each time the R detection signal is input, the count value is temporarily cleared to zero, and the first counter that counts the system clock and outputs the count value, the output of the first counter, and the 1 / k slot clock signal are The input of the rising edge of the 1 / k slot clock signal holds the output of the first counter and outputs the held signal to the selecting means as the first parameter, and 1 of the slot clock signal. 0 to k-1 at a timing synchronized with the 1 / k slot clock signal every cycle
A second counter that counts up to, a count value of the second counter, and a PCR detection signal as input,
Each time the R detection signal is input, the count value in the second counter is held, and the second register that outputs the held count value, the output of the second register, and the 1 / k slot clock signal are input. , A third register for holding the output of the second register by the rising input of the 1 / k slot clock signal and outputting the held signal to the selecting means as the second parameter signal, and the output of the slot number counter. A PCR detection signal is input, and a slot counter value at the time of input is held each time the PCR detection signal is input, and a fourth register that outputs the held signal and an output of the fourth register and 1 / k
The slot clock signal is input, and the output of the fourth register is held by the rising input of the 1 / k slot clock signal, and the fifth register that outputs the held signal and the output of the fifth register and the lower order The write address value of the digit is input, the write address value of the lower digit is subtracted from the output value of the fifth register, and the value obtained by subtracting 1 from the value is output to the selecting means as the third parameter signal. Subtractor, 1 / k slot clock signal, logic level 0
The signal and the PCR detection signal are input, and the output value is preset to 1 each time the PCR detection signal is input, and then 1
By inputting the rising edge of the / k slot clock signal,
A third flip-flop that reads the ethics level 0 signal and outputs it as an output value 0, and the output of the third flip-flop and the 1 / k slot clock signal are input,
It is characterized in that it has a fourth flip-flop for reading the output value 1 from the third flip-flop by the rising input of the 1 / k slot clock signal and outputting it as a correction valid signal to the selecting means.

According to the invention of claim 179,
The digital multiplex transmission apparatus according to claim 175 ,
The slot allocation information generating means is provided for each packet input detecting means, and includes as input the input detection signal and the half slot clock signal from the packet input detecting means,
A retiming means for converting the input detection signal into a signal having a pulse width of one cycle time of the half slot clock signal and outputting the same, and a half slot clock signal and a slot clock signal are input, and for each cycle of the half slot clock signal. The first pulse signal having the same number of pulse generation positions as that of the retiming means and the pulse generation position differ from the pulse signal for each cycle of the slot clock signal, and the pulse generation position is located behind the first pulse signal. A pulse generating means for generating two pulse signals, and each retiming means, which receives the output of the retiming means and the output of the pulse generating means and receives the pulse signal from the retiming means. The first AND gate that controls the passage of the pulse signal of And a stream number encoder for generating information indicating a digital stream corresponding to each input of the first pulse signal from each first AND gate, and a logic including the output of each first AND gate as an input. A sum gate and a slot number counter that outputs a slot counter value that counts the pulses of the slot clock signal for each transmission time of one multiplexing group, and outputs a carry signal each time the slot counter value returns from the maximum value to the initial value. , A counter having a larger number of digits than the slot number counter, and advances the write address value by one every time the first pulse signal is input through the OR gate and outputs the write address value as the write address signal. And a write address counter that outputs in the same format as the slot number counter,
The slot counter value is compared with the lower digit of the write address value having the same digit as the slot counter value, and if the result of the comparison is that the lower digit of the write address value is smaller than the slot counter value, the true value 1 A second logical product for controlling the passage of the second pulse signal by inputting the true value 1 from the magnitude comparing means, and the magnitude comparing means for outputting And a pulse signal that has passed through the second AND gate and is supplied to the stream number encoder and the logical sum gate, and the second pulse signal is supplied to the stream number encoder. When the second pulse signal is applied to the AND gate, the second pulse signal is applied to the write address counter through the OR gate. The write address counter counts the write address value by one, and the slot allocation information generating means further writes the information indicating the digital stream output from the stream number encoder or the information indicating the stuffing. It has a storage means to be written at the address indicated by the address signal, and a conversion means for performing a predetermined conversion on the carry signal output from the slot number counter, and reading out the signal output from the conversion means and the slot counter value. The address is input to the storage means, and the information indicating the digital stream or the information indicating the stuffing stored before the transmission time of one multiplexing group is read from the storage means.

According to the invention of claim 180,
The digital multiplex transmission apparatus according to claim 176 ,
The retiming means receives the half-slot clock signal, the logic level 0 signal, and the input detection signal as input, presets the output value to 1 each time the input detection signal is input, and inputs the rising edge of the half-slot clock signal thereafter. The first flip-flop that reads the logic level 0 signal and outputs it as the output value 0, and the output of the first flip-flop and the half slot clock signal are input, and by the rising input of the half slot clock signal, And a second flip-flop for reading the output value 1 from one flip-flop and outputting it to the selecting means as the output value 1.

Further, according to the invention of claim 181,
The digital multiplex transmission device according to claim 176 or 177, wherein the correction parameter generation means receives the PCR detection signal and a system clock of a predetermined frequency as input, and a PC
A counter that clears the count value to zero each time the R detection signal is input, counts the system clock and outputs the count value, and the counter output and the half-slot clock signal are input, and the half-slot clock signal rises. The input of the counter holds the output of the counter, and the first register that outputs the held signal as the first parameter to the selection unit, the PCR detection signal, and the slot clock signal are input, and each time the PCR detection signal is input. The second register that holds the logic level of the slot clock signal at the time of input and outputs the held logic level, and the output of the second register and the half slot clock signal are input, and the half slot clock signal rises. Hold the output of the second register by inputting A third register for outputting the held signal to the selection means as a second parameter signal, an output and a PCR detection signal of the slot number counter as input,
Each time the PCR detection signal is input, the slot counter value at the time of input is held, and the fourth register that outputs the held signal and the output of the fourth register and the half slot clock signal are input, and the half slot clock is input. The fifth register that holds the output of the fourth register by the input of the rising edge of the signal and outputs the held signal, and the output of the fifth register and the write address value of the lower digit are input to the fifth register. , A subtracter for subtracting the write address value of the lower digit from the output value of the register, and outputting the value obtained by subtracting 1 from the value to the selecting means as a third parameter signal, a half slot clock signal, and a logic level 0 signal. , And the PCR detection signal are input, and the output value is preset to 1 each time the PCR detection signal is input, and the half slot clock after that. At the rising edge of the signal, a third flip-flop that reads the ethics level 0 signal and outputs it as an output value 0, and the output of the third flip-flop and the half slot clock signal are input, and the rising edge of the half slot clock signal is input. It is characterized in that it has a fourth flip-flop for reading the output value 1 from the third flip-flop by the input of and also outputting it as a correction valid signal to the selecting means.

According to the invention of claim 182,
The digital multiplex transmission device according to any one of claims 176 to 181 , wherein the first pulse signal passing through each of the first AND gates is given to the selecting means, and the selecting means corresponds to the first pulse signal. The first parameter, the second parameter, the third parameter, and the correction valid signal are input from the correction parameter generating means.

According to the invention of claim 183,
The digital multiplex transmission apparatus according to any one of claims 176 to 182, wherein the slot counter value and the write address value are given to the parameter storage means, and the parameter storage means writes and reads to the same address as the storage means. It is characterized by performing.

[0247]

BEST MODE FOR CARRYING OUT THE INVENTION To clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a system configuration example of a digital multiplex transmission system using the digital multiplex transmission device according to the first embodiment of the present invention as a transmitter.

Specifically, a system configuration example of a digital multiplex transmission system constituted by the digital multiplex transmission device 20 and the receiving device 40 in this embodiment is shown.
The case where three digital streams of digital stream A, digital stream B, and digital stream C are multiplexed is shown.

In the digital multiplex transmission device 20, these digital streams are respectively stored in the buffer memory 2
1a, the buffer memory 21b, and the buffer memory 21c, and the buffer memory 21a accumulates the digital data of the digital stream A,
b stores the digital data of the digital stream B, and the buffer memory 21c stores the digital data of the digital stream C. The stuffing data memory 22 stores stuffing data in advance.

The transmission slot allocation circuit 23 has a buffer memory 21a, a buffer memory 21b, and a buffer memory 21 according to the slot allocation information output from the slot allocation information generation circuit 50 provided according to the present invention.
c or data stored in the stuffing data memory 22 is read out, multiplexed in each transmission slot, and output to the multiplexed frame generation circuit 24. The transmission slot allocation circuit 23 can be easily constructed by those skilled in the art, and a detailed configuration thereof will be omitted.

The multiplexed frame generation circuit 24 multiplexes the slot allocation information output from the slot allocation information generation circuit 50 into a specific transmission slot, and transmits each transmission slot output from the transmission slot allocation circuit 23. Together, they form one multiplexed frame and output it to the transmission line 30. Also, the multiplexed frame generation circuit 24 repeatedly generates and outputs the multiplexed frame. This multiplexed frame generation circuit can be easily constructed by those skilled in the art, and detailed configuration thereof will be omitted.

FIG. 2 shows an example of the structure of the multiplexed frame. Referring to FIG. 2, one multiplexed frame is composed of n transmission slots, and the 0th transmission slot at the beginning of the multiplexed frame is a multiplexed information slot in which a frame synchronization signal and slot allocation information are multiplexed. The MIS is arranged, and the slot allocation information is multiplexed in the slot allocation information field in the 0th transmission slot.

Digital data of digital stream A, digital data of digital stream B, digital data of digital stream C, or stuffing data are multiplexed in the first to n-1th transmission slots. Which data is multiplexed in each slot is identified by the slot allocation information multiplexed in the 0th transmission slot.

FIG. 3 shows an example of the structure of the slot allocation information field. Referring to FIG. 3, the slot allocation information field is composed of n-1 pieces of slot allocation information, and the allocation order of each slot allocation information is the arrangement of the first to n-1th transmission slots in the multiplexed frame. It corresponds in order.

That is, in the first slot allocation information in the slot allocation information field, the data multiplexed in the first transmission slot is digital data of digital stream A, digital data of digital stream B, and digital stream C. Of digital data or stuffing data, and the second slot allocation information is information indicating allocation of data multiplexed in the second transmission slot.

In FIG. 1, the data amount detecting circuit 25a and the data amount detecting circuit 25 are in accordance with the present invention.
b, a data amount detection circuit 25c is provided. The data amount detection circuit 25a measures the digital data amount from the digital stream A input to the buffer memory 21a, and the data amount detection circuit 25b measures the digital data amount from the digital stream B input to the buffer memory 21b. The detection circuit 25c measures the amount of data from the digital stream C input to the buffer memory 21c, and is provided according to the present invention each time the detected amount of data reaches the amount of data transmitted in one transmission slot. A detection signal is issued to the slot allocation information generation circuit 50, and the data amount detection circuit that issued the detection signal newly starts measurement of the data amount at that point. The data amount described below refers to the number of bits or packets input from each digital stream.

When the detection signal is generated, the slot allocation information generation circuit 50 stores and holds information indicating the digital stream measured by the data amount detection circuit which generated this detection signal as the slot allocation information, and eventually If no detection signal is generated from the data amount detection circuit of, if the number of slots allocated up to that time is less than the number of slots transmitted up to that time, information indicating stuffing is used as slot allocation information. Retain. In addition, the slot allocation information generation circuit 50 transmits the slot allocation information for one multiplexed frame stored and held during the output time of the previous multiplexed frame each time the multiplexed frame is repeatedly generated and output. It outputs to the allocation circuit 23 and the multiplexed frame generation circuit 24.

The transmission slot allocation circuit 23 reads the digital data of the digital stream allocated to each transmission slot from the buffer memory in accordance with the slot allocation information, and sequentially multiplexes it into the first to (n-1) th transmission slots, and multiplexes them. It is output to the frame generation circuit 24. At this time, the multiplexed frame generation circuit 24 multiplexes the slot allocation information for one multiplexed frame into the 0th transmission slot, and n transmissions including the respective transmission slots output from the transmission slot allocation circuit 23. A multiplexed frame composed of slots is constructed and a stream is output to the transmission path 30.

Therefore, the number of transmission slots in the multiplexed frame is automatically assigned according to the digital information rate of each digital stream. The position of the transmission slot assigned to each digital stream is 1
The operation that the amount of data transmitted in each transmission slot corresponds to each input time is obtained, and the object of the present invention is achieved.

In the receiving device 40, the stream input from the transmission path 30 is received, the frame synchronizing circuit 41 detects the frame synchronizing signal inserted in the multiplexed frame, and the synchronization with the multiplexed frame is established.
The timing signal indicating the position of the transmission slot in which the slot allocation information is multiplexed in the multiplexed frame is output to the slot allocation information separation circuit 43. This frame synchronization circuit can be easily constructed by those skilled in the art, and a detailed configuration thereof will be omitted.

The slot allocation information separating circuit 43 separates the slot allocation information from the transmission slot in which the slot allocation information is multiplexed by the timing signal. The transmission slot selection circuit 42 uses the slot allocation information separation circuit 4
According to the slot allocation information separated in 3, the transmission slot allocated to each digital stream is selected, and the multiplexed data is extracted from the transmission slot and output.

Therefore, the receiving apparatus 40 can obtain the operation of extracting the digital data of each digital stream separately from the multiplexed frame, and the object of the present invention can be achieved.

FIG. 4 shows an embodiment of the present invention.
Slot allocation information generation circuit 5 of digital multiplex transmission device
0 block diagram is shown. Hereinafter, the configuration and operation of the slot allocation information generating circuit 50 of FIG. 4 will be described in detail.

In FIG. 4, the retiming circuit 51a,
The retiming circuit 51b and the retiming circuit 51c have detection signals D1 from the respective data amount measuring circuits,
D2 and D3 are input. Retiming circuit 51a, 5
1b and 51c retiming each detection signal with a slot clock signal, and AND gates 53a, 53b and 53c.
Output to one of the input terminals.

The pulse generation circuit 52 uses the slot clock signal to generate five pulse signals φ0, φ having different phases.
1, φ2, φ3, φ4 are generated, the pulse signal φ1 is output to the other input terminal of the AND gate 53a, and the pulse signal φ2 is output to the other input terminal of the AND gate 53b.
The pulse signal φ3 is applied to the other input terminal of the AND gate 53c.
To output the pulse signal φ4 to one input terminal of the AND gate 53d and to output the pulse signal φ0 to one input terminal of the AND gate 58d.

AND gates 53a, 53b, 53c, 5
The output of 3d is connected to the stream number encoder 54 and the OR gate 55. The stream number encoder 54 generates information for identifying the stream according to the input, and outputs the information for identifying the stream to the data input terminal Din of the memory 60. The logical sum gate 55 outputs the logical sum of the outputs of the logical product gates 53a, 53b, 53c, and 53d to one input terminal of the logical sum gate 56 and the write enable terminal WE of the memory 60. The OR gate 56 outputs the output of the OR gate 55 and the AND gate 5
The output of 8 is logically ORed and output to the write address counter 57.

The write address counter 57 is composed of a 5-bit binary counter, counts the output of the OR gate 56, and outputs the most significant bit b4 of the count value.
(MSB) is output to the write address terminal WAH of the memory 60 and the data input terminal D of the flip-flop 61,
The lower bits b3 to b0 of the count value are output to the write address terminal WAL of the memory 60, the other input terminal of the AND gate 58, and one input terminal X of the magnitude comparison circuit 59.

The AND gate 58 outputs the pulse signal φ0 and the lower bit b3 of the count value of the write address counter 57.
~ B0 is output to the other input terminal of the OR gate 56. The slot number counter 64 is composed of a 4-bit binary counter that is 1 bit smaller than the write address counter 57, counts the slot clock signal, and outputs the count values b3 to b0 to the read address terminal RAL of the memory 60 and the size. The carry signal CR is output to the other input terminal Y of the comparison circuit 59 and also to the input terminal of the logic inverting gate 63.

The magnitude comparison circuit 59 determines the lower 4 of the count value of the write address counter 57 input to the input terminal X.
The value of the bit is compared with the value of the 4-bit count value of the slot number counter 64 input to the input terminal Y, and the value input to X is less than the value input to Y (for example, X = Y-1), the true value '1' is output, and X
When the value input to Y is equal to or more than the value input to Y, a false value "0" is output and applied to the other input terminal of the AND gate 53d.

The logical inversion gate 63 logically inverts the input and supplies it to the clock terminal CLK of the flip-flop 61. The flip-flop 61 reads a data input with a clock and holds it, and outputs it to the input terminal of the logic inverting gate 62. The logic inversion gate 62 logically inverts the input and outputs it to the read address terminal RAH of the memory 60.

The memory 60 writes and holds the output of the stream number encoder 54 at the address indicated by the count value of the write address counter 57, and indicates the output of the logical inversion gate 62 and the count value of the slot number counter 64. The data stored and held at the stored address is read and output as slot allocation information.

The operation of slot allocation information generating circuit 50 shown in FIG. 4 will be described in detail below.

The number of bits of the slot number counter 64 in the slot allocation information generating circuit 50 of FIG. 4 is set in correspondence with the number of transmission slots forming a multiplexed frame. For example, the number of bits 4 is one multiplexing. This corresponds to the case where a frame is composed of 2 4 powers, that is, 16 transmission slots.

The number of transmission slots constituting the multiplexed frame is not limited to the nth power of 2 (n is a positive integer), and may be any m (m is a positive integer). In that case, the slot number counter 64 It is a m-adic counter that counts modulo m and outputs the count value in a binary format. On the other hand, the write address counter 57 is an m-adic counter that is one digit more than the slot number counter 64. Yes,
A counter that counts modulo m and outputs the count value in a binary number format, outputs the upper digit in 1 bit, and the AND gate 58 indicates that the value indicated by the lower bit of the write address counter 57 is m-. When it is 1, it can be realized by changing the circuit to pass the pulse signal φ0.

Here, outputting a value obtained by counting m modulo means outputting the remainder obtained by dividing a numerical value by m, and this arithmetic method is known as modulo arithmetic.

FIG. 5 is a timing diagram showing the operation of the pulse generator 52. The pulse generator 52 has five pulse signals φ0, φ1, φ2, φ3 with different pulse positions for each cycle of the slot clock signal. , Φ4 are generated and output. The pulse signals .phi.1, .phi.2 and .phi.3 are retiming circuit 5 in AND gates 53a, 53b and 53c, respectively.
Outputs from 1a, 51b and 51c are controlled so that passage is permitted, and AND gates 53a, 53b and 5
The pulse signals φ1, φ2, and φ3 that have passed 3c are given to the stream number encoder 54 and the logical sum gate 55. One cycle time of the slot clock signal shown in FIG. 5 is equal to the transmission time of one transmission slot forming the multiplexed frame.

FIG. 6 shows the retiming circuits 51a and 51a.
It is a figure which shows one structural example of b and 51c, and one circuit is shown. FIG. 7 shows retiming circuits 51a, 51b,
It is a timing diagram which shows operation | movement of 51c.

Data amount measuring circuits 25a, 25b, 25c
The detection signal output from is in the pulse signal format, and a detection signal in the pulse signal format is generated and input to the retiming circuit each time a fixed amount of data arrives from the digital stream. The flip-flop F1 is preset by this detection signal, and the output of the flip-flop F1 becomes "1". The output of the flip-flop F1 is read into the flip-flop F2 by the slot clock signal, and the output of the flip-flop F2 becomes "1". At the same time, the flip-flop F1 reads "0" and the output of the flip-flop F1 becomes "0". If the flip-flop F1 is not newly preset by the detection signal, the flip-flop F2 outputs "0" in the next cycle of the slot clock signal.
Is read, the output becomes "0".

In this way, one pulse generated in the detection signal is converted by the retiming circuit into the time of one cycle of the slot clock signal, that is, the transmission time of one transmission slot, and is output.

Therefore, every time the detection signal is generated, the AND gates 53a, 53b and 53c are opened for the time of one cycle of the slot clock signal immediately after that, and the pulse signal from the pulse generator 52 is output from the stream number encoder 54.
At the same time, the pulse signal from the pulse generating circuit 52 is also applied to the write address counter 57 through the OR gate 55 and the OR gate 56.

At this time, the write address counter 57
The pulse signal from the pulse generating circuit 52 given through the OR gate 56 is counted, the count value is increased, and a new write address value is output to the memory 60. Further, the pulse signal passing through the OR gate 55 is also given to the write enable terminal WE of the memory 60 at the same time.

At this time, the stream number encoder 54
Since a pulse signal is given from the AND gates 53a, 53b, 53c corresponding to the digital stream in which the detection signal has been generated, the stream number encoder 54 generates information (number) indicating the corresponding digital stream, and the memory 60 To the data input terminal Din. Therefore, every time a detection signal is generated, a number indicating the corresponding digital stream is sequentially written and stored in the memory 60.

On the other hand, when the detection signal is not generated, the number indicating the corresponding digital stream is not written in the memory 60, and the count value of the write address counter 57 is updated by any one of the pulse signals φ1, φ2, and φ3. Is not done.

Here, the slot number counter 64 is
It is a 4-bit binary counter that increments the count value every cycle of the slot clock signal, and the count value corresponds to the slot number of each slot forming the multiplexed frame. Here, the slot numbers are named for convenience of description of the operation, such as 0, 1, 2 in the transmission order from the first transmission slot in the multiplexed frame.

The magnitude comparison circuit 59 compares the 4-bit output value of the slot number counter 64 with the lower 4-bit output value of the write address counter 57, and when the write address counter side is smaller, the true value '. 1'is output to one input terminal of the AND gate 53d. At this time, the gate of the logical product gate 53d is opened and the pulse signal φ4 from the pulse generator 52 is given to the stream number encoder 54, and at the same time, the write signal counter 57 is passed through the logical sum gate 55 and the logical sum gate 56. Is also given,
It is also given to the write enable terminal WE of the memory 60 through the OR gate 55.

Also, the stream number encoder 54 is
When receiving the pulse signal φ4 from the AND gate 53d, a number indicating stuffing is generated and output to the data input terminal Din of the memory 60.

Therefore, in the slot allocation information generating circuit 50 shown in FIG. 4, when the step of the count value of the write address counter 57 due to the generation of the detection signal is less than the step of the count value of the slot number counter 64, it is automatically performed. Specifically, the count value of the write address counter 57 follows the count value of the slot number counter 64, and the number indicating the stuffing is written and stored in the memory 60.

As shown in FIG. 2, each digital stream is multiplexed in the transmission slots after the first transmission slot and not in the 0th transmission slot. In FIG. 4, when the lower bits b3 to b0 of the counter value of the write address counter 57 become the maximum value '1111', that is, the slot number of the last transmission slot in the multiplexed frame, the AND gate 58 outputs the pulse signal φ0. Has passed,
It is given to the write address counter 57 through the OR gate 56.

Therefore, the write address counter 57 advances the count value by one, and the lower bits b3 to b3 of the count value.
b0 returns to "0000", that is, a value equal to the slot number of the leading transmission slot in the multiplexed frame, and carry is carried out, and the most significant bit b4 of the count value is reached.
The logical value of (MSB) is inverted. At this time, since the pulse signal φ0 is not given to the write enable terminal WE of the write address counter 57, writing to the memory 60 is not performed.

Therefore, the stream number encoder 5
The range of the lower 4 bit value of the address value of the memory 60 to which the 4 output is written is equal to the range of the transmission slot in which the digital data or the stuffing data is multiplexed, and the lower 4 bit value is equal to the slot number.

As described above, in the slot allocation information generating circuit 50 shown in FIG. 4, when the detection signal is generated, the address of the memory 60 equal to the slot number of the transmission slot transmitted immediately after the detection signal is generated, An operation is performed in which the number indicating the digital stream in which the detection signal is generated is stored and held.

When a plurality of detection signals are generated during the transmission time of one transmission slot, pulse signals φ1 and φ
By arranging the pulse positions of 2 and φ3 at different positions in one cycle of the slot clock signal, writing the numbers of the respective digital streams to the memory 60 updates the write address while updating the write address. Each digital stream in which these detection signals are generated is sent to the address corresponding to the slot number of the transmission slot that is transmitted immediately after the detection signal is generated and the slot number of the transmission slot that is immediately after that in the same cycle. The operation of storing and holding the indicated numbers is performed.

When no detection signal is generated, an operation is performed in which a number indicating stuffing is stored and held at an address equal to the slot number of the transmission slot transmitted immediately after that.

The reading of the stored and held number from the memory 60 is given to the memory 60 by continuously adding a read enable signal to the memory 60 (the description of this signal is omitted in FIG. 4). According to the read address thus obtained, the data is continuously output from the data output terminal Dout. A 4-bit count value of the slot number counter 64 is given to the read address terminal RAL, and a value obtained by logically inverting the output of the flip-flop 61 is given to the read address terminal RAH.

In the memory 60, the read address terminal RAL and the write address terminal WAL have the same digit, and the read address terminal RAH and the write address terminal WAH have the same digit. The carry signal CR of the slot number counter 64 is logically inverted by the logical inversion gate 63 and applied to the clock terminal of the flip-flop 61. Therefore, each time the count value of the slot number counter 64 returns from the maximum value (F in hexadecimal number) to the initial value (0),
The value of the most significant bit b4 of the write address counter at that time is read and held by the flip-flop 61, and its logical inversion value is read address terminal RAH.
Given to.

Therefore, the read address terminal RAH
In the memory 6 during transmission of the previous multiplexed frame.
The value assigned to the write address terminal WAH when the slot allocation information for one multiplexed frame which has been stored and held in 0 is written in the memory 60 is given.

Therefore, from the memory 60, the number indicating the digital stream or the number indicating the stuffing written during the transmission of the previous multiplexed frame is read one by one for each cycle of the slot clock signal, and one is multiplexed. The same number as the number of transmission slots that make up a frame is 1
It is read out every multiplexed frame time and output as slot allocation information.

Therefore, the slot allocation information generating circuit of FIG. 4 automatically creates slot allocation information for allocating multiplexing of digital data of multiple digital streams or multiplexing of stuffing data to transmission slots. Operation is achieved and the object of the invention is achieved.

Further, since the transmission slots are assigned according to the input speed of the digital data from the digital stream, the number of transmission slots is automatically assigned to each digital stream, and the operation of increasing the multiplexing efficiency can be obtained. The object of the present invention is achieved.

Since this slot allocation information is generated according to the time when a fixed amount of digital data is input and the transmission slot is allocated, there is little delay time jitter when multiplexing a plurality of packet format digital streams. The operation that multiplexing is performed is obtained and the object of the invention is achieved.

The number of bits of the write address counter 57 is one bit larger than that of the slot number counter 64, and the count range is twice that of the slot number counter 64. Therefore, even if the input speed of digital data from the digital stream fluctuates and the total amount of digital data input in one multiplexing frame time temporarily exceeds the total amount of data that can be transmitted in one multiplexing frame, the slot Assignment information is created, stored, and retained.

Since the slot allocation information stored and held in excess of the number of transmission slots of one multiplexed frame is read in the subsequent multiplexed frame time, it is possible to obtain the operation that digital data is transmitted without loss. The object of the present invention is achieved.

Incidentally, in the above, the retiming circuit 5
Although slot clock signals are used for 1a, 51b, 51c and the pulse generator 52, it is possible to use a clock signal that is 1 / k (k is an integer) of the slot clock signal and is synchronized with the transmission slot period. The same operation as described above is performed and the above effect is obtained. In this case, pulse signal φ4 is generated only in the final cycle of the pulse generation cycle repeated k times within one cycle of the slot clock signal.

The slot allocation information generation circuit of FIG.
By connecting the outputs of the packet input detection circuits 28a, 28b, and 28c as the detection signals, the present invention can be applied not only to the embodiment shown in FIG. 8 but also to the embodiments shown in FIGS. The operation is performed to obtain the above effect. Moreover, in the embodiments shown in FIGS. 8 and 9, since the transmission slot is allocated in correspondence with the packet input time point, there is an additional effect that the multiplexing with extremely small delay time jitter is achieved.

As another embodiment of the present invention, the basic structure thereof is as described above. However, in the case where the digital stream is in the packet format, especially in a plurality of digital streams, each digital stream is digitally converted into a packet of the same format. We are further devising the case where information is transmitted. The structure is shown in FIG.

Referring to FIG. 8, the digital multiplex transmission device 2
At 0, the packets of the digital stream A, the digital stream B, and the digital stream C are input to the buffer memory 21a, the buffer memory 21b, and the buffer memory 21c, respectively, and the buffer memory 21a accumulates the packets of the digital stream A and the buffer memory 21b. Stores the packets of the digital stream B, and the buffer memory 21c stores the packets of the digital stream C. Stuffing packet memory 2
6 stores the stuffing packet in advance.

The transmission slot allocation circuit 23 has a buffer memory 21a, a buffer memory 21b, and a buffer memory 21 according to the slot allocation information output from the slot allocation information generation circuit 50 provided according to the present invention.
c, or the packet stored in the stuffing packet memory 26 is read out, multiplexed in each transmission slot, and output to the packet multiplex frame generation circuit 27.

The packet multiplex frame generation circuit 27 accommodates the slot allocation information output from the slot allocation information generation circuit 50 in one packet and multiplexes it into one transmission slot. And a transmission line 3
Output to 0. In addition, the packet multiplex frame generation circuit 2
7 repeatedly generates and outputs the packet multiplex frame.

FIG. 10 shows an example of the structure of the packet multiplex frame. Referring to FIG. 10, one packet multiplexed frame is composed of n transmission slots,
One transmission slot is one packet. The 0th transmission slot at the head of the packet-multiplexed frame is a multiplexed information packet MIP in which a frame synchronization signal and slot allocation information are multiplexed. Digital stream A packets, digital stream B packets, and digital stream C are stored in the first to n-1th transmission slots.
, Or the stuffing packet is multiplexed. Which packet is multiplexed in each slot is identified by the slot allocation information multiplexed in the 0th transmission slot.

FIG. 11 shows the above multiplexed information packet MIP.
One configuration example is shown. Referring to FIG. 11, the frame synchronization signal and the slot allocation information are multiplexed in the payload part of the multiplexed information packet MIP, and the slot allocation information is multiplexed in the slot allocation information field of the payload part. An example of the structure of the slot allocation information field is shown in FIG.

Referring to FIG. 11, the slot allocation information field is composed of n-1 pieces of slot allocation information, and the arrangement order of each slot allocation information corresponds to the arrangement order of each packet in the packet multiplex frame. . That is,
The first slot allocation information in the slot allocation information field indicates whether the packet multiplexed in the first transmission slot is a digital stream A packet, a digital stream B packet, a digital stream C packet, or a stuffing packet. Is assigned to the second transmission slot, and the second slot allocation information is information indicating the allocation of the packet multiplexed in the second transmission slot.

In FIG. 8, packet input detection circuits 28a, 28b and 28c are provided according to the present invention. The packet input detection circuit 28a monitors the input of packets of the digital stream A to the buffer memory 21a, the packet input detection circuit 28b monitors the input of packets of the digital stream B to the buffer memory 21b, and the packet input detection circuit 28c The input of the packets of the digital stream C to the buffer memory 21c is monitored, and each time one packet is completely input to the buffer memory, the respective detection signals are sent to the slot allocation information generating circuit 50 provided according to the present invention. And the packet input detection circuit which issued the detection signal continuously monitors the next packet input to the buffer memory.

When the detection signal is generated, the slot allocation information generation circuit 50 stores, as slot allocation information, information indicating the digital stream monitored by the packet input detection circuit that generated the detection signal, and If the packet input detection circuit does not generate any information, and if the number of slots allocated up to that time is smaller than the number of slots transmitted up to that time, information indicating stuffing is stored and held as slot allocation information.
In addition, the slot allocation information generation circuit 50 transmits the slot allocation information for one packet multiplexed frame stored and held during the output time of the previous packet multiplexed frame each time the packet multiplexed frame is repeatedly generated and output. It outputs to the allocation circuit 23 and the packet multiplex frame generation circuit 27.

The transmission slot allocation circuit 23 reads the packets of the digital stream allocated to each transmission slot from the buffer memory in accordance with the slot allocation information and sequentially multiplexes them into the 1st to n-1th transmission slots to form a packet multiplexing frame. Output to the generation circuit 27. At this time, the packet multiplex frame generation circuit 23 multiplexes the slot allocation information for one packet multiplex frame into the 0th transmission slot, and n packets including the packets of each transmission slot output from the transmission slot allocation circuit 23. The packet multiplex frame composed of the transmission slots of the above is constructed and the stream is output to the transmission path 30.

Therefore, the number of transmission slots in the packet multiplex frame is automatically assigned according to the packet transmission rate of each digital stream, and the position of the transmission slot assigned to each digital stream is input by the packet of each digital stream. The operation corresponding to the time point is obtained, and the object of the present invention is achieved.

In the receiver 40, the multiplexed frame input from the transmission line 30 is received, the frame synchronization circuit 45 first detects the packet synchronization signal in the header part of the packet to establish packet synchronization, and then the multiplexing information. The frame synchronization signal provided in the payload portion of the packet MIP is detected to establish synchronization with the packet multiplexed frame, and a timing signal indicating the transmission slot position of the multiplexed information packet MIP is output to the slot allocation information separation circuit 43. . This frame synchronization circuit can be easily constructed by those skilled in the art, and a detailed configuration thereof will be omitted.

The slot allocation information separation circuit 43 separates the slot allocation information from the payload portion of the multiplexed information packet MIP based on the timing signal, and the transmission slot selection circuit 42 and the stuffing packet insertion circuit 4
4a, 44b, 44c.

The transmission slot selection circuit 42 selects the transmission slot assigned to each digital stream according to the slot assignment information, extracts the multiplexed packet from the transmission slot, and stuffing packet insertion circuits 44a, 44b. , 44c, respectively.

Stuffing packet insertion circuit 44a
Inserts and outputs a stuffing packet in a transmission slot that is not assigned to the digital stream A according to the slot assignment information. Similarly, the stuffing packet insertion circuit 44b inserts and outputs a stuffing packet into a transmission slot that is not assigned to the digital stream B according to the slot assignment information.
The stuffing packet insertion circuit 44c inserts and outputs a stuffing packet into a transmission slot that is not assigned to the digital stream C according to the slot assignment information.

Therefore, in the receiving device 40, the packets of each digital stream are separated and extracted from the packet multiplex frame, and are output as a packet format stream having the same format as the input to the digital multiplex transmission device 20. Operation is achieved and the object of the invention is achieved.

In the digital multiplex transmission apparatus 20 of this embodiment, the frame synchronization signal is multiplexed in the payload portion of the multiplexed information packet MIP, and the reception apparatus 40 detects the frame synchronization signal to establish synchronization with the packet multiplex frame. However, in the case of a transport stream, a specific packet identifier is added to the header of the multiplexed information packet MIP, and the receiving device 40 detects the packet identifier to perform synchronization with the packet multiplex frame, or frame synchronization. The above operation is performed and the above effects can be obtained by a method of using a signal and a specific packet identifier together.

FIG. 12 is a timing chart showing the operation of the first embodiment of the present invention shown in FIG. 1 and the second embodiment of the present invention shown in FIG. Hereinafter, a detailed description will be given with reference to FIG.

FIG. 12 shows the operation when the multiplexed frame or packet multiplexed frame is composed of 16 transmission slots. Therefore, the slot number counter 64 (see FIG. 4) is a 4-bit binary counter, the count value of which varies from 0 to F depending on the slot clock signal (see FIG. 14).
The count value is represented by a hexadecimal number) is periodically repeated, and this count value corresponds to the slot number of the transmission slot in the multiplexed frame or the packet multiplexed frame.

Digital stream A, digital stream B, digital stream C, or digital stream A, digital stream B, and digital stream C of the same packet format are input at different bit rates, and therefore, as shown in FIG. The time for transmitting a certain amount of data is different.
In the example shown in FIG. 12, the bit rate ratio of the multiplexed frame to the digital stream A, the digital stream B, and the digital stream C is 1: 1 / 4.5: 1/7:
Therefore, the transmission time ratio of a fixed amount of data is 1: 4.5: 7: 4.

This fixed amount of data is the amount of data transmitted in one transmission slot shown in FIG. 2. In the packet format, when the structure and data length of the packet in each stream are the same, the transmission slot is By constructing one packet with one packet, the packet multiplex frame shown in FIG. 10 can be used. However, even in the case of the packet format, it is not necessary to limit the fixed data amount to one packet, and if not limited, the multiplexed frame shown in FIG. 2 can be used.

The data amount measuring circuit 25a of FIG. 1 or FIG.
The packet input detection circuit 28a generates a pulse in the detection signal D1 every time when a fixed amount of data is input from the digital stream A, that is, every time when the fixed amount of data is written in the buffer memory 21a, the slot allocation is performed. The retiming circuit in the information circuit 50 (detailed configuration is shown in FIG.
The operation timing is output to 51a shown in FIG.
At this time, the retiming circuit 51a generates and outputs a pulse having a 1-cycle time width of the slot clock signal as shown in FIG. 12 immediately after the pulse is generated in the detection signal D1.

The same operation is performed on the digital stream B and the digital stream C, and each time the fixed amount of data from each digital stream is written to the buffer memory, the retiming circuit 51b and the retiming circuit 51c respectively output the data. At the time indicated by 12, a pulse having a 1-cycle time width of the slot clock signal is output.

In FIG. 12, for the sake of explanation,
A number from 1 to 29 is assigned in order of the detection time point to each area of the constant data amount detected as the time point when the constant data amount is sequentially input from the digital stream A, the digital stream B, and the digital stream C. is doing.

Stream number encoder 54 (FIG. 4)
Receives the pulse signals (φ1, φ2, φ3 in FIG. 5) that have been input through the AND gates 53a, 53b, and 53c (FIG. 4) controlled by the respective retiming signals. Accordingly, as shown in FIG. 14, the memory 60 generates information (indicated as A, B, and C in the figure) indicating the digital stream assigned to the transmission slot.
(Fig. 4).

At the same time, the write address counter 57 (FIG. 4) generating the write address of the memory 60 increments the write address value by one each time the pulse signal is received. Also, during the time when the fixed amount of data is not reached, the pulse signal is not input, so the update of the write address value is temporarily stopped.

However, since the size comparison circuit 59 (FIG. 4) compares the count value of the slot number counter 64 (FIG. 4) with the count values b3 to b0 of the write address counter, the size comparison circuit 59. From FIG. 12, as shown in FIG. 12, when the count value of the write address counter is smaller, '1' is output, and each time the output is performed, the pulse signal φ4 (passes through the AND gate 53d (FIG. 4). (Fig. 5)
The write address counter 57 counts and the write address value is incremented by one.

The passed pulse signal φ4 is also given to the stream number encoder 54 at the same time, and at this time, the stream number encoder 54 outputs information indicating the allocation of the stuffing packet (denoted by n in the figure) to the memory 60.

In this way, the memory 60 is stored in FIG.
Information (output to the stream number encoder 54) indicating slot allocation shown in FIG. 12 is written in the address (write address value of the memory 60) shown in FIG. Moreover, the address in which the information indicating the allocation of the slot to the data of each digital stream is written in this way is the value indicated by the slot number counter 64 when the input data reaches a certain amount of data, that is, It is apparent from the embodiment shown in FIG. 12 that this corresponds to the slot number immediately after the slot number of the transmission slot being transmitted.

When the detection signal generated at the time when a certain amount of data reaches a plurality of streams is generated at the same point, for example, when the count value of the slot number counter 64 is 6, C4 is input. It is also clear from FIG. 12 that the time domain data with the numbers B5 and B5 are written to the addresses (07, 08) corresponding to the immediately following consecutive slot numbers. Further, it is also clear from FIG. 12 that the information indicating the allocation of the stuffing packet is written in the addresses corresponding to the slot numbers excluding the slots allocated according to the time when such a fixed amount of data is reached.

Therefore, the number of transmission slots is automatically assigned to each stream according to the amount of digital information of each digital stream, that is, the number of times a certain amount of data is reached per frame, and the transmission is also assigned. It is clear from FIG. 12 that the slot number of the slot corresponds to each time when it is detected that a certain amount of data has been reached.

Each time the count value of the slot number counter 64 returns from 0 to 0, the value of the most significant digit b4 of the write address counter 57 is held by the flip-flop 61 (FIG. 4), and the value is logically inverted. Is given as the most significant digit of the read address value of the memory 60.

Therefore, as shown in FIG. 12, the slot allocation information for one frame created during the previous frame time is read out and output from the memory 60. The transmission slot allocation circuit 23 (FIG. 1) uses the buffer memory (21 a, 21 b, 21 in FIG. 1) according to the slot allocation information.
c) or a fixed amount of data is read from the stuffing data memory 22 (FIG. 1) and multiplexed into each transmission slot, and when the packet multiplex frame of FIG. 10 is used in the case of a packet format stream, the transmission slot allocation circuit 23 (FIG. 8) is a buffer memory (21 in FIG. 8).
a, 21b, 21c) or the stuffing packet memory 26 (FIG. 8), and the packets are multiplexed in each transmission slot.

The multiplexed frame generation circuit 24 (FIG. 1) is
The multiplexing information slot MIS (FIG. 2) for transmitting the slot allocation information and the frame synchronization signal is placed in the slot of the transmission slot number 0 at the head of the frame and multiplexed,
The multiplexed frame shown in is generated and sent to the transmission path. When the packet multiplex frame of FIG. 10 is used in the case of a packet format stream, the packet multiplex frame generation circuit 27 (FIG. 8) uses the multiplex information packet MIP for transmitting the slot allocation information and the frame synchronization signal.
(FIG. 11) is multiplexed into the slot having the transmission slot number 0 at the head of the frame, and the packet multiplexed frame shown in FIG. 10 is generated and sent to the transmission path.

As described above, the delay time of one frame is fixedly added to the time until the fixed amount of data that has been input is multiplexed and transmitted in the transmission slot of the multiplexed frame or the packet multiplexed frame. However, this added delay time is fixed and does not cause delay time jitter. That is, the fluctuation of the delay time is only the time fluctuation from the completion of the input of the fixed amount of data to the transmission time of the transmission slot of the transmission slot number corresponding to the address in which the information indicating the allocation is generated and written by the stream encoder 54. Becomes

As shown in FIG. 12, most of the fluctuation amount of delay time (delay time jitter amount) is one transmission slot time or less, and a constant data amount is input at the same time for three slots clock signals in the same cycle. However, as shown in FIG. 12, when the count value of the slot number counter 64 is 2, A23, B22, and C21 that have been input are completed.
The data in the time domain with the number is
Addresses corresponding to the slot numbers (03, 04, 0
As is clear from the data written in 5), it is less than 3 transmission slot times.

In FIG. 12, a plurality of slots allocated when a plurality of slots are simultaneously input in the same cycle of the slot clock signal are digital stream A, digital stream B, and digital stream C.
Are assigned in that order. The order of priority is the pulse signals φ1, φ2, φ3 input to one input terminal of the AND gates 53a, 53b, 53c shown in FIG. 4 (FIG. 5).
It is simply determined by the order of occurrence time of.

Therefore, the AND gates 53a, 53
The priority order can be easily changed by simply exchanging the pulse signals of the three pulse signals input to one of the input terminals of b and 53c. For example, every time the plurality of simultaneous inputs are completed, the logical product gate to which the pulse signal φ1 was given at the previous completion of the plurality of simultaneous inputs is φ.
3 is given, and φ1 is given to the AND gate to which the pulse signal φ2 was given, and φ2 is given to the AND gate to which the pulse signal φ3 was given. Can evenly assign the slot allocation priority to each digital stream.

After the slots have been assigned to all the slots within one frame time as described above, if there is a packet whose input is further completed within that frame time (in FIG. 12, the count of the slot number counter 64 is counted). When the value is E, the C20 numbered time domain data that has been input) is written in the first slot (the write address value is 01 in FIG. 12) in the subsequent frame, and the value of the most significant digit is immediately before. It is clear that it is allocated from the 1 to 0 in writing up to) and is therefore interleaved and transmitted in the following frame with the minimum delay time.

In the case of multiplexing three digital streams as in the example of FIG. 12, the generation of multiplexing delay time jitter of 2-3 transmission slot times can be avoided in principle regardless of any method. Absent. In general, when k digital streams are multiplexed, the generation of multiplexing delay time jitters in k-1 to k transmission slot times is unavoidable in principle. Therefore, according to the present invention, it is apparent that the multiplexing in which the generation amount of the delay time jitter in the multiplexing is extremely small is performed.

As the third embodiment of the present invention, the configuration thereof is as described above, but when the digital stream is in the packet format, particularly when multiple transport streams are multiplexed, In each digital stream, digital information is transmitted in packets of the same format, and the information transmission rate is freely changed with respect to the physical transmission rate. The difference between the physical transmission rate and the information transmission rate is the stuffing packet (null). We are further devising the case of multiplex transmission of digital streams supplemented by packets. The structure is shown in FIG.

In FIG. 9, the same parts as those in FIG. 8 perform the same operations, and the description thereof will be omitted. In the digital multiplex transmission device 20 shown in FIG. 9, a digital stream A, a digital stream B, and a digital stream C are provided.
Are input to stuffing packet removal circuits 29a, 29b, 29c provided according to the present invention.

Stuffing packet removal circuit 29a
Removes the stuffing packet (null packet) included in the digital stream A and outputs only the valid packet to the buffer memory 21a. At this time, the stuffing packet is identified by the value of the packet identifier in the header part of the packet. Similarly, the stuffing packet removal circuit 29b is used by the digital stream B
Stuffing packet included in the digital stream C is output to the buffer memory 21b, and the stuffing packet removal circuit 29c removes the stuffing packet included in the digital stream C and outputs only the valid packet to the buffer memory 21c.

The buffer memory 21a stores the valid packets of the digital stream A output from the stuffing packet removing circuit 29a, and similarly, the buffer memory 21b stores the stuffing packet removing circuit 29b.
The valid packet of the digital stream B output from the buffer memory 21c is stored in the buffer memory 21c, and the valid packet of the digital stream C output from the stuffing packet removal circuit 29c is stored in the buffer memory 21c.

At this time, the packet input detection circuit 28a
Is the digital stream A to the buffer memory 21a.
Input of valid packets of the digital stream B to the buffer memory 21b, the packet input detection circuit 28b monitors input of valid packets of the digital stream B to the buffer memory 21b, and the packet input detection circuit 28c validates the digital stream C to the buffer memory 21c. Watching for packet input.

Therefore, the digital multiplex transmission device 20
In this case, since the number of transmission slots in the packet multiplex frame is automatically assigned according to the rate of effective packets of each digital stream, that is, the digital information transmission rate, the multiplexing efficiency is increased, and moreover, the number of transmission slots assigned to each digital stream is increased. Since the position corresponds to the time when the valid packet of each digital stream is input, the operation that the delay time jitter in the multiplexing is reduced is obtained, and the object of the present invention is achieved.

At this time, in the receiving device 40, the effective packet of each digital stream is separated and taken out from the packet multiplex frame, and the stuffing packet is supplemented, which has the same format as the input to the digital multiplex transmission device 20. The operation of separating and outputting as a packet format stream is obtained, and the object of the present invention is achieved.

FIG. 13 is a timing chart representing an operation of the embodiment of the present invention shown in FIG. Hereinafter, the operation of the third exemplary embodiment of the present invention will be described in detail with reference to FIG.

FIG. 13 shows an operation example in the case where the packet multiplex frame is composed of 16 packets. Therefore, the slot number counter 64 (FIG. 4) in the slot allocation information generating circuit 50 is It is a 4-bit binary counter, and the count value is cyclically repeated from 0 to F (the count value is expressed in hexadecimal in FIG. 13) by the slot clock signal, and this count value is packet-multiplexed. It corresponds to the slot number of the transmission slot in the frame.

Digital stream A, digital stream B, digital stream C of the same packet format
Are input at different physical rates, and therefore the transmission time of one packet is different as shown in FIG. 13, but the packet structure and data length are the same.

Also, in FIG. 13, digital stream A, digital stream B, and digital stream C
Include stuffing packets, and the digital information transmission rate and the physical transmission rate are different.

Note that, in FIG. 13, for the sake of explanation, the valid packets included in the digital stream A, the digital stream B, and the digital stream C are numbered from 1 to 29 in order of the time of completion of input. .

The packet input detection circuit 28a generates a pulse in the detection signal D1 every time the input of the valid packet from the digital stream A is completed, that is, every time the writing to the buffer memory 21a is completed, and the packet input detection circuit 28a in the slot allocation information circuit 50 is provided. It is output to the retiming circuit 51a (detailed configuration of the retiming circuit is shown in FIG. 6 and operation timing is shown in FIG. 7). At this time, the retiming circuit 51a operates as shown in FIG.
As shown in, a pulse having a one-cycle time width of the slot clock signal is generated and output immediately after the pulse is generated in the detection signal D1.

The same operation is performed for the digital stream B and the digital stream C, and each time the valid packet from each digital stream is written in the buffer memory, the retiming circuit 51b and the retiming circuit 51c respectively output the same figure. At the time point indicated by 13, a pulse having a 1-cycle time width of the slot clock signal is output.

Stream number encoder 54 (FIG. 4)
Receives the pulse signals (φ1, φ2, φ3 in FIG. 5) that have been input through the AND gates 53a, 53b, and 53c (FIG. 4) controlled by the respective retiming signals. Accordingly, as shown in FIG. 12, information indicating the digital stream to be allocated (A,
B and C) are generated and output to the memory 60 (FIG. 4).

At the same time, the write address counter 57 (FIG. 4) generating the write address of the memory 60 increments the write address value by one each time the pulse signal is received. Also in (1), when the valid packet is not input, the pulse signal is not input, so the update of the write address value is temporarily stopped.

However, since the size comparison circuit 59 (FIG. 4) compares the count value of the slot number counter 64 (FIG. 4) with the count values b3 to b0 of the write address counter, the size comparison circuit 59. From FIG. 12, as shown in FIG. 12, when the count value of the write address counter is smaller, '1' is output, and each time the output is performed, the pulse signal φ4 (passes through the AND gate 53d (FIG. 4). (Fig. 5)
The write address counter 57 counts and the write address value is incremented by one.

The passed pulse signal φ4 is also given to the stream number encoder 54 at the same time, and at this time, the stream number encoder 54 outputs information indicating the allocation of the stuffing packet (denoted by n in the figure) to the memory 60.

In this way, the memory 60 is stored in FIG.
Information (output of the stream number encoder 54) indicating slot allocation shown in FIG. 13 is written in the address (write address value of the memory 60) shown in FIG. Moreover, the address in which the information indicating the allocation of the slot to the packet of each digital stream is written is the value indicated by the slot number counter 64 at the time when the input of the valid packet is completed, that is, the transmission being performed at that time. It is clear from FIG. 13 that it corresponds to the slot number immediately after the slot number of the slot.

When a plurality of valid packets are simultaneously input, for example, the packets with the numbers B6 and C7 that have been input when the count value of the slot number counter 64 is A are immediately following consecutive packets. It is also clear from FIG. 13 that the data is written in the addresses (0B, 0C) corresponding to the slot numbers of. Further, it is also apparent from FIG. 13 that information indicating the allocation of the stuffing packet is written in the addresses corresponding to the slot numbers other than the slots allocated according to the completion of input of such valid packets.

Therefore, transmission slots are automatically assigned according to the amount of digital information of each digital stream, that is, the number of input valid packets per frame, and the slot number of the assigned transmission slot is the time when each valid packet is input. It is clear from FIG. 13 that it corresponds to.

Each time the count value of the slot number counter 64 returns from 0 to 0, the value of the most significant digit b4 of the write address counter 57 is held by the flip-flop 61 (FIG. 4), and the logically inverted value is set. It is given as the most significant digit of the read address value of the memory 60.

Therefore, as shown in FIG. 13, the slot allocation information for one frame created during the previous frame time is read from the memory 60 and output. The transmission slot allocation circuit 23 (FIG. 9) uses the buffer memory (21a, 21b, 21 in FIG. 9) according to the slot allocation information.
c) Alternatively, the packet is read from the stuffing packet memory 26 (FIG. 9) and multiplexed in each transmission slot.

The packet multiplex frame generation circuit 27 (FIG. 9) multiplexes the multiplex information packet MIP (FIG. 11) for transmitting the slot allocation information and the frame synchronization signal into the slot of the transmission slot number 0 at the beginning of the frame. 1
The packet multiplex frame indicated by 0 is generated and sent to the transmission path.

As described above, the delay time of one frame is fixedly added to the time from the input of the valid packet to the transmission of the packet multiplexed frame after being multiplexed. However, since the added delay time is fixed, delay time jitter does not occur. That is, the fluctuation of the delay time is only the fluctuation of the time from the completion of the input of the valid packet to the transmission of the transmission slot having the transmission slot number corresponding to the address in which the information indicating the allocation is generated and written by the stream encoder 54. .

As shown in FIG. 13, most of the delay time jitter is one transmission slot time or less, and even when three valid packets are input in the same cycle of the slot clock signal, as shown in FIG. , The packets with the numbers A29, B27, and C28 that have been input when the count value of the slot number counter 64 is B,
As is clear from the fact that the data is written in the addresses (0C, 0D, 0E) corresponding to the three consecutive slot numbers immediately after, it is less than three transmission slot times.

Further, after the allocation to all slots within one frame time is performed as described above, the packet which is further input within the frame time (in FIG. 13, the count value of the slot number counter 64 is E If there is a packet with the B11 number that has been input at the time of, the first slot in the subsequent frame (see FIG. 1).
In 3, the write address value is 11, and the value of the most significant digit is changed from 0 to 1 in the writing so far). Therefore, it is also apparent that the subsequent frame is transmitted by being interleaved with a minimum delay time.

In the case of multiplexing three digital streams of the same packet format as shown in FIG. 13, which has been described as an example, it is theoretically possible to perform multiplexing of 2-3 transmission slot times regardless of any method. It is inevitable that the delay time jitter will occur. Therefore, according to the present invention, it is apparent that packet multiplexing with extremely small delay time jitter is performed.

FIG. 14 is a block diagram showing a configuration example of a digital multiplex transmission device according to the fourth embodiment of the present invention.

Specifically, the configuration of the digital multiplex transmission device including the digital multiplex circuit 20, the PCR correction amount generation circuit 80, the PCR correction circuit 92, the PSI insertion circuit 93, and the PSI memory 94 in this embodiment. An example is shown, in which a plurality of programs are selected from three input streams of the input stream A, the input stream B, and the input stream C in the transport stream format and multiplexed, and one transport stream is selected. Is generated and transmitted.

In FIG. 14, the digital multiplexing circuit 20
Then, the input stream A is input to the buffer memory 21b through the PID filter / conversion circuit 71a, the input stream B is input to the buffer memory 21b through the PID filter / conversion circuit 71b, and the input stream C is input.
Is input to the buffer memory 21c through the PID filter / conversion circuit 71c.

The PID filter / conversion circuit 71a identifies the packet identifier PID attached to the header portion of the input TS packet, removes unmultiplexed TS packets in the input stream, and multiplexes the program T.
Only the S packet is passed and output to the buffer memory 21a. The PID filter / conversion circuit 71b identifies the packet identifier PID attached to the header portion of the input TS packet, removes unmultiplexed TS packets in the input stream, and passes only TS packets of the program to be multiplexed. And outputs it to the buffer memory 21b. The PID filter / conversion circuit 71c inputs TS
The packet identifier PID attached to the header part of the packet is identified, and the TS not multiplexed in the input stream
The packet is removed, and only the TS packet of the program to be multiplexed is passed and output to the buffer memory 21c.

Furthermore, each PID filter / conversion circuit 71
a, 71b, and 71c are PIs of TS packets to be passed.
D is the PID of a TS packet from another input stream
The PID values are appropriately rewritten and output so that they do not overlap each other. This PID filter / conversion circuit 71a-71
Since c can be easily configured by those skilled in the art, detailed description of its configuration will be omitted.

The buffer memory 21a stores the TS packets which have passed through the PID filter / conversion circuit 71a, and the buffer memory 21b stores the PID filter / conversion circuit 71a.
The TS packets that have passed through b are accumulated and stored in the buffer memory 2
1c is a T that has passed through the PID filter / conversion circuit 71c.
Store S packets. The stuffing packet memory 26 stores null packets in advance.

The transmission slot multiplexing circuit 90, in accordance with the slot allocation information output from the slot allocation information generating circuit 91, includes the buffer memory 21a and the buffer memory 21.
b, the TS packet accumulated in the buffer memory 21c is taken out and multiplexed in the corresponding transmission slot, or the null packet accumulated in the stuffing packet memory 26 is read out and multiplexed in the corresponding transmission slot, and PCR is performed. Output to the correction circuit 92. The transmission slot multiplexing circuit 90 can be configured by a read control circuit of each memory, a selector circuit, and the like, and can be easily configured by those skilled in the art. Therefore, detailed description of the configuration will be omitted.

The PCR correction circuit 92, for the PCR_PID packet being output from the transmission slot multiplexing circuit 90,
The correction amount output from the PCR correction amount generation circuit 80 is set to P
The PCR field value of the CR_PID packet is arithmetically added and output to the PSI insertion circuit 93. Since the PCR correction circuit 92 is composed of a full adder, a shift register, etc., and can be easily constructed by those skilled in the art,
Detailed description of the configuration is omitted.

The PSI memory 94 describes the program organization in the multiplexed output stream and the correspondence between the packet identifier PID of the TS packet and the program number.
A plurality of TS packets accommodating PSI defined by PEG-2 are stored in advance. This PSI is information necessary for the receiver to select a desired program from the plurality of programs multiplexed in the multiplexed output stream sent by the packet multiplex transmission device, and to decode and display the desired program.

The PSI inserting circuit 92 sequentially takes out TS packets containing PSI one by one from the PSI memory 94, inserts them into the output of the PCR correcting circuit 92, and outputs them. At this time, the PSI insertion circuit 93 replaces the null packet included in the output of the PCR correction circuit 92 with the PSI memory 9
It is replaced with the TS packet extracted from No. 4. The PSI insertion circuit 93 is composed of a timer circuit, a null packet detection circuit, a memory read control circuit, and the like, and can be easily constructed by those skilled in the art. Therefore, detailed description of the configuration will be omitted.

The packet input detection circuit 28a monitors the input of the TS packet of the input stream A to the buffer memory 21a, and the packet input detection circuit 28b monitors the input of the TS packet of the input stream B to the buffer memory 21b. The packet input detection circuit 28c monitors the input of TS packets of the input stream C to the buffer memory 21c. Each packet input detection circuit 28a
28c detect the input of TS packets to the buffer memories 21a to 21c, and each time one TS packet completes the input to the buffer memories 21a to 21c, the input detection signal to the slot allocation information generation circuit 91. Is output.

The slot allocation information generating circuit 91 generates slot allocation information for each predetermined fixed number of transmission slots (hereinafter referred to as one multiplexing group) and outputs it to the transmission slot multiplexing circuit 90. Slot allocation information generation circuit 91
Then, the slot allocation information is generated as follows.

When the input detection signal is generated, the slot allocation information generating circuit 91 stores information indicating the corresponding input stream as slot allocation information. Here, the corresponding input stream is an input stream monitored by the packet input detection circuits 28a to 28c that have generated the input detection signal. Further, no input detection signal is generated from any of the packet input detection circuits 28a to 28c,
In the above-mentioned one multiplexing group, when the number of slot allocation information allocated up to that point is smaller than the number of slots to be transmitted up to the simultaneous point, the slot allocation information generating circuit 91 outputs information indicating stuffing as slot allocation information. Memorize as.

In the slot allocation information generating circuit 91, while one multiplexing group based on the previously generated slot allocation information is being transmitted from the transmission slot multiplexing circuit 90,
New slot allocation information is generated. The generated slot allocation information is 1 in the transmission slot multiplexing circuit 91.
It is output from the slot allocation information generating circuit 91 to the transmission slot multiplexing circuit 90 at the transmission cycle of the multiplexing group.

The transmission slot multiplexing circuit 90 stores the TSs stored in the buffer memories 21a to 21c according to the slot allocation information input from the slot allocation information generating circuit 91.
Packet or stuffing packet memory 26
The null packets stored in are extracted and multiplexed. Therefore, the packet multiplexing circuit 20 according to the present embodiment performs the following multiplexing.

The number of transmission slots assigned to each input stream A, B, C in one multiplexing group is set according to the number of TS packets that have passed through each PID / conversion circuit 71a, 71b, 71c. Further, the position of the transmission slot allocated in one multiplexing group for the TS packets input from the respective input streams A, B, C is the time when the TS packets are input to the buffer memories 21a to 21c for each input stream. Corresponding to.

FIG. 15 is a block diagram showing an example of the configuration of the slot allocation information generating circuit 91 in the digital multiplexing circuit 20 according to this embodiment. Hereinafter, the configuration and operation of the slot allocation information generation circuit 91 of FIG. 15 will be described in detail.

The retiming circuit 51a, the retiming circuit 51b, and the retiming circuit 51c have input detection signals D1 to D3 from the packet input detection circuits 28a to 28c.
Are input respectively. Retiming circuits 51a to 51
c retiming each input detection signal D1, D2, D3 with a half slot clock signal,
It outputs to one input terminal of 3a, 53b, 53c.

The pulse generation circuit 52 generates pulse signals φ1, φ2, φ3, φ4 having different pulse generation positions based on the half slot clock signal and the slot clock signal. The generated pulse signal φ1 is supplied to the AND gate 53.
a is output to the other input terminal of a, the pulse signal φ2 is output to the other input terminal of the AND gate 53b, the pulse signal φ3 is output to the other input terminal of the AND gate 53c, and the pulse signal φ4 is output. The AND gate 53d is output to the other input terminal.

The output of the logical product gate 53a is connected to the stream number encoder 54 and the logical sum gate 55. Similarly, the outputs of the AND gates 53b, 53c, 53d are also connected to the stream number encoder 54 and the OR gate 55, respectively. The stream number encoder 54 outputs the information for identifying the stream to the AND gate 53.
It is generated according to the input of a to 53c and is output to the data input terminal Din of the memory 60. The logical sum gate 55 stores the logical sum of the outputs of the logical product gates 53a to 53d in the memory 60.
Write enable terminal WE and write address counter 5
Output to 7.

The write address counter 57 is composed of a 5-bit binary counter, counts pulses generated at the output of the OR gate 55, and stores the most significant bit b4 (MSB) of the count value in the memory 60. The write address terminal WAH and the data input terminal D of the flip-flop 61 are output, and the lower bits b3 to b0 of the count value are output to the memory 6.
It is output to the write address terminal WAL of 0 and one input terminal X of the magnitude comparison circuit 59.

The slot number counter 64 is composed of a 4-bit binary counter that is one bit less than the write address counter 57, counts the slot clock signal, and outputs the count values b3 to b0 to the read address terminal of the memory 60. The carry signal CR is output to the other input terminal Y of the RAL and the magnitude comparison circuit 59, and the carry signal CR is output to the input terminal of the logic inverting gate 63.

The magnitude comparison circuit 59 determines the lower 4 of the count value of the write address counter 57 input to the input terminal X.
The value of the bit and the value of the 4-bit count value of the slot number counter 64 input to the input terminal Y are compared. When the value input to X is less than the value input to Y (for example, X = Y−1), the magnitude comparison circuit 5
9 outputs a true value "1", and outputs a false value "0" when the value input to X is equal to or more than the value input to Y, and each output is a logical product. Gate 53d
Applied to the other input terminal of.

The logic inverting gate 63 logically inverts the input and supplies it to the clock terminal CLK of the flip-flop 61. The flip-flop 61 reads and holds data from the data input terminal D in synchronization with the clock, and
It outputs to the input terminal of the logic inversion gate 62. The logic inversion gate 62 logically inverts the input and outputs it to the read address terminal RAH of the memory 60.

In the memory 60, the write address counter 5
The output of the stream number encoder 54 is written and stored in the address indicated by the counter value of 7 and the data stored in the address indicated by the output of the logical inversion gate 62 and the count value of the slot number counter 64. Is read out and output as slot allocation information.

The operation of slot allocation information generating circuit 91 shown in FIG. 15 will be described in detail below.

The number of bits of the slot number counter 64 in the slot allocation information generating circuit of the present invention is determined in correspondence with the number of transmission slots forming one multiplexing group. In the present embodiment, the number of bits of the slot number counter 64 is set. The number is 4. This is a multiplexing group 2 of 4
This corresponds to the case where it is configured with the power of 16, that is, 16 transmission slots.

Note that the number of transmission slots in one multiplexing group is not limited to 2 to the nth power (n is a positive integer), and any m
(M is a positive integer). In that case, the slot number counter 64 is a m-ary counter and is a counter that outputs the count value in a binary number format, while the write address counter 57 is one digit larger than the slot number counter 64 by m. It is a base number counter which outputs a count value in a binary number format, and the upper digit is output as 1 bit.

FIG. 16 is a timing chart showing an operation example of the pulse generating circuit 52. As is clear from the figure, the half-slot clock signal is synchronized with the slot clock signal, and its one cycle time is equal to half the one cycle time of the slot clock signal and half the transmission time of one transmission slot. ing.

The pulse generation circuit 52 generates three pulse signals φ1 to φ3 at different pulse generation positions for each cycle of the half slot clock signal. Further, the pulse generation circuit 52 generates a pulse signal φ4 having a pulse generation position different from that of the pulse signals φ1 to φ3 for each cycle of the slot clock signal, and the pulse generation position is located behind the pulse signals φ1 to φ3. is there.

The pulse signals .phi.1 to .phi.3 are output from the retiming circuits 51a to 51c, and the logical product gates 53 are output.
The passage of a through 53c is controlled, and the AND gates 53a, 53a,
The pulse signals φ1 to φ3 that have passed through 3b and 53c are given to the stream number encoder 54 and the AND gate 55.

FIG. 17 is a timing chart showing an operation example of retiming circuits 51a to 51c shown in FIG. The input detection signals output from the packet input detection circuits 28a to 28c are in a pulse signal format, and an input detection signal is generated each time one TS packet is input to the buffer memories 21a to 21c, and the retiming circuits 51a to 51c
To enter.

The flip-flop F1 is preset by this input detection signal, and the output from the flip-flop F1 becomes "1". Next, when the rising edge of the half slot clock signal is input to the clock terminal CLK,
The output of the flip-flop F1 is read by the flip-flop F2 from the data input terminal D, and
The output of 2 becomes '1'. At the same time, flip-flop F
Since the rising edge of the half-slot clock signal is also input to the clock terminal CLK of No. 1, the flip-flop F
1 reads "0" from the data input terminal D, and its output becomes "0". If the flip-flop F1 is not newly preset by the input detection signal, the flip-flop F2 receives the output "0" of the flip-flop F1 in response to the rising edge of the half-slot clock signal in the next cycle, and the output is "0". It becomes 0 '.

In this way, the input detection signals D1 to D3
1 pulse generated in each retiming circuit 51a,
At 51b and 51c, the pulse is converted into a pulse having a half time width with respect to one cycle time of the half slot clock signal, that is, one transmission slot, and output to the AND gates 53a, 53b and 53c.

Therefore, every time the input detection signals D1 to D3 are generated, the output of the retiming circuit to which the input detection signal is input is connected for the period of one cycle immediately after the rise of the half slot clock signal. The AND gates 53a to 53c are opened. Therefore, the pulse generation circuit 5
The pulse signal from 2 is the open AND gates 53a-5
3c and is given to the stream number encoder 54, and at the same time, the write address counter 57 and the memory 60.
Is also applied to the write enable terminal WE.

At this time, the write address counter 57 is
The pulse signal applied through the OR gate 55 is counted, the count value is incremented by 1, and a new write address value is output to the memory 60.

On the other hand, in the stream number encoder 54, since the pulse signal is given from the AND gates 53a to 53c corresponding to the input stream, information indicating the input stream corresponding to this pulse signal (hereinafter referred to as stream number) is obtained. It is generated and output to the data input terminal Din of the memory 60. Therefore, the stream number is sequentially written and stored in the memory 60 each time an input detection signal is generated.

When a plurality of input detection signals are generated during the same cycle time of the half slot clock signal, in the present embodiment, the generation positions of the pulse signals given from the pulse generation circuit 52 to the AND gates 53a to 53c are changed. As shown in FIG. 16, the stream number encoder 54 receives different pulse signals having different pulse generation positions from different AND gates 53a to 53c, and the write address counter 57 also receives a logical sum. A plurality of pulse signals are input through the gate 55.

Therefore, the stream number encoder 54 is based on the input of the pulse signals having different pulse generation positions.
The stream numbers output from are sequentially written and stored in different addresses in the memory 60.

On the other hand, when the input detection signals D1 to D3 are not generated, since the pulse signals are not given from the AND gates 53a to 53c, the stream number is not written in the memory 60, and the write address counter 57 does not receive the stream number. However, the count value is not updated by any of the pulse signals φ1 to φ3.

The slot number counter 64 is a 4-bit binary counter that increments the count value for each cycle of the slot clock signal, and the count value corresponds to the slot number of the transmission slot forming the multiplexing group. There is. Here, the slot numbers are named for convenience of explanation of the operation, such as 0, 1, 2, ... In the transmission order from the first transmission slot of the multiplexing group.

The magnitude comparison circuit 59 compares the 4-bit output value of the slot number counter 64 with the write address counter 57.
When the write address counter 57 side is small, the logical product gate 5
The true value "1" is output to one input terminal of 3d. At this time, the gate of the AND gate 53d is opened, and the pulse signal φ4 from the pulse generator 52 is given to the stream number encoder 54. At the same time, the pulse signal φ4 is written enable to the write address counter 57 and the memory 60. It is also given to the terminal WE.

When receiving the pulse signal φ4 from the AND gate 53d, the stream number encoder 54 generates a number indicating stuffing and outputs it to the data input terminal Din of the memory 60.

Therefore, in the slot allocation information generating circuit 91 according to the present embodiment, the step of the counter value of the write address counter 57 due to the generation of the input detection signals D1 to D3 is
When the count value of the slot number counter 64 is less than the step, the count value of the write address counter 57 automatically follows the count value of the slot number counter 64, and the stuffing number is written in the memory 60. The operation of being stored is performed.

When a plurality of input detection signals are generated during half the transmission time of one transmission slot, the pulse positions of the pulse signals φ1 to φ3 are set to one cycle of the half slot clock signal in this embodiment. Since the memory 60 is arranged at different positions, the respective stream numbers are written in the memory 60 while sequentially updating the write address. More specifically, when a plurality of input detection signals are generated during half the transmission time of one transmission slot, the address at which each stream number is written in the memory 60 is immediately after the generation of those input detection signals. It corresponds to the slot number of the transmission slot transmitted from the transmission slot multiplexing circuit 23 and the slot number of the transmission slot immediately following it.

Further, when the input detection signal is not generated and the number of slot allocation information allocated up to that point in one multiplexing group is smaller than the number of slots to be transmitted up to the simultaneous point, immediately after the time point. An operation is performed in which a number indicating stuffing is stored in an address corresponding to the slot number of the transmission slot transmitted from the transmission slot multiplexing circuit 23.

Read address terminal RAL of memory 60
Is given a 4-bit count value of the slot number counter 64, and the read address terminal RAH is given a value obtained by logically inverting the output of the flip-flop 61. The read enable signal is constantly and continuously applied to the memory 60 (the description of this signal is omitted in FIG. 15), whereby the memory 60 of the stream number is
The data is read continuously from the data output terminal Dout according to the read address given to the memory 60.

In the memory 60, the read address terminal RAL and the write address terminal WAL have the same digit, and the read address terminal RAH and the write address terminal WAH have the same digit. The carry signal CR from the slot number counter 64 is logically inverted by the logical inversion gate 63 and applied to the clock terminal CLK of the flip-flop 61. Therefore, every time the count value of the slot number counter 64 returns from the maximum value (F in hexadecimal notation) to the initial value (0), the value of the most significant bit b4 of the write address counter 57 at that time is the flip-flop 61. Is read and held, and its logical inversion value is given to the read address terminal RAH.

On the other hand, in the memory 60, new slot allocation information for one multiplexing group is stored during transmission of the previous multiplexing group, that is, the multiplexing group based on the previously generated slot allocation information. Complete. Therefore, the value given to the read address terminal RAH of the memory 60 by the above operation is the write address terminal W when the new slot allocation information is stored in the memory 60.
The value input to AH is given.

Therefore, from the memory 60, the stream number or the number indicating the stuffing written in the memory 60 while the previous multiplexing group is transmitted is read. In the read operation, the stream number or the number indicating the stuffing is read one by one in each cycle of the slot clock signal, and the same as the number of transmission slots forming one multiplexing group per transmission time of one multiplexing group. As the number, the stream number or the number indicating stuffing written in the memory 60 is read out and output from the memory 60 as slot allocation information for one multiplexing group.

Therefore, the slot allocation information generating circuit 91 in the present embodiment causes the transmission slot multiplexing circuit 90 to provide the slot allocation information for allocating the TS packet or null packet of each input stream to the corresponding transmission slot for multiplexing. The operation is automatically created and output.

Further, in the present embodiment, the number of bits of the write address counter 57 is one bit larger than the number of bits of the slot number counter 64, and the count range is twice that of the slot number counter 64. For this reason, the TS packet speed passing through the PID filter / conversion circuits 11a to 11c fluctuates, and the total number of TS packets to be multiplexed input within the transmission time of one multiplexing group is temporarily 1 multiplexing group. In this embodiment, the slot allocation information is normally created and stored even when the number of transmission slots is exceeded.

Since the slot allocation information stored in the memory 60 in excess of the number of transmission slots of one multiplexing group is read out at the transmission time of the multiplexing group subsequent to the relevant multiplexing group, it is read in each of the input streams A to C. 1
If the average value of the total of the TS packets to be multiplexed input within the multiplexing group transmission time is less than or equal to the number of transmission slots of one multiplexing group, the buffer memories 21a to
The TS packets input to 21c are multiplexed and transmitted without loss.

In the above-described embodiment, the retiming circuits 51a to 51c and the pulse generating circuit 52 are included.
The half-slot clock signal is used for the present invention, but in the present invention, one cycle time is 1 / k of the slot clock signal.
(K is an integer greater than or equal to 1) and even if a clock signal synchronized with the transmission slot period is used, the same operation as the slot allocation operation described above can be obtained, and the physical speed of each input stream is the multiplexed output speed. It can be used in a range of less than k times. At this time, the pulse signal φ4 may be generated only in the final cycle of the pulse generation cycle repeated k times per slot clock signal cycle time, and may be generated behind the pulse signals φ1, φ2, and φ3.

FIG. 18 is a timing chart showing an operation example of the digital multiplex transmission apparatus in this embodiment shown in FIG. Hereinafter, the operation of the digital multiplex transmission apparatus according to this embodiment will be described in detail with reference to FIG.

FIG. 18 shows the operation when the multiplexed frame or packet multiplexed frame is composed of 16 transmission slots. Therefore, the slot number counter 64 provided inside the slot allocation information generation circuit 91
Is a 4-bit binary counter, and the count value periodically counts from 0 to F (the count value is expressed in hexadecimal in FIG. 18) according to the slot clock signal. Corresponds to the slot number of the transmission slot in one multiplexing group.

The input stream A, the input stream B, and the input stream C are input at different physical speeds. Therefore, as shown in FIG. 18, the transmission time of one TS packet is different. In the example shown in FIG. 18, the physical output ratios of the multiple output speed, the input stream A, the input stream B, and the input stream C are 1/1/2 to 1: 1.
/1.5.

The packet input detection circuit 28a generates a pulse in the input detection signal D1 every time the TS packet to be multiplexed of the input stream A completes input to the buffer memory 21a, and the retiming circuit 51a outputs Figure 1 shows a pulse of the slot clock signal with one cycle time width.
Output at the time point shown in 8.

The same operation is performed on the input streams B and C, and the TS packets to be multiplexed on the input streams B and C are stored in the buffer memories 21b and 21b.
Each time the input to 21c is completed, the retiming circuit 51
From b and 51c, a pulse having a one-cycle time width of the half slot clock signal is output at the time points shown in FIG.

In FIG. 18, for convenience of explanation, the TS packets to be multiplexed are the buffer memories 21a to 21.
The input stream A,
1 in order of input stream B and input stream C
Numbers from 29 to 29 are attached.

The stream number encoder 54 controls the AND gates 53a and 53 under the control of the retiming signal.
Upon receiving the pulse signals that have passed through b and 53c, a stream number (indicated by A, B, and C in FIG. 18, respectively) that is information indicating an input stream assigned to the transmission slot is generated and output to the memory 60.

At the same time, the write address counter 57, which is generating the write address of the memory 60, advances the write address value by one and updates it each time the pulse signal is received. Buffer memory 21a for any input stream
When the TS packet is not input to 21c, the write address counter 57 does not receive the pulse signal, so that the write address value in the memory 60 is not updated.

However, the size comparison circuit 59 compares the count value of the slot number counter 64 and the count values b3 to b0 of the write address count 57 with each other, and the result of FIG.
As shown in, when the count value of the write address counter 57 is smaller, "1" is output. For this reason,
The pulse signal φ4 passes through the AND gate 53d and is given to the write address counter 57, and no matter which input stream A to C the TS packet is not input to the buffer memories 21a to 21c, the writing is performed. The address counter 57 updates the write address value by one.

At the same time, the pulse signal φ4 that has passed through the AND gate 53d is also given to the stream number encoder 54, and the stream number encoder 54 outputs information indicating stuffing (denoted by n in FIG. 18) to the memory 60. .

According to this embodiment, the stream number (output of the stream number encoder 54) is written in the memory 60 at the write address shown in FIG. 18 in this way. Moreover, the address in which the stream number is written is the value indicated by the slot number counter 64 at the time when the TS packets from each input stream have completed input to the buffer memory, that is, the slot of the transmission slot being transmitted at that time. It is clear from the embodiment shown in FIG. 18 that the number corresponds to the slot number immediately following it.

Further, according to this embodiment, when the input detection signals are generated at the same time points for a plurality of input streams, for example, when the count value of the slot number counter 64 is A, the input to the buffer memory is not performed. It is also possible to write the completed TS packets with the numbers B6 and C7 to the addresses (0B, 0C) corresponding to the continuous slot numbers immediately after the completion of the buffer memory input.
More obvious. Further, it is also apparent from FIG. 18 that information (denoted as n) indicating the allocation of the stuffing packet is written in the address corresponding to the slot number in which the TS packet is not allocated.

Further, according to the present embodiment, the number of transmission slots to which the TS packets input for each of the input streams A, B, C are assigned in one multiplexing group is the number of transmission slots per transmitting time of one multiplexing group. The slot numbers indicating the allocation positions are automatically allocated in correspondence with the numbers input to the buffer memories 21a, 21b, and 21c, and the slot numbers at the time when the TS packets to be multiplexed are input to the buffer memories 21a, 21b, and 21c. It corresponds to. This is also clear from FIG.

Further, according to this embodiment, the value of the most significant digit b4 of the write address counter 57 is held by the flip-flop 61 every time the count value of the slot number counter 64 returns from F to 0. The held value is logically inverted and given as the most significant digit of the read address value of the memory 60.

Therefore, as shown in FIG.
From, the slot allocation information for one multiplexing group created during the previous multiplexing group transmission time is read and output. The transmission slot allocation circuit 23, in accordance with the slot allocation information, the buffer memories 21a to 21c,
Alternatively, the TS packet or the null packet is read from the stuffing packet memory 26 one by one, and
As shown in, the data is multiplexed into the corresponding transmission slot and output.

Here, in the present embodiment, as shown in FIG. 18, the delay time of one multiplexing group time is the time until the input TS packet is multiplexed in the transmission slot and transmitted. However, since this delay time is fixed, only the time variation from the time when the TS packet is input to the time when the transmission of the transmission slot having the slot number assigned to the TS packet is started is considered. Should be the delay jitter.

As already described with reference to FIG. 18, in the packet multiplex circuit 20 of the digital multiplex transmission apparatus according to the present embodiment, at the time when the TS packet input to the buffer memories 21a to 21c is detected, the TS packet is detected. The operation of creating the slot allocation information is started, and the transmission slot in which the TS packet is multiplexed is determined. Therefore, the multiplexing delay time of the TS packet to be multiplexed and output is as follows.
It is already determined before the time when it is taken out from 21c and multiplexed in the transmission slot, that is, when the allocation information of the TS packet to the transmission slot is created.

Therefore, in the digital multiplex transmission apparatus of the present invention, the information indicating the time point at which the input of the PCR_PID packet to the buffer memory is detected and the PCR_PID.
The PCR correction amount is generated based on the information indicating the transmission slot to which multiplexing is assigned to the PID packet.

PID filter / conversion circuits 71a to 71c
Then, only TS packets to be multiplexed of each input stream are passed. The PCR packet input detection circuit 81a of the PCR correction amount generation circuit 80 shown in FIG.
Of the TS packets that have passed through the filter / conversion circuit 71a, the input of the PCR_PID packet to the buffer memory 21a is detected, and the PCR detection signal PD1 is output to the correction parameter generation circuit 82a. Similarly, the PCR packet input detection circuit 81b includes a PID filter / conversion circuit 71
Of the TS packets passing through b, the PCR_PID packet is detected to be input to the buffer memory 21b, and the PCR is detected.
The detection signal PD2 is output to the correction parameter generation circuit 82b. The PCR packet input detection circuit 81c detects the input of the PCR_PID packet to the buffer memory 21 among the TS packets that have passed through the PID filter / conversion circuit 71c, and outputs the PCR detection signal PD3 to the correction parameter generation circuit 82c.

Note that the PCR_PID packet is an MPEG
According to the -2 standard, it can be detected by the value of the packet identifier PID, the presence of the adaptation field, the non-zero adaptation field length, and the PCR flag being 1. Of these, the packet identifier PID can be used for detection if it is known, but it can be obtained from the input stream and is designated by the program map table PMT included in the input stream. This program map table P
MT is a table similarly transmitted according to the MPEG-2 standard, and is transmitted by a TS packet having a packet identifier PID designated by the program association table PAT. Here, the program association table PAT is a table transmitted by a TS packet in which a specific value is added to the packet identifier PID in the input stream.

Therefore, a PC for each program to be multiplexed
The value of the packet identifier of the R_PID packet can also be obtained from the input stream. In the PCR packet input detection circuit, by making the value of the packet identifier PID to be detected plural, the PC of any program to be multiplexed
It is also possible to detect the R_PID packet.

Next, referring to FIG. 19 and FIG. 20, PCR
A configuration example and operation of the correction parameter generation circuits 73a to 73c included in the correction amount generation circuit 70 will be described in detail.

In the correction parameter generation circuit of FIG. 19, the counter CT1 is the PCR packet input detection circuit 8
Each time the PCR detection signal is input from 1a to 81c, the counter value is cleared to zero and the count value of the 27 MHz clock counted up to that time is output to the register R1. The register R1 holds the output of the counter CT1 at the rising edge of the half-slot clock signal and outputs it as the parameter signal T1 to the selector 83.

Each time the PCR detection signal is input to the register R2, the logic level of the slot clock signal at the time of input is held, and the held logic level is output to the register R3. The register R3 holds the output of the register R2 at the rising edge of the half-slot clock signal, and outputs it as the parameter signal T2 to the selector 83.

In the register R4, every time the PCR detection signal is input, the slot number counter 6 at the time of the input is input.
The output of 4 (b3 to b0) is held and is output to the register R5. In the register R5, the output of the register R4 is held at the rising edge of the half-slot clock signal and is output to one input terminal X of the subtractor SUB1. The other input terminal Y of the subtracter SUB1 outputs the lower digit of the write address counter 57 (b3 to b0).
Is typing. The subtractor SUB1 subtracts the value given to the input terminal Y from the value given to the input terminal X, and further subtracts 1 from the value (X-Y-1).
Is output to the selector 83 as a parameter signal T3.

In the flip-flop F3, the output value is preset to "1" every time the PCR detection signal is input,
After that, "0" is read at the rising edge of the half slot clock signal and is output to the flip-flop F4 as an output value "0". In the flip-flop F4, the output value "1" from the flip-flop F3 is read at the rising edge of the half slot clock signal and is output to the selector 83 as the correction valid signal VALID.

FIG. 20 is a timing chart representing an operation of the correction parameter generating circuit shown in FIG.

According to FIG. 20, the buffer memories 21a ...
Two PCR_PID packets are continuously input to 21c, and the packet input detection circuits 28a to 28c are
The input detection signal is generated by detecting the input time point of these PCR_PID packets. The input detection signal is converted by the retiming circuit from a rising edge of the half-slot clock signal immediately after that to a signal having a one-cycle time width of the half-slot clock signal.

In the figure, the slot number counter 6
When the output value of 4 becomes k, the value (b3-b0) of the lower bit of the write address counter 57 becomes k. Here, as the pulse signal is applied from the pulse generation circuit 52 to the write address counter 57 through the AND gates 53a to 53c, the write address value output to the memory 60 advances by one. At the same time, the pulse signal that also passed through the AND gates 53a to 53c is also given to the stream number encoder 54, and the stream number encoder 54 outputs the stream numbers corresponding to the AND gates 53a to 53c to which the pulse signals have been input. It is output to the memory 60. Therefore, thereafter, the stream numbers output from the stream number encoder 54 are sequentially written and stored in the addresses k + 1, k + 2, ... Of the memory 60.

That is, in the embodiment shown in FIG.
The D packet (1), that is, the TS packet (1) including the PCR, is assigned to the transmission slot with the slot number k + 1, and the TS packet (2) including the PCR includes the slot. Multiplexing is assigned to the transmission slot numbered k + 2. Here, the transmission slot with the slot number k is the transmission slot that was being transmitted from the transmission slot multiplexing circuit 90 when the TS packet (1) including the PCR was completely input to the buffer memories 21a to 21c. For slot number k +
The transmission slot of 1 is a transmission slot sent from the transmission slot multiplexing circuit 90 immediately after the transmission slot of slot number k. Similarly, the transmission slot of slot number k + 2 is a transmission slot sent from the transmission slot multiplexing circuit 90 immediately after the transmission slot of slot number k + 1.

On the other hand, the PCR packet input detection circuit 81a
To 81c detect that the TS packet input to the buffer memories 21a to 21c is a PCR_PID packet, generate a pulse in the PCR detection signal at the time of completion of the input, and the correction parameter generation circuits 82a to 82 in FIG.
give to c.

The counter CT1 receives the pulse generated in the PCR detection signal, clears the count value to zero, and starts counting the 27 MHz clock signal. The counter value of the counter CT1 is read and held in the register R1 at the rising time of the half slot clock signal, is output from the register R1 as the parameter T1, and is given to the selector 83. Therefore, the parameter T1 indicates the number of cycles of the 27 MHz clock signal from the time when the buffer memory input of the PCR_PID packet is completed to the time when the half-slot clock signal rises immediately thereafter.

The register R2 receives the pulse generated in the PCR detection signal, reads and holds the logic level of the slot clock signal at the time of the pulse generation, and outputs it to the register R3. The register R3 reads and holds the output of the register R2 at the input of the rising edge of the half-slot clock signal and holds it as the parameter T2.
Output to. Therefore, the parameter T2 indicates that when the logic level is "1", the buffer memory input completion time of the PCR_PID packet was in the first half cycle of the slot clock signal, and when it is "0". , PCR_PID packet buffer memory input completion time was in the latter half cycle of the slot clock signal.

The register R4 receives the pulse generated in the PCR detection signal, reads and holds the output value of the slot number counter 64 at the time of the pulse generation, and outputs it to the register R5. The register R5 receives the rising edge of the half-slot clock signal, reads and holds the output of the register R4, and outputs it to the Y input terminal of the subtraction circuit SUB1. An output of the lower 4 bits of the write address counter 57 is given to the X input terminal of the subtraction circuit SUB1, and the subtraction circuit SUB1 performs an XY-1 arithmetic operation and sets the result as a parameter T3. Output to the selector 83.

Therefore, the transmission slot to which multiplexing is assigned to the PCR_PID packet is
It is the same as the slot number of the transmission slot being transmitted from the transmission slot multiplexing circuit 90 at the time when the buffer memory input of the PID packet is completed, and is immediately after the multiplexing group being currently transmitted to the multiplexing group transmitted from the transmission slot multiplexing circuit 90. In the case of the transmission slot to which it belongs (hereinafter, simply referred to as the transmission slot immediately after the completion of the buffer memory input), the value of the parameter T3 becomes “0”. On the other hand, P
If the transmission slot to which multiplexing is assigned to the CR_PID packet is a transmission slot that is further transmitted after the transmission slot immediately after the completion of the buffer memory input, the value of the parameter T3 is set to the buffer memory input completion. The transmission slot immediately after the time point and the PC
The slot difference from the transmission slot to which multiplexing is actually assigned to the R_PID packet is shown.

Therefore, by the parameters T1 and T2 generated by the correction parameter generation circuits 82a to 82c of FIG. 19, the transmission slot of the transmission slot immediately after the completion of the buffer memory input of the PCR_PID packet is completed. Information indicating the time until the start of transmission can be obtained. Also, according to the parameter T3, the PC
From the transmission start time of the transmission slot immediately after the completion of the buffer memory input of the R_PID packet, the PCR_P
Information indicating the time until the transmission start time of the transmission slot to which the multiplexing is actually assigned to the ID packet is obtained. Therefore, information indicating the multiplexing delay time of the PCR_PID packet is obtained by the parameters T1, T2, and T3.

In the flip-flop F3, when a pulse is generated in the PCR detection signal, the output is preset to the logic level "1", and then the logic level "0" is applied to the data input D at the rising time of the half slot clock signal. Is read and the output logic level returns to 0 ',
'0' is output until a pulse is generated again in the PCR detection signal. In the flip-flop F4, the flip-flop F4 is provided at each rising time of the half slot clock signal.
The output of No. 3 is read and output to the selector 83 as the correction valid signal VALID.

Therefore, the correction valid signal VALID is
The logic level becomes "1" for one cycle time of the half slot clock signal immediately after the input of the R_PID packet is completed.

As shown in the timing chart of FIG. 20, in the correction parameter generation circuit of this embodiment, PCR_
The parameter T1, the parameter T2, and the parameter T3, which are the information indicating the multiplexing delay time of the PCR_PID packet, are obtained during one cycle of the half slot clock signal immediately after the PID packet is completely input to the buffer memories 21a to 21c. . Therefore, PCR_PID
Even when packets are continuously input to the buffer memories 21a to 21c and multiplexed and output, the parameters for each PCR_PID packet can be obtained.
Therefore, it is not necessary to change the circuit scale regardless of the number of programs to be multiplexed included in one input stream.

Further, instead of the half slot clock signal, one cycle time is 1 of the slot clock signal.
When a 1 / k slot clock signal that is / k and is synchronized with the slot clock signal is applied, 0 to k-1 are counted at the timing synchronized with the 1 / k slot clock signal for each cycle of the slot clock signal. A counter is provided, and instead of the slot clock signal input to the register R2 in FIG. 19, the count value of this counter may be input, held by the input of the PCR detection signal, and output to the register R3. Thus, as the parameter T2, 1 at the time when the PCR detection signal is generated
A signal indicating the pulse generation position in the / k slot clock signal can be output. Also, FIG. 15 and FIG.
The half slot clock signal used in the embodiment shown in FIG. 1 also uses the 1 / k slot clock signal here.

The selector 83 has a parameter T output from each of the correction parameter generating circuits 73a, 73b, 73c.
1, the parameter T2, the parameter T3, and the correction valid signal VALID are selected according to the outputs of the AND gates 53a to 53c provided inside the slot allocation information generating circuit 49 and output to the parameter memory 84.

That is, when a pulse signal is generated at the output of the AND gate 53a, the correction parameter generating circuit 82a
Output is selected and given to the parameter memory 84,
When a pulse signal is generated at the output of the AND gate 53b, the output of the correction parameter generation circuit 82b is selected and given to the parameter memory 84, and the AND gate 53c is selected.
When the pulse signal is generated at the output of the parameter memory 84, the output of the correction parameter generation circuit 82c is selected and the parameter memory 84
Given to.

However, when the logic level of the selected correction valid signal VALID is "0", the selector 83 replaces all the values of the parameters T1, T2 and T3 with "0" and outputs them to the parameter memory 84. To do. Further, even when no pulse signal is generated at the output of any of the AND gates 53a to 53c, the selector 83
Sets the output values of the parameter T1, the parameter T2, and the parameter T3 to "0", and outputs them to the parameter memory 84.

In the parameter memory 84, the same write address signal (WAH, WAL), the same write enable signal (WE), and the same read address as those of the memory 60 provided inside the slot allocation information generating circuit 91. Signals (RAH, RAL) are input. In the parameter memory 84, the same write address signal (WAH, WAL) and the same write enable signal (W
According to E), the parameter T1, the parameter T2, and the parameter T3 output from the selector 83 are stored, and the same read address signal (R
AH, RAL) according to the stored parameters T1,
Parameter T2 and parameter T3 are data ROM8
5 is output.

The data ROM 85 is a read-only memory (read-only memory), and in the data ROM 85, the parameter T output from the parameter memory 84 is used.
When the address 1, the parameter T2, and the parameter T3 are input to the address, the correction data stored in advance at the address is output, and the output correction data is the PCR correction circuit 9
Given to 2. The value of the correction data stored in the data ROM 85 will be described below.

Of the multiplexing delay times added to the PCR_PID packet that is multiplexed and output, the varying time, that is, the delay jitter is, as described above, the PCR_PID packet from the time when the buffer memory input is completed.
The time until the transmission start time of the transmission slot immediately after the completion of the PID packet buffer memory input, and the P
From the transmission start time of the transmission slot immediately after the completion of the CR_PID packet buffer memory input, the PCR_
It is the total time until the transmission start time of the transmission slot to which multiplexing is actually assigned to the PID packet. The former time can be represented by the following (Equation 1) using the parameters T1 and T2 in units of the number of cycles of the 27 MHz system clock. T1 + T2 × (1 transmission slot time / 2) × 27 × 10 ⁶ (Equation 1)

For the latter time, using the parameter T3,
As a unit of cycle number of 27 MHz system clock,
It can be expressed by the following (Equation 2). T3 × (1 transmission slot time) × 27 × 10 ⁶ (Equation 2)

Therefore, the delay jitters are expressed by (Equation 1) and (Equation 2)
The values of are summed and expressed by the following (formula 3). T1 + {(T2 / 2) + T3} × (1 transmission slot time) × 27 × 10 ⁶ ... (Equation 3)

Here, one transmission slot time can be known from the multiplexing output rate. For example, set the multiplexing speed to 2
When it is set to 9.1621 Mbit / s, the transmission time of one TS packet is 15 bits of the TS packet.
Since it is 04, it is 1504 / 29.1621 × 10
⁶ (seconds) = 51.57379 × 10 ⁻⁶ (seconds) is one transmission slot time. Therefore, in this case, (Equation 3) can be expressed by the following (Equation 4) or (Equation 5). T1 + {(T2 ÷ 2) + T3} × 1393.249 (Equation 4) or T1 + {(T2 ÷ 2) + T3} × 1504 × (27 ÷ 29.1621) (Equation 5)

Further, in this embodiment, when the correction parameter generating circuits 82a to 82c obtain the parameter T1,
The counter CT1 counts the 27 MHz clock signal, but instead of the 27 MHz clock signal, a clock of the above-described multiplexed output speed (frequency 29.162 MH) is used.
z) can also be used. In this case, T1 is 27M
When the number of cycles of the system clock of Hz is converted as a unit, it is T1 × (27 ÷ 29.1621),
Substituting T1 in (Equation 5), the delay jitter is expressed by the following (Equation 6). [T1 + {(T2 ÷ 2) + T3} × 1504] × (27 ÷ 29.1621) ... (Equation 6)

The actual PCR field is PCR_ba.
se and PCR_ext, and PCR_ba
se is represented by 33 bits, and PCR_ext is represented by 9 bits. The resolution of PCR_ext is 27M
Hz and takes a value in the range of 0 to 299. PCR_
base is the upper digit, and the value of PCR_ext is 299.
The value advances by one when returning from 0 to 0. Therefore, PCR_ba
The resolution of se is 90 kHz.

Therefore, the value of (Equation 6) is rounded off after the decimal point and divided by 300 to obtain the quotient and the remainder. The quotient is represented by a 33-bit binary number, and the remainder is represented by a 9-bit binary number. The data thus obtained is stored in advance in the data ROM 85 as correction data.

As described above, the delay jitter added to the PCR_PID packet is calculated by the parameters T1, T2,
And the parameter T3. When a plurality of output speeds are used as the multiplexed output speed, the data calculated by (Equation 6) is stored in a plurality of sets of data ROMs.
It may be stored in advance in 85 and used by switching according to the input address according to the multiplexed output speed.

In the data ROM 85, the parameter T1,
The parameters T2 and T3 are given as input addresses. When a plurality of output speeds are used as the multiplexed output speed, an input address in which a bit indicating the multiplexed output speed is further attached to a bit different from the parameter T1, the parameter T2, and the parameter T3 is stored in the data ROM 85. Given. Correction data corresponding to the input address value is output from the data ROM 85 and given to the PCR correction circuit 92.

The PCR correction circuit 92 is the PC of the PCR_PID packet output from the transmission slot multiplexing circuit 90.
The correction data is arithmetically added to the R field and output. At this time, the PCR_ext portion is added in the 300-ary system, and when a carry occurs, 1 is added to the PCR_base portion. For the TS packets other than the PCR_PID packet, the parameters T1, T2, and T3 are "0", and the data RO is used as the input address.
Since it is given to M76, as shown in (Equation 6), P
The correction data is “0” for correcting CR_base and PCR_ext. Therefore, the TS packets other than the PCR_PID packet are output from the PCR correction circuit 92 without changing their contents.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it is obvious that each embodiment can be appropriately modified within the scope of the technical idea of the present invention.

[0484]

As is apparent from the above description, according to the present invention, since a multiplexed frame is formed according to the transmission rate of each of a plurality of input digital streams, the plurality of digital streams can be flexibly changed. It is possible to multiplex efficiently and with high quality.

That is, when assigning a plurality of digital streams to each transmission slot of a multiplexed frame, the time when the input from each digital stream reaches a certain amount is detected, and each digital signal generated according to this detected time is detected. Since the multiplexing frame is configured by allocating each digital stream to each transmission slot based on the slot allocation information for the stream, the multiplexing efficiency can be increased.

Further, by transmitting the multiplexed frame to which the slot allocation information is added by the digital multiplex transmission apparatus and method of the present invention, the receiving side can change the multiplexed frame from the multiplexed frame by the slot allocation information added to the multiplexed frame. Based on the basic configuration of separating digital streams, it is not necessary to set transmission slots in advance for each digital stream or to input and specify transmission slot setting information from the outside, and digital multiplex transmission with little delay jitter. Can be provided.

That is, according to the digital multiplex transmission apparatus and method of the present invention, every time when the input data amount from the digital stream reaches the data amount transmitted in one transmission slot, the transmission corresponding to that time point is performed. Each time a packet is allocated and stored, and in the case of a digital stream in the form of a packet, each time one packet for transmitting valid information excluding the stuffing packet is input, the transmission slot corresponding to the input point The number of transmission slots to be assigned to each digital stream is automatically determined with respect to the digital information rate of each digital stream for each multiplexed frame.

Therefore, it is not necessary to set a transmission slot for each digital stream in advance or input information for setting a transmission slot from the outside.

Information indicating the allocation of the digital stream to the transmission slot is multiplexed and transmitted in the multiplexed frame. Therefore, the receiving side can separate the desired digital stream from the multiplexed frame based on the information indicating the allocation. Further, it is not necessary to specify the transmission slot in advance for each digital stream.

Further, when the digital information rate of the digital stream is changed at any time by changing the video coding parameters, changing the number of audio channels, switching programs, etc., the difference between the physical transmission rate of the digital stream and the digital information transmission rate. For example, in the case of a transport stream, is input by being supplemented with a null packet that is a stuffing packet. However, in the present invention, since allocation is performed for a packet that transmits effective information,
Multiple digital streams are efficiently multiplexed.

Also, the transmission slot allocation is performed at the time when the amount of input data from the digital stream reaches the amount of data transmitted in one transmission slot or the time when a packet for transmitting effective information is input. There is.

In particular, in the case of a packet-type digital stream, the packet is assigned to the transmission slot corresponding to the input time of the packet and stored, and the packet input for transmitting effective information in any digital stream is input. If the number of slots allocated up to that time is less than the number of slots transmitted up to that time, the stuffing packet is allocated with a transmission slot and stored, and this stuffing packet stores this transmission in the next multiplexed frame. Information indicating slot allocation is read out, and a packet or stuffing packet for transmitting effective information of each digital stream is multiplexed in the transmission slot.

Therefore, the delay time from the input of a packet to the multiplexing and output of the transmission slot is always approximately one multiplexing frame time for any packet forming any digital stream. Become. Therefore, the delay time jitter is small.

[0494] Also, the time when the amount of input data from the digital stream reaches the amount of data transmitted in one transmission slot or the time when a packet for transmitting effective information is input is the same in two or more digital streams. Even in such a case, the transmission slots are continuously assigned to the respective digital streams.
Therefore, the delay time jitter is small.

Further, the total number of packets for transmitting effective information input from each digital stream within the time of one cycle of the multiplexed frame is such that the number of transmission slots of the multiplexed frame is temporarily changed due to short-term fluctuation of the digital information transmission rate. Even if the number of packets is excessively exceeded, the excess number of packets is put into the transmission slot of the subsequent multiplexed frame and transmitted. Therefore, the average speed that can be multiplexed with respect to a digital stream whose digital information speed fluctuates can be increased, and the multiplexing efficiency is high.

Further, according to the present invention, PCR_values of a plurality of PID values to be multiplexed in one input stream.
Even when the PID packet exists, the delay jitter can be corrected without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a digital multiplex transmission system using a digital multiplex transmission device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a configuration of a multiplexed frame according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of a slot allocation information field in the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of a slot allocation information generation circuit in the embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the pulse generator provided in the slot allocation information generating circuit in the embodiment of the present invention.

FIG. 6 is a diagram showing a configuration example of a retiming circuit provided inside a slot allocation information generation circuit according to the embodiment of the present invention.

FIG. 7 is a timing chart showing an operation of the retiming circuit according to the exemplary embodiment of the present invention.

FIG. 8 is a block diagram showing a schematic configuration of a digital multiplex transmission system using a digital multiplex transmission device according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a schematic configuration of a digital multiplex transmission system using a digital multiplex transmission device according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a configuration example of a packet multiplex frame of the digital multiplex transmission system in the second and third embodiments of the present invention.

FIG. 11 is a diagram showing a configuration example of a multiplexing information packet of a packet multiplexing frame in the second and third embodiments of the present invention.

FIG. 12 is a timing chart showing an operation example in the first embodiment and the second embodiment of the present invention.

FIG. 13 is a timing chart showing an operation example according to the third embodiment of the present invention.

FIG. 14 is a block diagram showing a schematic configuration of a digital multiplex transmission device according to a fourth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration example of a slot allocation information generation circuit of a digital multiplex transmission device according to a fourth embodiment of the present invention.

FIG. 16 is a timing chart showing an operation of a pulse generation circuit provided in the slot allocation information generation circuit according to the fourth embodiment of the present invention.

FIG. 17 is a timing chart showing an operation of the retiming circuit according to the fourth exemplary embodiment of the present invention.

FIG. 18 is a timing chart showing the operation of the digital multiplex apparatus of the digital multiplex transmission apparatus according to the fourth embodiment of the present invention.

FIG. 19 is a diagram showing an example of the configuration of a correction parameter generation circuit provided inside a PCR correction amount generation circuit of a digital multiplex transmission device according to a fourth embodiment of the present invention.

FIG. 20 is a timing chart showing the operation of the correction parameter generation circuit according to the fourth embodiment of the present invention.

FIG. 21 is a block diagram showing a configuration example of a digital multiplex transmission device in a conventional technique.

FIG. 22 is a block diagram showing another configuration example of a digital multiplex transmission device in the related art.

[Explanation of symbols]

20 digital multiplex transmission equipment 21a, 21b, 21c buffer memory 22 stuffing data memory 23 transmission slot allocation circuit 24 multiplex frame generation circuits 25a, 25b, 25c data amount measuring circuit 26 stuffing memory 27 packet multiplex frame generation circuit 28 packet input detection circuit 29a, 29b, 29c Stuffing packet removal circuit 30 Transmission line 40 Receiver 41 Frame synchronization circuit 42 Transmission slot selection circuit 43 Slot allocation information separation circuit 44a, 44b, 44c Stuffing packet insertion circuit 45 Frame synchronization circuit 50, 91 Slot allocation information generation Circuits 51a, 51b, 51c Retiming circuit 52 Pulse generators 53a, 53b, 53c, 53d AND gate 54 Stream number encoders 55, 56 Logic Gate 57 Write address counter 58 Logical product gate 59 Size comparison circuit 60 Memory 61 Flip-flops 62, 63 Logical inversion gate 64 Slot number counters 71a, 71b, 71c PID filter / conversion circuits 81a, 81b, 81c PCR packet input detection circuit 82a , 82b, 82c correction parameter generation circuit 83 selector 84 parameter memory 85 data ROM 90 transmission slot multiplexing circuit 92 PCR correction circuit 93 PSI insertion circuit 94 PSI memory

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H04N 7/08 H04N 7/08 Z 7/081 7/13 Z 7/24 (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 3/16 H04J 3/00 H04J 3/06 H04J 3/22 H04J 7/08 H04N 7/08 H04N 7/081 H04N 7/24

Claims (183)

(57) [Claims] 1. A digital multiplex transmission apparatus that multiplexes a plurality of digital streams into respective transmission slots of a multiplexed frame and transmits the multiplexed data according to the transmission rate of each digital stream. and slot allocation information generating means for generating allocation information for each transmission slot, the each digital stream, the digital input
The amount of data that can be transmitted in one transmission slot is reached
The digital data amount detecting means for detecting the
However , the slot allocation information generating means detects the time point by the digital data amount detecting means.
Slot allocation information of the digital stream
Generates and multiplexes the respective digital stream in accordance with the generated slot allocation information, by adding the slot allocation information in the multiplexing frame, the digital multiplex transmission apparatus characterized by transmitting to the receiving side. Wherein said slot allocation information, the digital multiplex transmission apparatus according to claim 1, wherein the generating on the basis of the detected time. 3. The slot allocation information generating means generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot in which the time point is detected by the digital data amount detecting means. 3. The digital multiplex transmission device according to claim 2, wherein: 4. The slot allocation information generating means, when the digital data amount detecting means does not detect the time point for any of the digital streams within one cycle of the transmission slot, the multiplexing is performed. In the frame one cycle, the number of the slot allocation information generated by the transmission slot one cycle in which the time point is not detected is transmitted by the transmission slot one cycle in which the time point is not detected 4. The digital multiplex transmission apparatus according to claim 2 or 3 , wherein when the number of slots is smaller than the number of slots, allocation information of stuffing data is generated for a transmission slot immediately after. 5. The slot allocation information generating means, when the digital data amount detecting means detects the time points for a plurality of the digital streams within one cycle of the transmission slot, the slot allocation information generating means is provided immediately after the transmission slot. generating the slot allocation information for successive same number of the transmission slot from claim 2, wherein 4
5. The digital multiplex transmission device according to any one of 1. 6. The digital signal for which the time point has been detected by the digital data amount detection means within one cycle of the transmission slot immediately before the transmission slot for which the slot allocation information has been generated, the slot allocation information of the stream, immediately after the slot allocation information is already generated the transmission slot, any one of claims 2 to 5, the slot allocation information and generates to the transmission slot uncreated The digital multiplex transmission device described in 1. 7. The slot allocation information generating means, when the slot allocation information for each transmission slot for one cycle of the multiplexed frame is generated, further within the one cycle of the multiplexed frame, the digital stream. when the time is detected for, according to claim 2, characterized in that to generate the allocation information of the digital stream for transmission slot of a multiplexing frame 6 immediately after the multiplex frame Digital multiplex transmission equipment. 8. The slot allocation information generating means does not generate the slot allocation information for a transmission slot for transmitting the slot allocation information among the transmission slots constituting the multiplexed frame. The digital multiplex transmission device according to any one of claims 2 to 7 , which is characterized in that. 9. A digital multiplex transmission apparatus for multiplexing and transmitting a plurality of digital streams in each transmission slot of a multiplexed frame, detecting that the input digital data has reached a predetermined amount for each digital stream, Data amount detecting means for outputting a detection signal for each of the detected digital streams; retiming means for retiming and outputting each detection signal with a clock signal synchronized with the transmission slot cycle; The pulse generation means for generating a plurality of pulse signals having different phases for each cycle, and the passage of each pulse signal corresponding to the digital stream among the plurality of pulse signals by the pulse generation means are retimed. Each of the digital stripes is controlled by inputting a detection signal. And a slot allocation for generating allocation information for the transmission slot of the digital stream corresponding to the pulse signal passing through the first pulse signal passage control means. Information generating means, write address value setting means for advancing and setting a write address value by one each time the slot allocation information is generated, and counting the number of transmission slots transmitted in one cycle of the multiplexing frame. And a lower write address value in the write address value having the same digit as the count value by the transmission slot count means and the count value, and as a result of the comparison, the lower address When the value is smaller than the count value, the magnitude comparison means for outputting a true value and the pulse generation means generate the value. Second pulse signal passage control means for controlling passage of one pulse signal other than the pulse signal corresponding to the digital stream by inputting the true value, and the second pulse signal passage The slot allocation information generating means for generating allocation information of the stuffing data for the transmission slot by the input of the pulse signal which has passed through the control means, and the write address value of 1 each time the slot allocation information is generated. And a write address value setting means for setting the write address value to generate a signal indicating that the lower write address value in the write address value has reached a value equal to the number of transmission slots of the one multiplexing frame. Means and the write address value setting means for further advancing and setting the write address value by one each time the signal is generated. Storage means for storing and holding the slot allocation information for the transmission slots of the digital stream and the stuffing data at an address corresponding to the write address value set by the write address value setting means; Holding the write address value set when the allocation information of the transmission slot for the one multiplexed frame is stored by the storage means in one cycle of the conversion frame, An assignment information reading unit for reading and outputting the slot assignment information stored at the address of the storage unit, and multiplexing the digital streams and the stuffing data according to the slot assignment information read by the assignment information reading unit. And adds the slot allocation information to the multiplexed frame, Digital multiplex transmission apparatus characterized by transmitting the signal side. 10. The digital multiplex transmission device according to claim 9 , wherein the predetermined amount is the amount of data transmitted in the one transmission slot. 11. The method of claim, characterized in that the range of the write address value setting the write address values set in section, and with twice the number of transmission slots of the one multiplexing frame 9 Or the digital multiplex transmission device according to item 10 . 12. A digital multiplex transmission apparatus for multiplexing a plurality of packet format digital streams in respective transmission slots of a multiplexed frame and transmitting the packets, the packets forming the respective digital streams according to the transmission rate of the respective digital streams. and slot assignment information generating unit operable to generate the allocation information for each transmission slot, the each digital stream, is inputted packet
When the number of packets transmitted in one transmission slot is reached
Packet count detecting means for detecting, and the slot allocation information generating means is configured to detect the time point by the packet count detecting means.
Generates the slot allocation information of the digital stream
Then , the digital multiplex transmission apparatus is characterized in that the digital streams are multiplexed in accordance with the generated slot allocation information, the slot allocation information is added to the multiplexed frame, and the multiplexed frame is transmitted to the receiving side. 13. The method of claim 1, characterized in that the slot assignment information, generated based on the time when the detected
2. The digital multiplex transmission device as described in 2 . 14. The slot allocation information generating means generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot in which the time point is detected by the packet number detecting means. 14. The digital multiplex transmission device according to claim 13 . 15. The slot allocation information generating means, when the packet number detecting means does not detect the time point for any of the digital streams within one cycle of the transmission slot, the multiplexed frame. In one cycle, the number of the slot allocation information generated up to one cycle of the transmission slot in which the time point was not detected, the transmission slot transmitted in one cycle of the transmission slot in which the time point was not detected When the number is smaller than the number, allocation information of the stuffing packet for the transmission slot immediately after is generated.
13. The digital multiplex transmission device according to 13 or 14 . 16. The slot allocation information generating means, when the packet number detecting means detects the time points for a plurality of the digital streams within one cycle of the transmission slot, the consecutive number immediately after the transmission slot. 16. The digital multiplex transmission apparatus according to claim 13, wherein the slot allocation information for the same number of the transmission slots is generated. 17. The digital stream for which the packet number detection means has detected the time point within one cycle of the transmission slot immediately before the transmission slot for which the slot allocation information has been generated, of the slot allocation information, immediately after the slot allocation information is already generated the transmission slots in any of claims 13 16 of the slot allocation information and generates to the transmission slot uncreated The described digital multiplex transmission device. 18. The slot allocation information generating means, when the slot allocation information for each transmission slot for one cycle of the multiplexing frame is generated, further within the one cycle of the multiplexing frame, the digital stream. when the time is detected for, according to any one of claims 13 to 17, and generates the allocation information of the digital stream for transmission slot of the multiplexed frame immediately after the multiplex frame Digital multiplex transmission equipment. 19. The slot allocation information generating means does not generate the slot allocation information for a transmission slot that transmits the slot allocation information among the transmission slots that form the multiplexed frame. The digital multiplex transmission device according to any one of claims 13 to 18 , which is characterized in that. 20. A digital multiplex transmission device for multiplexing and transmitting a plurality of packet-format digital streams in respective transmission slots of a multiplexed frame, detecting that the number of input packets has reached a predetermined amount for each digital stream. A packet number detecting means for outputting a detection signal for each of the detected digital streams; a retiming means for retiming and outputting each detection signal with a clock signal synchronized with the transmission slot cycle; Pulse regenerating means for generating a plurality of pulse signals having different phases for each cycle of the signal; and retiming the passage of each of the pulse signals corresponding to the digital stream among the plurality of pulse signals by the pulse generating means. The digital signals controlled by the input of the detected signal. Pulse signal passage control means provided for each stream, and a slot for generating allocation information for the transmission slot of the digital stream corresponding to the pulse signal passed through the first pulse signal passage control means. Allocation information generating means, a write address value setting means for advancing and setting a write address value by one each time the slot allocation information is generated, and a transmission number of the transmission slot in one cycle of the multiplexed frame. The transmission slot counting means for counting, the lower write address value in the write address value having the same digit as the count value by the transmission slot count means, and the count value are compared, and as a result of the comparison, the lower When the address value is smaller than the count value, the magnitude comparison means for outputting a true value, and the pulse generation means Second pulse signal passage control means for controlling passage of one pulse signal other than the pulse signal corresponding to the digital stream among the plurality of generated pulse signals by inputting the true value; and the second pulse. The slot allocation information generating means for generating allocation information for the transmission slot of the stuffing packet by the input of the pulse signal having passed through the signal passing control means, and the write address value for each generation of the slot allocation information. And a write address value setting means for setting the write address value, and a signal indicating that the lower write address value in the write address value has reached a value equal to the number of transmission slots of the one multiplexed frame. Generating means, and the write address for advancing and setting the write address value by one each time the signal is generated. Value setting means, and storage means for storing and holding the slot allocation information for the transmission slots of the digital stream and the stuffing packet at an address corresponding to the write address value set by the write address value setting means. And further, holding the write address value set when the storage slot allocation information for one multiplexing frame is stored by the storage means during one cycle of the multiplexing frame, An allocation information reading means for reading and outputting the slot allocation information stored at the address of the storage means indicated by the embedded address value, each digital stream according to the slot allocation information read by the allocation information reading means. Of the packet and the stuffing packet of the By adding a packet containing the slot allocation information beam, the digital multiplex transmission apparatus characterized by transmitting to the receiving side. 21. The method of claim, characterized in that the predetermined amount, and the amount of data transmitted by the first transmission slot 20
The described digital multiplex transmission device. Claims the scope of the claims 22, wherein said write address value setting the write address values set in section, characterized in that twice the said number of transmission slots of the one multiplexing frame 20 Alternatively, the digital multiplex transmission device according to 21 . 23. A digital multiplex transmission apparatus for multiplexing and transmitting a plurality of packet-format digital streams in respective transmission slots of a multiplexing frame, and stuffing packet removing means for removing a stuffing packet included in each digital stream; Slot allocation information generation for generating allocation information for each transmission slot of the effective packet forming each digital stream according to the transmission rate of the effective packet of each digital stream from which the stuffing packet has been removed by the stuffing packet removal means. Means for multiplexing the digital streams according to the generated slot allocation information, adding the slot allocation information to the multiplexed frame, and transmitting the multiplexed frame to the receiving side. Tal multiplex transmission equipment. 24. The digital multiplex transmission apparatus further comprises valid packet number detection means for detecting a time point at which the valid packets that have been input have reached a predetermined number for each of the digital streams, and the slot allocation information generation 24. The digital multiplex transmission apparatus according to claim 23 , wherein the means generates the slot allocation information of the digital stream, the time point of which is detected by the valid packet number detection means. 25. The digital multiplex transmission apparatus according to claim 24 , wherein the predetermined number is the number of valid packets transmitted in the one transmission slot. The method according to claim 26, wherein the slot allocation information, and generating, based on the detected time claims 2
4. The digital multiplex transmission device according to 4 or 25 . 27. The slot allocation information generating means generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot in which the time point is detected by the packet number detecting means. 27. The digital multiplex transmission device according to claim 26 . 28. The slot allocation information generating means, when the effective packet number detecting means does not detect the time point of any of the digital streams within one cycle of the transmission slot, the multiplexing is performed. If the number of the slot allocation information generated within the one cycle of the transmission slot in which the time point is not detected is less than the number of the transmission slots transmitted up to that time in the one cycle of the frame, the immediately following transmission is performed. 28. The digital multiplex transmission apparatus according to claim 26 , wherein allocation information of stuffing packets for slots is generated. 29. The slot allocation information generating means, when the valid packet number detecting means detects the time points for a plurality of the digital streams within one cycle of the transmission slot, immediately after the transmission slot. claims 26, characterized in that generating the slot allocation information for successive same number of the transmission slot 28
5. The digital multiplex transmission device according to any one of 1. 30. The slot allocation information generating means is characterized in that, in the one cycle immediately preceding the transmission slot of the transmission slot for which the slot allocation information has been generated, the valid packet number detecting means detects the time point. the slot allocation information of the stream, immediately after the slot allocation information is already generated the transmission slot, claim 26, slot assignment information and generating relative to the transmission slot of the uncreated 29 The digital multiplex transmission device described in 1. 31. The slot allocation information generating means, when the slot allocation information for each transmission slot for one cycle of the multiplexed frame is generated, further within the one cycle of the multiplexed frame, the digital stream. when the time is detected for, according to claim 26, characterized in that to generate the allocation information of the digital stream for transmission slot of the multiplexed frame 30 immediately after the multiplex frame Digital multiplex transmission equipment. 32. The slot allocation information generating means does not generate the slot allocation information for a transmission slot for transmitting the slot allocation information among the transmission slots forming the multiplexed frame. The digital multiplex transmission device according to any one of claims 26 to 31 , which is characterized in that. 33. A digital multiplex transmission device for multiplexing and transmitting a plurality of packet format digital streams in respective transmission slots of a multiplexing frame, and stuffing packet removing means for removing a stuffing packet included in each digital stream, Valid packet number detecting means for detecting that a predetermined number of valid packets of each digital stream from which the stuffing packet has been removed by the stuffing packet removing means are input, and outputting a detection signal for each detected digital stream; Retiming means for retiming and outputting each detection signal with a clock signal synchronized with the transmission slot cycle; and pulse generating means for generating a plurality of pulse signals having different phases for each cycle of the clock signal. Of the plurality of pulse signals generated by the pulse generating means, the passage of each pulse signal corresponding to the digital stream is controlled by the input of the retimed detection signal. Pulse signal passage control means, slot assignment information generation means for generating assignment information for the transmission slots of the digital stream corresponding to the pulse signal passed through the first pulse signal passage control means, and the slot assignment Write address value setting means for advancing and setting the write address value by one each time information is generated; transmission slot counting means for counting the number of transmission slots transmitted in one cycle of the multiplexing frame; The lower part of the write address value of the same digit as the count value by the transmission slot counting means Comparing the write address value with the count value, and as a result of the comparison, if the lower address value is a value smaller than the count value, a magnitude comparing means for outputting a true value, and the pulse generation. Second pulse signal passage control means for controlling passage of one pulse signal other than the pulse signal corresponding to the digital stream among the plurality of pulse signals generated from the means by the input of the true value; Slot allocation information generating means for generating allocation information for the transmission slot of the stuffing packet by inputting the pulse signal which has passed through the pulse signal passing control means, and for each time the slot allocation information is generated, the writing information is further written. The write address value setting means for advancing and setting the address value by one, and the lower write address in the write address value. Means for generating a signal indicating that the value has reached a value equal to the number of transmission slots of the one multiplexing frame; and, each time the signal is generated, the write address value is further advanced by 1 and set. Write address value setting means, and the slot allocation information for the transmission slot of the digital stream and the stuffing packet is stored and held in an address corresponding to the write address value set by the write address value setting means. Storage means, further holding the write address value set when the allocation information of the transmission slot for the one multiplexed frame is stored by the storage means in one cycle of the multiplexed frame, Assignment information for reading and outputting the slot assignment information stored at the address of the storage means indicated by the write address value A packet including the slot allocation information in the multiplexed frame, wherein the effective packet and the stuffing packet of each digital stream are multiplexed according to the slot allocation information read by the allocation information reading unit. A digital multiplex transmission device, characterized in that it is added to and transmitted to the receiving side. 34. The digital multiplex transmission apparatus according to claim 33 , wherein the predetermined number is the number of valid packets transmitted in the one transmission slot. 35. Claim 33, characterized in that the range of the write address value setting the write address values set in section, and with twice the number of transmission slots of the one multiplexing frame Or the digital multiplex transmission device described in 34 . 36. A digital multiplex transmission method for multiplexing a plurality of digital streams into respective transmission slots of a multiplexed frame and transmitting the multiplexed data, the digital data forming the respective digital streams according to the transmission rate of the respective digital streams. wherein the slot allocation information generating step of generating allocation information for each transmission slot, the each digital stream, the digital input
The amount of data that can be transmitted in one transmission slot is reached
The digital data amount detection process to detect the
However , in the slot allocation information generating step, the time point is detected in the digital data amount detecting step.
Slot allocation information of the digital stream
Generates and multiplexes the respective digital stream in accordance with the generated slot allocation information, by adding the slot allocation information in the multiplexing frame, the digital multiplex transmission method characterized by transmitting to the receiving side. 37. The claim 3, characterized in that the slot assignment information, generated based on the time when the detected
6. The digital multiplex transmission method described in 6 . 38. The slot allocation information generating step generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot in which the time point is detected in the digital data amount detecting step. 38. The digital multiplex transmission method according to claim 37, wherein: 39. The slot allocation information generating step, in the digital data amount detecting step, when the time point is not detected for any of the digital streams within one cycle of the transmission slot, the multiplexing is performed. If the number of the slot allocation information generated within the one cycle of the transmission slot in which the time point is not detected is less than the number of the transmission slots transmitted up to that time in the one cycle of the frame, the immediately following transmission is performed. 39. The digital multiplex transmission method according to claim 37 , wherein allocation information of stuffing data is generated for slots. 40. The slot allocation information generating step, when the digital data amount detecting step detects the time points of a plurality of the digital streams within one cycle of the transmission slot, the step immediately after the transmission slot is performed. claims 37, characterized in that generating the slot allocation information for successive same number of the transmission slot
39. The digital multiplex transmission method according to any one of 39 . 41. In the slot allocation information generating step, the digital data amount detecting means detects the time point within one cycle of the transmission slot immediately before the transmission slot for which the slot allocation information has been generated. the slot allocation information of the stream, immediately after the slot allocation information is already generated the transmission slot, any of claims 37 40 of the slot allocation information and generates to the transmission slot uncreated The digital multiplex transmission method described in. 42. In the slot allocation information generating step, when the slot allocation information for each transmission slot of one cycle of the multiplexing frame is generated, the digital stream is further generated within one cycle of the multiplexing frame. when the time is detected for, according to claim 37, characterized in that to generate the allocation information of the digital stream for transmission slot of the multiplexed frame 41 immediately after the multiplex frame Digital multiplex transmission method. 43. The slot allocation information generating step includes not generating the slot allocation information for a transmission slot transmitting the slot allocation information among the transmission slots forming the multiplexed frame. 43. A digital multiplex transmission method according to any one of claims 37 to 42 . 44. A digital multiplex transmission method for multiplexing and transmitting a plurality of digital streams in respective transmission slots of a multiplexed frame, detecting that the input digital data has reached a predetermined amount for each digital stream, A data amount detecting step of outputting a detection signal for each of the detected digital streams; a retiming step of retiming and outputting each detection signal with a clock signal synchronized with the transmission slot cycle; The pulse generation step of generating a plurality of pulse signals having different phases for each cycle, and the passage of each pulse signal corresponding to the digital stream among the plurality of pulse signals by the pulse generation step is retimed. Each of the digital streams is controlled by inputting a detection signal. A first pulse signal passage control step provided for each frame, and a slot for generating allocation information for the transmission slot of the digital stream corresponding to the pulse signal passed through the first pulse signal passage control step. An allocation information generating step; a write address value setting step of advancing and setting a write address value by 1 each time the slot allocation information is generated; and a number of transmission slots to be transmitted in one cycle of the multiplexed frame. The transmission slot counting step for counting, the lower write address value in the write address value of the same digit as the count value by the transmission slot counting step, and the count value are compared, and as a result of the comparison, the lower If the address value is smaller than the count value, a true / small value comparison step of outputting a true value and the pulse generation step are performed. A second pulse signal passage control step of controlling passage of one pulse signal other than the pulse signal corresponding to the digital stream among the plurality of pulse signals by inputting the true value; The slot allocation information generating step of generating allocation information of the stuffing data for the transmission slot by the input of the pulse signal which has passed through the control step, and the write address value is further set to 1 each time the slot allocation information is generated. And a write address value setting step of setting the write address value, and generating a signal indicating that the lower write address value in the write address value has reached a value equal to the number of transmission slots of the one multiplexing frame. And a step of setting the write address value by advancing the write address value by one each time the signal is generated. A storage step of storing and holding the slot allocation information for the transmission slots of the digital stream and the stuffing data at an address corresponding to the write address value set by the write address value setting step, Holds the write address value set when the allocation information of the transmission slot for the one multiplexed frame is stored in the storage step during one cycle of the multiplexed frame, and indicates the write address value An assignment information reading step of reading and outputting the slot assignment information stored at the address of the storage step, wherein each of the digital streams and the stuffing data are read according to the slot assignment information read in the assignment information reading step. Multiplexing and adding the slot allocation information to the multiplexed frame Digital multiplex transmission method characterized by transmitting to the receiving side. 45. A claim 44, characterized in that the predetermined amount, and the amount of data transmitted by the first transmission slot
The described digital multiplex transmission method. 46. A claim 44, characterized in that the range of the write address value setting the write address values set in step was twice of the number of transmission slots of the one multiplexing frame Or the digital multiplex transmission method described in 45 . 47. A digital multiplex transmission method for multiplexing a plurality of packet-format digital streams into respective transmission slots of a multiplexed frame and transmitting the packets, the packets forming the respective digital streams according to a transmission rate of the respective digital streams. and slot allocation information generating step of said generating the allocation information for each transmission slot, the each digital stream, is inputted packet
When the number of packets transmitted in one transmission slot is reached
And a packet number detecting step of detecting the packet number, wherein in the slot allocation information generating step, the time point is detected in the packet number detecting step.
Generates the slot allocation information of the digital stream
Then , the digital stream is multiplexed according to the generated slot allocation information, the slot allocation information is added to the multiplexed frame, and the multiplexed frame is transmitted to the receiving side. 48. A claim 4, characterized in that the slot assignment information, generated based on the time when the detected
7. The digital multiplex transmission method described in 7 . 49. The slot allocation information generating step, in the packet number detecting step, generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot in which the time point is detected. 49. The digital multiplex transmission method according to claim 48 . 50. In the slot allocation information generating step, when the time point is not detected for any of the digital streams within one cycle of the transmission slot in the packet number detecting step, the multiplexed frame is detected. In one cycle, the number of the slot allocation information generated up to one cycle of the transmission slot in which the time point was not detected, the transmission slot transmitted in one cycle of the transmission slot in which the time point was not detected When the number is smaller than the number, allocation information of the stuffing packet for the transmission slot immediately after is generated.
48. A digital multiplex transmission method as described in 48 or 49 . 51. The slot allocation information generating step, in the packet number detecting step, when the time points of a plurality of the digital streams are detected within one cycle of the transmission slot, the consecutive immediately after the transmission slot. The digital multiplex transmission method according to any one of claims 48 to 50 , characterized in that the slot allocation information for the same number of the transmission slots is generated. 52. In the slot allocation information generating step, the digital stream in which the time point is detected in the packet number detecting step within one cycle of the transmission slot immediately before the transmission slot in which the slot allocation information has been generated. of the slot allocation information, immediately after the slot allocation information is already generated the transmission slot, in any one of claims 48 to 51 in which the slot allocation information and generates to the transmission slot uncreated The described digital multiplex transmission method. 53. In the slot allocation information generating step, when the slot allocation information for each transmission slot for one cycle of the multiplexed frame is generated, the digital stream is further included in one cycle of the multiplexed frame. 53. The allocation information of the digital stream is generated for a transmission slot of a multiplexed frame immediately after the multiplexed frame when the time point is detected with respect to. Digital multiplex transmission method. 54. The slot allocation information generating step does not generate the slot allocation information for a transmission slot that transmits the slot allocation information among the transmission slots forming the multiplex frame. The digital multiplex transmission method according to any one of claims 48 to 53 . 55. A digital multiplex transmission method for multiplexing a plurality of packet-format digital streams into respective transmission slots of a multiplexed frame for transmission, and detecting that the number of input packets reaches a predetermined number for each digital stream. A packet number detection step of outputting a detection signal for each of the detected digital streams; a retiming step of retiming and outputting each detection signal with a clock signal synchronized with the transmission slot cycle; A pulse generating step of generating a plurality of pulse signals having different phases for each cycle of the signal, and the passage of each pulse signal corresponding to the digital stream among the plurality of pulse signals by the pulse generating step is retimed. The digital signals controlled by the input of the detected signal. A first pulse signal passage control step provided for each stream, and a slot for generating allocation information for the transmission slot of the digital stream corresponding to the pulse signal passed through the first pulse signal passage control step. An allocation information generating step; a write address value setting step of advancing and setting a write address value by 1 each time the slot allocation information is generated; and a number of transmission slots to be transmitted in one cycle of the multiplexed frame. The transmission slot counting step for counting, the lower write address value in the write address value of the same digit as the count value by the transmission slot counting step, and the count value are compared, and as a result of the comparison, the lower If the address value is smaller than the count value, the magnitude comparison step of outputting a true value, and the pulse generation step A second pulse signal passage control step of controlling passage of one pulse signal other than the pulse signal corresponding to the digital stream among the plurality of generated pulse signals by inputting the true value; and the second pulse. The slot allocation information generating step of generating allocation information for the transmission slot of the stuffing packet by the input of the pulse signal that has passed through the signal passing control step, and the write address value for each generation of the slot allocation information. And the write address value setting step of setting the write address value by one, and a signal indicating that the lower write address value in the write address value has reached a value equal to the number of transmission slots of the one multiplexing frame. And a step of generating the write address for advancing and setting the write address value by one each time the signal is generated. Value setting step, and a storage step of storing and holding the slot allocation information for the transmission slots of the digital stream and the stuffing packet at an address corresponding to the write address value set in the write address value setting step. And holding the write address value that was set when the transmission slot allocation information for the one multiplexed frame was stored by the storage step during one cycle of the multiplexed frame. An assignment information reading step of reading and outputting the slot assignment information stored at the address of the storage step indicated by a value, the slot assignment information being read in the assignment information reading step, Packet and the stuffing packet are multiplexed, and the multiplexed frame is preceded by Digital multiplex transmission method characterized by by adding packet including slot assignment information is transmitted to the receiving side. 56. A claim, characterized in that the predetermined number, and the number of packets transmitted by the first transmission slot 5
5. The digital multiplex transmission method described in 5 . 57. The range of the write address value set in the write address value setting step is set to be twice the number of the transmission slots of the one multiplexed frame . Or the digital multiplex transmission method described in 56 . 58. A digital multiplex transmission method for multiplexing and transmitting a plurality of packet-format digital streams in respective transmission slots of a multiplexed frame, the stuffing packet removing step of removing a stuffing packet included in each digital stream; Slot allocation information generation for generating allocation information for each of the transmission slots of the valid packets forming the digital streams according to the transmission rate of the valid packets of the digital streams from which the stuffing packets have been removed by the stuffing packet removal step. And a step of multiplexing the digital streams according to the generated slot allocation information, adding the slot allocation information to the multiplexed frame, and transmitting the multiplexed frame to the receiving side. Tal multiplex transmission method. 59. The digital multiplex transmission method further comprises a valid packet number detecting step of detecting a time point when the valid packets that have been input have reached a predetermined number for each of the digital streams. 59. The digital multiplex transmission method according to claim 58 , wherein in the step, the slot allocation information of the digital stream of which the time point is detected in the effective packet number detection step is generated. 60. The digital multiplex transmission method according to claim 59 , wherein the predetermined number is the number of valid packets transmitted in the one transmission slot. 61. claim 5 the slot allocation information, and generating, based on the detected time
The digital multiplex transmission method described in 9 or 60 . 62. The slot allocation information generating step generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot in which the time point is detected in the valid packet number detecting step. The digital multiplex transmission method according to claim 61 , characterized in that: 63. The slot allocation information generating step, when the time point is not detected for any of the digital streams in one cycle of the transmission slot in the valid packet number detecting step, the multiplexing is performed. If the number of slot allocation information generated up to that time within one frame period is smaller than the number of transmission slots transmitted up to that time, the allocation information of the stuffing packet for the next transmission slot is generated. 63. The digital multiplex transmission method according to claim 61 or 62 . 64. In the slot allocation information generating step, when the time point is detected for a plurality of the digital streams within one cycle of the transmission slot in the valid packet number detecting step, immediately after the transmission slot. claims 61, characterized in that generating the slot allocation information for successive same number of the transmission slot 63
The digital multiplex transmission method according to any one of 1. 65. In the slot allocation information generating step, the digital signal for which the time point is detected by the valid packet number detecting means within one cycle of the transmission slot immediately before the transmission slot for which the slot allocation information has been generated. the slot allocation information of the stream, immediately after the slot allocation information is already generated the transmission slot, claim 61, characterized in that the slot allocation information is generated for the transmission slot of the uncreated 64 The digital multiplex transmission method described in. 66. In the slot allocation information generating step, when the slot allocation information is generated for each transmission slot for one cycle of the multiplexed frame, the digital stream is further included in one cycle of the multiplexed frame. when the time is detected for, according to any one of claims 61 to 65, characterized in that to generate the allocation information of the digital stream for transmission slot of the multiplexed frame immediately after the multiplex frame Digital multiplex transmission method. 67. The slot allocation information generating step does not generate the slot allocation information for a transmission slot for transmitting the slot allocation information among the transmission slots forming the multiplex frame. 67. The digital multiplex transmission method according to claim 61 . 68. A digital multiplex transmission method for multiplexing a plurality of packet-type digital streams in respective transmission slots of a multiplexed frame and transmitting the multiplexed stuffing packets, the stuffing packet removing step of removing stuffing packets included in each digital stream, A valid packet number detection step of detecting that a predetermined number of valid packets of each digital stream from which the stuffing packet has been removed by the stuffing packet removal step have been input, and outputting a detection signal for each of the detected digital streams; A retiming step of retiming and outputting each detection signal with a clock signal synchronized with the transmission slot cycle; and a pulse generating step of generating a plurality of pulse signals having different phases for each cycle of the clock signal. A first provided for each digital stream for controlling passage of each pulse signal corresponding to the digital stream among the plurality of pulse signals generated by the pulse generation step by inputting the retimed detection signal. Pulse signal passing control step, slot allocation information generating step for generating allocation information for the transmission slot of the digital stream corresponding to the pulse signal passed through the first pulse signal passing control step, and the slot allocation A write address value setting step of advancing and setting a write address value by one each time information is generated; a transmission slot counting step of counting the number of transmission slots transmitted in one cycle of the multiplexing frame; In the write address value of the same digit as the count value in the transmission slot counting step, Comparing the write address value with the count value, and as a result of the comparison, if the lower address value is a value smaller than the count value, a magnitude comparing step of outputting a true value; A second pulse signal passage control step of controlling passage of one pulse signal other than the pulse signal corresponding to the digital stream among a plurality of pulse signals generated from the step by the input of the true value; The slot allocation information generating step of generating allocation information for the transmission slot of the stuffing packet by inputting the pulse signal that has passed through the pulse signal passing control step, and the writing operation is performed each time the slot allocation information is generated. The write address value setting step of advancing and setting the address value by one, and the lower write address in the write address value. Generating a signal indicating that the value has reached a value equal to the number of transmission slots of the one multiplexed frame; and advancing and setting the write address value by one each time the signal is generated. A write address value setting step, and the slot allocation information for the transmission slot of the digital stream and the stuffing packet is stored and held in an address corresponding to the write address value set in the write address value setting step. A storing step, holding the write address value set when the transmission slot allocation information for one multiplexing frame during one cycle of the multiplexing frame is stored by the storing step, and Allocation information reading step of reading and outputting the slot allocation information stored at the address of the storage step indicated by the embedded address value According to the slot allocation information read in the allocation information reading step, the effective packet and the stuffing packet of each digital stream are multiplexed, and a packet including the slot allocation information is added to the multiplexed frame. Then, the digital multiplex transmission method is characterized in that it is transmitted to the receiving side. 69. The digital multiplex transmission method according to claim 68 , wherein the predetermined number is the number of valid packets transmitted in the one transmission slot. Wherein 70] according to claim 68, characterized in that the range of the write address value setting the write address values set in step was twice of the number of transmission slots of the one multiplexing frame Or the digital multiplex transmission method described in 69 . 71. A digital multiplex transmission apparatus for multiplexing a plurality of digital streams into respective transmission slots of a multiplexed frame and transmitting the multiplexed data, the digital data constituting the respective digital streams corresponding to the transmission rate of the respective digital streams. Slot allocation information generating means for generating allocation information for each transmission slot , and an input digital signal for each digital stream.
The amount of data that can be transmitted in one transmission slot is reached
Digital data amount detecting means for detecting a time point, have a multiplexing means for multiplexing the respective digital stream in accordance with the generated slot allocation information, the slot allocation information generating means, the digital data amount detecting means And the time point is detected
Slot allocation information of the digital stream
And the generated slot allocation information to the multiplexed
The digital streams are multiplexed by the digitizing means.
A digital multiplex transmission device characterized in that it is added to a multiplexed frame and transmitted. 72. The digital multiplex transmission apparatus according to claim 71 , wherein said slot allocation information generating means generates said slot allocation information based on said detected time point. 73. The slot allocation information generating means generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot in which the time point is detected by the digital data amount detecting means. 73. The digital multiplex transmission device according to claim 72, wherein 74. When the digital data amount detecting means detects the time points for a plurality of the digital streams within one cycle of the transmission slot, the slot allocation information generating means, continuously immediately after, with respect to the digital data amount detecting said time point detected by means of the same number of the transmission slot, according to any of claims 71 73, characterized in that to generate said slot assignment information Digital multiplex transmission equipment. 75. When the digital data amount detecting means does not detect the time point of any one of the digital streams within one cycle of the transmission slot, the slot allocation information generating means determines the transmission slot. 75. The digital multiplex transmission device according to any one of claims 71 to 74 , wherein stuffing data allocation information is generated for a transmission slot immediately after. 76. When the digital data amount detecting means does not detect any one of the digital streams at the time point within one cycle of the transmission slot, and within one cycle of the multiplexing frame. , The number of the slot allocation information generated within the one cycle of the transmission slot in which the time point is not detected is smaller than the number of the transmission slots transmitted in the one cycle of the transmission slot in which the time point is not detected 76. The digital multiplex transmission apparatus according to claim 75 , wherein in said case, said slot allocation information generating means generates stuffing data allocation information for a transmission slot immediately after said transmission slot. 77. The slot allocation information for the transmission slot immediately after the transmission slot when the time point is detected by the digital data amount detecting means within one cycle of the transmission slot. Is generated, the slot allocation information generating means is configured to generate the digital stream for which the time point is detected for the transmission slot immediately after the transmission slot for which the slot allocation information has not been generated. 77. The digital multiplex transmission apparatus according to claim 71 , wherein said slot allocation information is generated. 78. The slot allocation information generating means,
When the slot allocation information for each transmission slot for one cycle of the multiplexed frame has already been generated, and within one cycle of the multiplexed frame, the digital data amount detecting means, Furthermore, when the time point is detected for the digital stream, the slot allocation information generation means generates allocation information of the digital stream for a transmission slot of a multiplexed frame immediately after the multiplexed frame. The digital multiplex transmission device according to any one of claims 71 to 77 , characterized in that. 79. When the digital data amount detecting means detects the time point a plurality of times for each of the one digital stream or a plurality of digital streams within one cycle of one transmission slot, the slot allocation is performed. The information generating means generates the slot allocation information for the same number of the transmission slots immediately after the transmission slot as the number of the transmission slots detected by the digital stream amount detecting means. The digital multiplex transmission apparatus according to any one of 71 to 78 . 80. The slot allocation information generating means does not generate the slot allocation information for a transmission slot for transmitting the slot allocation information among the transmission slots forming the multiplexed frame. 80. The digital multiplex transmission device according to any one of claims 71 to 79 . 81. A digital multiplex transmission device for multiplexing a plurality of digital streams of a plurality of packet formats into respective transmission slots of a multiplexed frame and transmitting the multiplexed digital streams according to the transmission rate of each digital stream. and slot allocation information generating means for generating allocation information for each transmission slot of the packet constituting a multiplexing means for multiplexing the respective digital stream in accordance with the generated slot allocation information, the each digital stream, and input The package
The number of packets transmitted in the one transmission slot
And a packet number detecting means for detecting a time when the reached, the slot allocation information generating means, wherein said time point is detected by the packet number detecting means
Generates the slot allocation information of the digital stream
A digital multiplex transmission device characterized by the following. 82. A digital multiplex transmission apparatus for multiplexing and transmitting a plurality of digital streams of a plurality of packet formats in each transmission slot of a multiplexing frame, and a stuffing packet removing means for removing a stuffing packet included in each digital stream. Slot allocation information for generating allocation information for each transmission slot of a packet included in each digital stream according to a transmission rate of the packet of each digital stream after the stuffing packet is removed by the stuffing packet removing means A digital multiplex transmission apparatus comprising: a generation unit and a multiplexing unit that multiplexes the digital streams in accordance with the generated slot allocation information. 83. The slot allocation information generated by the slot allocation information generating means is added to a multiplexed frame in which the digital streams are multiplexed by the multiplexing means, and the multiplexed frame is transmitted. Item 81
82 is a digital multiplex transmission apparatus. 84. The digital multiplex transmission apparatus according to claim 81 , wherein said slot allocation information generating means generates said slot allocation information based on said detected time point. 85. The slot allocation information generating means generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot in which the time point is detected by the packet number detecting means. 85. The digital multiplex transmission device according to claim 84 . 86. When the packet number detecting means detects the time points for a plurality of the digital streams within one cycle of the transmission slot, the slot allocation information generating means immediately after the transmission slot. 86. The digital signal according to claim 81 , wherein the slot allocation information is generated for the same number of the transmission slots as the time point detected by the packet number detection means, which is consecutive to Multiplexer. 87. When the time point of any of the digital streams is not detected in one cycle of the transmission slot by the packet number detecting means, and in one cycle of the multiplexed frame, When the number of the slot allocation information generated within the one cycle of the transmission slot in which the time point is not detected is smaller than the number of transmission slots in the one cycle of the transmission slot in which the time point is not detected 87. The digital multiplex transmission apparatus according to claim 86 , wherein said slot allocation information generation means generates stuffing packet allocation information for a transmission slot immediately after said transmission slot. 88. A digital multiplex transmission system in which a transmitter multiplexes a plurality of digital streams into respective transmission slots of a multiplexed frame and transmits the multiplexed frame to a receiver, wherein the transmitter comprises each of the digital streams. Slot allocation information generating means for generating allocation information for each transmission slot of digital data forming each digital stream according to each transmission rate; and multiplexing each digital stream according to the generated slot allocation information. Multiplexing means and the input digital for each digital stream
Data reaches the amount of data transmitted in the one transmission slot.
A digital data amount detecting means for detecting the time when it reaches, and the digit generated by the slot allocation information generating means.
The time data is detected by the total data amount detecting means.
The slot allocation information of the digital stream is added to the multiplexed frame in which the digital streams are multiplexed by the multiplexing means, and is transmitted, and the receiving device is configured to receive the multiplexed signal. A digital multiplex transmission system, wherein the desired digital stream is extracted from the multiplexed frame and output based on the slot allocation information added to the frame. 89. The receiving device separates the slot allocation information from the multiplexed frame, and a digital signal of the desired digital stream from the multiplexed frame based on the separated slot allocation information. 89. The digital multiplex transmission system according to claim 88, further comprising output means for selecting the transmission slot in which data is multiplexed and outputting the selected digital data. 90. The digital multiplex transmission system according to claim 88 , wherein said slot allocation information generating means generates said slot allocation information based on said detected time point. 91. The slot allocation information generating means generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot in which the time point is detected by the digital data amount detecting means. 91. The digital multiplex transmission system according to claim 90 . 92. When the digital data amount detecting means detects the time points for a plurality of the digital streams within one cycle of the transmission slot, the slot allocation information generating means, continuously immediately after, for the detected said time point as many of the transmission slot in the digital data amount detecting means, according to any one of claims 88 to 91, characterized in that to generate said slot assignment information Digital multiplex transmission system. 93. When the digital data amount detecting means does not detect the time point of any of the digital streams within one cycle of the transmission slot, the slot allocation information generating means determines the transmission slot. 93. The digital multiplex transmission system according to claim 88 , wherein allocation information of stuffing data is generated for a transmission slot immediately after. 94. When the digital data amount detecting means does not detect any one of the digital streams at the time point within one cycle of the transmission slot, and within one cycle of the multiplexing frame. , The number of the slot allocation information generated within the one cycle of the transmission slot in which the time point is not detected is smaller than the number of the transmission slots transmitted in the one cycle of the transmission slot in which the time point is not detected in case, the slot allocation information generating means, said transmission digital multiplex transmission system according to claim 93, wherein the generating the allocation information of stuffing data to the transmission slot immediately following the slot. 95. The slot allocation information for the transmission slot immediately following the transmission slot when the time point is detected by the digital data amount detecting means within one cycle of the transmission slot. Is generated, the slot allocation information generating means is configured to generate the digital stream for which the time point is detected for the transmission slot immediately after the transmission slot for which the slot allocation information has not been generated. 95. The digital multiplex transmission system according to claim 88 , wherein said slot allocation information is generated. 96. The slot allocation information generating means,
When the slot allocation information for each transmission slot for one cycle of the multiplexed frame has already been generated, and within one cycle of the multiplexed frame, the digital data amount detecting means, Furthermore, when the time point is detected for the digital stream, the slot allocation information generation means generates allocation information of the digital stream for a transmission slot of a multiplexed frame immediately after the multiplexed frame. 96. The digital multiplex transmission system according to any one of claims 88 to 95 , wherein: 97. When the digital data amount detecting means detects the time point a plurality of times for each of the one digital stream or each of the plurality of digital streams within one period of one transmission slot, the slot The allocation information generating means generates the slot allocation information for the same number of the transmission slots immediately following the transmission slot as the number of the transmission slots detected by the digital stream amount detecting means. The digital multiplex transmission system according to any one of Items 88 to 96 . 98. The slot allocation information generating means does not generate the slot allocation information for a transmission slot for transmitting the slot allocation information among the transmission slots forming the multiplexed frame. 98. A digital multiplex transmission system according to any one of claims 88 to 97 . 99. In a digital multiplex transmission system for multiplexing a plurality of digital streams of a plurality of packet formats into respective transmission slots of a multiplexed frame by a transmitter and transmitting the multiplexed frame to a receiver, the transmitter is Slot allocation information generating means for generating allocation information for each transmission slot of a packet forming each digital stream according to a transmission rate of each digital stream; and each digital stream according to the generated slot allocation information. And the input packet for each digital stream.
The number of packets transmitted in the one transmission slot has been reached
Packet count detection means for detecting a time point, and the packet generated by the slot allocation information generation means.
The digital signal whose time point has been detected by the
The slot allocation information of the stream is added to the multiplexed frame in which the digital streams are multiplexed by the multiplexing unit, and is transmitted, and the receiving device is configured to receive the multiplexed frame. A digital multiplex transmission system, wherein the desired digital stream is extracted from the multiplexed frame and output based on the slot allocation information added to the. 100. A digital multiplex transmission system in which a transmitter multiplexes a plurality of digital streams of a plurality of packet formats into respective transmission slots of a multiplexed frame, and the multiplexed frame is transmitted to a receiver. A stuffing packet removing means for removing a stuffing packet included in each digital stream, and a stuffing packet included in each digital stream according to a transmission rate of a packet of the digital stream from which the stuffing packet has been removed by the stuffing packet removing means. Slot allocation information generating means for generating allocation information for each transmission slot of the packet to be transmitted, multiplexing means for multiplexing each digital stream according to the generated slot allocation information, and the slot allocation information The slot allocation information generated by the composing means is added to the multiplexed frame in which the respective digital streams are multiplexed by the multiplexing means, and is transmitted, and the receiving device receives the slot allocation information. A digital multiplex transmission system, wherein the desired digital stream is extracted from the multiplexed frame and output based on the slot allocation information added to the multiplexed frame. 101. The receiving device includes a separating unit that separates the slot allocation information from the multiplexed frame, and a packet of the desired digital stream from the multiplexed frame based on the separated slot allocation information. , The transmission slot in which the
101. The digital multiplex transmission system according to claim 99 or 100, further comprising: output means for outputting the selected digital data. 102. The receiving device further outputs digital data from the output means based on the slot allocation information separated by the separation means,
The digital multiplex transmission system according to claim 101 , further comprising means for multiplexing stuffing packets. 103. The digital multiplex transmission system according to claim 99 , wherein said slot allocation information generating means generates said slot allocation information based on said detected time point. 104. The slot allocation information generation means generates allocation information of a corresponding digital stream for a transmission slot immediately after the transmission slot in which the time point is detected by the packet number detection means. 104. The digital multiplex transmission system according to claim 103 . 105. When the packet number detecting means detects the time points for a plurality of the digital streams in one cycle of the transmission slot, the slot allocation information generating means immediately after the transmission slot. 105. The digital signal according to claim 102 , wherein the slot allocation information is generated for the same number of the transmission slots as the time point detected by the packet number detecting means, which is consecutive to Multiplex transmission system. 106. When the packet number detecting means does not detect any one of the digital streams at the time point within the one cycle of the transmission slot, the slot allocation information generating means, 106. The digital multiplex transmission system according to claim 102 , wherein allocation information of a stuffing packet is generated for a transmission slot immediately after. 107. When the packet number detecting means does not detect any of the digital streams at the time point within one cycle of the transmission slot, and within one cycle of the multiplexed frame, When the number of the slot allocation information generated within the one cycle of the transmission slot in which the time point is not detected is smaller than the number of transmission slots in the one cycle of the transmission slot in which the time point is not detected 107. The digital multiplex transmission system according to claim 106 , wherein said slot allocation information generating means generates stuffing packet allocation information for a transmission slot immediately after said transmission slot. 108. The slot allocation information for the transmission slot immediately after the transmission slot when the time point is detected by the packet number detection means within one cycle of the transmission slot, In the case where it has already been generated, the slot allocation information generating means, for the transmission slot immediately after the transmission slot, in which the slot allocation information has not been generated, of the digital stream of which the time point has been detected. 108. The digital multiplex transmission system according to claim 102, wherein the slot allocation information is generated. 109. When the slot allocation information generating means has already generated the slot allocation information for each transmission slot for one cycle of the multiplexed frame, and the multiplexed frame In one cycle, when the packet number detecting means further detects the time point of the digital stream, the slot allocation information generating means transmits the multiplexed frame immediately after the multiplexed frame. The digital multiplex transmission system according to any one of claims 102 to 108 , wherein allocation information of the digital stream is generated for a slot. 110. In one cycle of one transmission slot, when the packet number detecting means detects the time point a plurality of times for each of the one digital stream or each of the plurality of digital streams, the slot allocation is performed. The information generation means generates the slot allocation information for any one of the transmission slots immediately following the transmission slot and having the same number as the time point detected by the packet number detection means. The digital multiplex transmission system according to claim 102 . 111. The slot allocation information generating means does not generate the slot allocation information for a transmission slot that transmits the slot allocation information among the transmission slots forming the multiplexed frame. The digital multiplex transmission system according to any one of claims 99 to 110 . 112. A digital multiplex transmission method for multiplexing a plurality of digital streams in respective transmission slots of a multiplexed frame and transmitting the multiplexed data, wherein the digital data forming each of the digital streams is dependent on the transmission rate of each of the digital streams. A slot allocation information generating step of generating allocation information for each transmission slot , and an input digital signal for each digital stream.
Data reaches the amount of data transmitted in the one transmission slot.
And the digital data amount detection process to detect the time when it reaches
In the slot allocation information generating step, the time point is detected in the digital data amount detecting step.
Slot allocation information of the digital stream
And a multiplexing step of multiplexing each of the digital streams in accordance with the generated slot allocation information. 113. The slot allocation information generated in the slot allocation information generating step is added to a multiplexed frame in which the digital streams are multiplexed in the multiplexing step and transmitted. Item 11
2. The digital multiplex transmission method described in 2 . 114. The digital multiplex transmission method according to claim 112 , wherein in said slot allocation information generating step, said slot allocation information is generated based on said detected time point. 115. In the slot allocation information generating step, corresponding digital stream allocation information is generated for a transmission slot immediately after the transmission slot in which the time point is detected in the digital data amount detecting step. The digital multiplex transmission method according to claim 114, wherein: 116. In the digital data amount detecting step, when the time points of a plurality of the digital streams are detected within one cycle of the transmission slot, the transmission slot is generated in the slot allocation information generating step. continuously immediately after, with respect to the digital data amount detecting said time point detected in step with the same number of the transmission slot, in any one of claims 112 to 115, characterized in that to generate said slot assignment information The described digital multiplex transmission method. 117. When, in the digital data amount detecting step, the time point is not detected for any one of the digital streams within one cycle of the transmission slot, the transmission is performed in the slot allocation information generating step. 117. The digital multiplex transmission method according to claim 112 , wherein allocation information of stuffing data is generated for a transmission slot immediately after the slot. 118. In the digital data amount detecting step, when the time point is not detected for any of the digital streams within one cycle of the transmission slot, and within one cycle of the multiplexing frame. , The number of the slot allocation information generated within the one cycle of the transmission slot in which the time point is not detected is smaller than the number of the transmission slots transmitted in the one cycle of the transmission slot in which the time point is not detected 118. The digital multiplex transmission method according to claim 117 , wherein in the case, in the slot allocation information generating step, stuffing data allocation information is generated for a transmission slot immediately after the transmission slot. 119. The slot allocation information for the transmission slot immediately after the transmission slot when the time point is detected in the digital data amount detecting step within one cycle of the transmission slot. In the case where the slot allocation information is generated, in the slot allocation information generating step, the digital signal for which the time point has been detected is transmitted to the transmission slot immediately after the transmission slot for which the slot allocation information has not been generated. The digital multiplex transmission method according to any one of claims 112 to 118 , characterized in that the slot allocation information of a stream is generated. 120. When the slot allocation information generating step has already generated the slot allocation information for each transmission slot for one cycle of the multiplexing frame, and the multiplexing frame Within one cycle, in the digital data amount detecting step,
When the time point is detected for the digital stream, in the slot allocation information generating step, allocation information of the digital stream is generated for a transmission slot of a multiplexed frame immediately after the multiplexed frame. 120. The digital multiplex transmission method according to any one of claims 112 to 119 . 121. When the digital data amount detecting step detects the time point a plurality of times for each of the one digital stream or each of the plurality of digital streams in one cycle of one transmission slot, the slot In the allocation information generating step, the slot allocation information is generated for the same number of the transmission slots immediately following the transmission slot as the number of the transmission slots detected in the digital stream amount detecting step. The digital multiplex transmission method according to any one of claims 112 to 120 . 122. In the slot allocation information generating step, the slot allocation information is not generated for a transmission slot transmitting the slot allocation information among the transmission slots forming the multiplexed frame. The digital multiplex transmission method according to any one of claims 112 to 121 . 123. A digital multiplex transmission method for multiplexing a plurality of digital streams of a plurality of packet formats into respective transmission slots of a multiplexed frame and transmitting the multiplexed digital streams according to the transmission rate of each digital stream. A slot allocation information generating step of generating allocation information for each of the transmission slots of the constituent packets, and the input packet for each digital stream.
The number of packets transmitted in the one transmission slot
The packet number detection step of detecting the arrival time and the packet number generated in the slot allocation information generation step.
The digit whose time point was detected in the step number detection step
Digital multiplex transmission method characterized in that it comprises a multiplexing step of multiplexing the respective digital stream in accordance with the slot allocation information Le stream. 124. A digital multiplex transmission method for multiplexing and transmitting a plurality of digital streams of a plurality of packet formats in respective transmission slots of a multiplexed frame, the stuffing packet removing step of removing a stuffing packet contained in each digital stream. Slot allocation information for generating allocation information for each transmission slot of a packet included in each digital stream according to a packet transmission rate of each digital stream after the stuffing packet is removed by the stuffing packet removal step A digital multiplex transmission method comprising: a generating step; and a multiplexing step of multiplexing the respective digital streams according to the generated slot allocation information. 125. The slot allocation information generated in the slot allocation information generating step is added to a multiplexed frame in which the respective digital streams are multiplexed in the multiplexing step and transmitted. Item 12
3. The digital multiplex transmission method according to 3 or 124 . 126. The digital multiplex transmission method according to claim 123 , wherein said slot allocation information generating step generates said slot allocation information based on said detected time point. 127. In the slot allocation information generating step, the corresponding digital stream allocation information is generated for a transmission slot immediately after the transmission slot in which the time point is detected in the packet number detecting step. 127. The digital multiplex transmission method according to claim 126, wherein: 128. In the packet number detecting step, when the time points are detected for a plurality of the digital streams within one cycle of the transmission slot, the slot allocation information generating step includes continuously immediately after, for the detected said time point as many of the transmission slot in the packet number detecting step, according to any one of claims 123 to 127, characterized in that to generate said slot assignment information Digital multiplex transmission method. 129. In the packet number detecting step, when the time point is not detected for any of the digital streams within one cycle of the transmission slot, the transmission slot is generated in the slot allocation information generating step. 129. The digital multiplex transmission method according to claim 123, wherein the allocation information of the stuffing packet is generated for the transmission slot immediately after. 130. In the packet number detection step, when the time point is not detected for any of the digital streams within one cycle of the transmission slot, and within one cycle of the multiplexed frame, When the number of the slot allocation information generated within the one cycle of the transmission slot in which the time point is not detected is smaller than the number of transmission slots in the one cycle of the transmission slot in which the time point is not detected 130. The digital multiplex transmission method according to claim 129 , wherein in the slot allocation information generating step, stuffing packet allocation information is generated for a transmission slot immediately after the transmission slot. 131. A transmitter multiplexes a plurality of digital streams into respective transmission slots of a multiplexed frame,
In the digital multiplex transmission method for transmitting the multiplexed frame to a receiving device, the transmitting device assigns allocation information for each transmission slot of digital data forming each digital stream according to a transmission rate of each digital stream. Slot allocation information generating step, a multiplexing step of multiplexing the digital streams according to the generated slot allocation information , and an input digital signal for each digital stream.
Data reaches the amount of data transmitted in the one transmission slot.
And the digital data amount detection process to detect the time when it reaches
The slot allocation information generating step,
When the time point is detected in the digital data amount detection step
Said slot assignment information of the digital stream, and a delivery step in which the respective digital stream is transmitted in addition to the multiplexed frames are multiplexed by the multiplexing process, the receiver, the multiplexed received A digital multiplex transmission method, wherein the desired digital stream is extracted from the multiplexed frame and output based on the slot allocation information added to the frame. 132. The receiving device includes a separating step of separating the slot allocation information from the multiplexed frame, and a digital signal of the desired digital stream from the multiplexed frame based on the separated slot allocation information. 132. A digital multiplex transmission method according to claim 131, further comprising: selecting the transmission slot in which data is multiplexed and outputting the selected digital data. 133. The digital multiplex transmission method according to claim 131 , wherein in said slot allocation information generating step, said slot allocation information is generated based on said detected time point. 134. In the slot allocation information generating step, corresponding digital stream allocation information is generated for a transmission slot immediately after the transmission slot in which the time point is detected in the digital data amount detecting step. 133. The digital multiplex transmission method according to claim 133, wherein: 135. In the digital data amount detecting step, when the time points are detected for a plurality of the digital streams within one cycle of the transmission slot, the transmission slot is generated in the slot allocation information generating step. 134. The slot allocation information is generated for the same number of the transmission slots as the time point detected in the digital data amount detecting step, which is continuous immediately after. The described digital multiplex transmission method. 136. In the digital data amount detecting step, when the time point is not detected for any of the digital streams within one cycle of the transmission slot, the transmission is performed in the slot allocation information generating step. The digital multiplex transmission method according to any one of claims 131 to 135 , characterized in that stuffing data allocation information is generated for a transmission slot immediately after the slot. 137. In the digital data amount detecting step, when the time point is not detected in any one of the digital streams within one cycle of the transmission slot, and within one cycle of the multiplexing frame. , The number of the slot allocation information generated within the one cycle of the transmission slot in which the time point is not detected is smaller than the number of the transmission slots transmitted in the one cycle of the transmission slot in which the time point is not detected 138. The digital multiplex transmission method according to claim 136 , wherein in the case, in the slot allocation information generating step, allocation information of stuffing data is generated for a transmission slot immediately after the transmission slot. 138. The slot allocation information for the transmission slot immediately after the transmission slot when the time point is detected in the digital data amount detecting step within one cycle of the transmission slot. In the case where the slot allocation information is generated, in the slot allocation information generating step, the digital signal for which the time point has been detected is transmitted to the transmission slot immediately after the transmission slot for which the slot allocation information has not been generated. 138. The digital multiplex transmission method according to any one of claims 131 to 137 , wherein the slot allocation information of a stream is generated. 139. When the slot allocation information generating step has already generated the slot allocation information for each transmission slot of one cycle of the multiplexing frame, and the multiplexing frame Within one cycle, in the digital data amount detecting step,
When the time point is detected for the digital stream, in the slot allocation information generating step, allocation information of the digital stream is generated for a transmission slot of a multiplexed frame immediately after the multiplexed frame. 139. The digital multiplex transmission method according to any one of claims 131 to 138 . 140. In one cycle of one transmission slot, when the digital data amount detecting step detects the time point a plurality of times for each of the one digital stream or each of the plurality of digital streams, the slot In the allocation information generating step, the slot allocation information is generated for the same number of the transmission slots immediately following the transmission slot as the number of the transmission slots detected in the digital stream amount detecting step. The digital multiplex transmission method according to any one of claims 131 to 139 . 141. In the slot allocation information generating step, the slot allocation information is not generated for a transmission slot that transmits the slot allocation information among the transmission slots that configure the multiplexed frame. 141. The digital multiplex transmission method according to claim 131 . 142. In a digital multiplex transmission method of multiplexing a plurality of digital streams of a plurality of packet formats in respective transmission slots of a multiplexed frame in a transmitter and transmitting the multiplexed frame to a receiver, the transmitter comprises A slot allocation information generating step of generating allocation information for the respective transmission slots of packets forming the digital streams according to the transmission rate of each digital stream; and the digital streams according to the generated slot allocation information. And the input packet for each digital stream.
The number of packets transmitted in the one transmission slot has been reached
The packet number detection step of detecting the time point is performed, and the packet generated in the slot allocation information generation step is
The digit whose time point was detected in the step number detection step
A step of adding the slot allocation information of the digital stream to the multiplexed frame in which the digital streams are multiplexed by the multiplexing step and transmitting the added information. A digital multiplex transmission method, wherein the desired digital stream is extracted from the multiplexed frame and output based on the slot allocation information added to the frame. 143. In a digital multiplex transmission method of multiplexing a plurality of digital streams of a plurality of packet formats in respective transmission slots of a multiplexed frame in a transmitter and transmitting the multiplexed frame to a receiver, the transmitter comprises A stuffing packet removing step of removing a stuffing packet included in each digital stream, and a stuffing packet included in each digital stream according to a packet transmission rate of each digital stream from which the stuffing packet is removed by the stuffing packet removing step. Slot allocation information generating step for generating allocation information for each transmission slot of the packet to be transmitted, multiplexing step for multiplexing each digital stream in accordance with the generated slot allocation information, and slot allocation information generating step The slot allocation information generated in the step of adding the slot allocation information to the multiplexed frame in which the digital streams are multiplexed by the multiplexing step, and transmitting the added information. A digital multiplex transmission method, wherein the desired digital stream is extracted from the multiplexed frame and output based on the slot allocation information added to the multiplexed frame. 144. The receiving device separates the slot allocation information from the multiplexed frame, and a packet of the desired digital stream from the multiplexed frame based on the separated slot allocation information. , The transmission slot in which the
The digital multiplex transmission method according to claim 142 or 143 , further comprising an output step of outputting the selected digital data. 145. The receiving device further outputs digital data from the output step based on the slot allocation information separated in the separating step.
145. The digital multiplex transmission method according to claim 144 , further comprising the step of multiplexing stuffing packets. 146. The digital multiplex transmission method according to claim 142 , wherein in said slot allocation information generating step, said slot allocation information is generated based on said detected time point. 147. In the slot allocation information generating step, in the packet number detecting step, allocation information of a corresponding digital stream is generated for a transmission slot immediately after the transmission slot in which the time point is detected. 147. The digital multiplex transmission method according to claim 146 . 148. In the packet number detecting step, when the time points of a plurality of the digital streams are detected within one cycle of the transmission slot, the slot allocation information generating step includes 146. The slot allocation information is generated for the same number of the transmission slots as the time point detected in the packet number detecting step, which is continuous immediately thereafter. 145 . Digital multiplex transmission method. 149. In the packet number detecting step, when the time point is not detected for any of the digital streams within one cycle of the transmission slot, the transmission slot is generated in the slot allocation information generating step. 149. The digital multiplex transmission method according to any one of claims 145 to 148 , characterized in that allocation information of a stuffing packet is generated for a transmission slot immediately after the. 150. When, in the packet number detecting step, the time point is not detected for any of the digital streams within one cycle of the transmission slot, and within one cycle of the multiplexing frame, When the number of the slot allocation information generated within the one cycle of the transmission slot in which the time point is not detected is smaller than the number of transmission slots in the one cycle of the transmission slot in which the time point is not detected 150. The digital multiplex transmission method according to claim 149 , wherein in the slot allocation information generating step, stuffing packet allocation information is generated for a transmission slot immediately after the transmission slot. 151. When the time point is detected in the packet number detecting step within one cycle of one of the transmission slots, and the slot allocation information for the transmission slot immediately following the transmission slot is If it has already been generated, in the slot allocation information generating step, the digital stream for which the time point has been detected for the transmission slot immediately following the transmission slot for which the slot allocation information has not been generated. 151. The digital multiplex transmission method according to any one of claims 145 to 150 , characterized in that the slot allocation information is generated. 152. When the slot allocation information generating step has already generated the slot allocation information for each transmission slot of one cycle of the multiplexing frame, and the multiplexing frame In one packet, in the packet number detecting step, and when the time point is detected in the digital stream, in the slot allocation information generating step, the multiplexed frame immediately following the multiplexed frame is detected. The digital multiplex transmission method according to any one of claims 145 to 151 , wherein allocation information of the digital stream is generated for a transmission slot. 153. In one cycle of one transmission slot, when the packet number detecting step detects the time point a plurality of times for each of the one digital stream or each of the plurality of digital streams, the slot allocation is performed. In the information generating step, the slot allocation information is generated for any one of the transmission slots immediately after the transmission slot, which is the same number as the time point detected in the packet number detecting step. The digital multiplex transmission method according to any one of claims 145 to 152 . 154. In the slot allocation information generating step, the slot allocation information is not generated for a transmission slot transmitting the slot allocation information among the transmission slots forming the multiplexed frame. 154. The digital multiplex transmission method according to any one of claims 142 to 153 . 155. Means for allocating a transmission slot of the packet according to an input time point of the inputted packet, means for multiplexing the packet in the transmission slot according to the allocation and transmitting the system time information of the packet. A means for generating a correction amount of the system time information based on the multiplexing delay time of the included packet; and a means for correcting the system time information of the packet including the system time information by the correction amount. A digital multiplex transmission device characterized by: 156. The correction amount is the time from an input time of a packet including the system time information to an end time of a transmission slot being transmitted at the input time, and a transmission slot immediately after the transmission slot to the system. 155. The digital multiplex transmission apparatus according to claim 155 , wherein the packet is generated based on a total time of a time up to a transmission slot assigned to a packet including time information. 157. The correction amount is a parameter indicating a time from an input time point of a packet including the system time information to an end time point of a transmission slot being transmitted at the input time point, and a parameter immediately after the transmission slot. 155. The digital multiplex transmission apparatus according to claim 155 , wherein the digital multiplex transmission apparatus is generated based on a parameter indicating the number of transmission slots from a transmission slot to a transmission slot assigned to a packet including the system time information. 158. The correction amount is a parameter indicating a time from an input time point of a packet including the system time information to an end time point of a transmission slot being transmitted at the input time point, and a parameter immediately after the transmission slot. It is generated based on a parameter indicating the number of transmission slots from a transmission slot to a transmission slot assigned to a packet including the time information, and a parameter indicating a multiplexing transmission rate.
155. A digital multiplex transmission apparatus according to item 155 . 159. Means for allocating a transmission slot of the packet according to an input time point of the inputted packet, means for multiplexing the packet in the transmission slot according to the allocation and transmitting the system time information of the packet. Means for generating a parameter representing the included multiplexing delay time, means for storing the parameter, means for reading the stored parameter at the time of multiplexing, and a correction amount based on the read parameter. A digital multiplex transmission apparatus comprising: a generating unit; and a unit that corrects the system time information with the correction amount. 160. The parameter is a parameter representing a time from an input time point of a packet including the system time information to an end time point of a transmission slot being transmitted at the input time point, and a transmission immediately after the transmission slot. 160. The digital multiplex transmission apparatus according to claim 159 , characterized in that it is configured by a parameter representing the number of transmission slots from a slot to a transmission slot assigned to a packet containing the system time information. 161. The parameter is a parameter representing a time from an input time point of a packet including the system time information to an end time point of a transmission slot being transmitted at the input time point, and a transmission immediately after the transmission slot. 160. The digital multiplex transmission according to claim 159 , characterized in that it comprises a number of transmission slots from a slot to a transmission slot assigned to a packet containing the system time information, and a parameter representing a multiplexing transmission rate. apparatus. 162. The means for generating the correction amount comprises a read-only memory that inputs the parameter and outputs the correction amount.
159. A digital multiplex transmission apparatus according to 159 . 163. A digital multiplex transmission apparatus which selects a packet of a multiplexing target program from at least one input digital stream, multiplexes the selected packet into a corresponding transmission slot, and outputs the multiplexed packet, A digital multiplexing means for allocating a transmission slot to be multiplexed with the packet according to, when the packet is a packet including system time information, an input completion time point of the packet including the system time information, and the packet Correction amount generation for generating a correction amount of delay jitter generated when a packet including the system time information is multiplexed based on information indicating the transmission slot assigned to the packet including the system time information in the multiplexing means Means and the correction amount generation means Based on the correction amount,
A digital multiplex transmission apparatus comprising: a correction unit configured to correct the system time information of a packet including the system time information multiplexed and output from the digital multiplexing unit. 164. The correction amount is a first time from a time point when the input of a packet including the system time information is completed to a time point when the input of the digital multiplexing means ends the transmission of a transmission slot being transmitted. , A second time from the transmission start time of the transmission slot immediately after the transmission slot to the transmission start time of the transmission slot assigned to the packet including the system time information, which is represented by the total time. 163. The digital multiplex transmission device according to claim 163, wherein: 165. The correction amount generation means is provided for each of the at least one input digital stream, and a PCR packet input detection means for detecting an input completion time point of a packet including the system time information and outputting a PCR detection signal. , A transmission slot which is provided for each of the PCR packet detection means and is being transmitted at the time of input of the packet including the PCR detection signal output from the PCR packet input detection means and the system time information Information and information indicating a transmission slot allocated to the packet including the system time information are input from the digital multiplexing means, and the first time and the second time for the packet including the system time information are input. Correction parameter generating means for generating various parameters for obtaining time, Selection means for inputting and outputting the various parameters generated by the correction parameter generation means from the correction parameter generation means corresponding to the PCR packet input detection means that has detected the packet including the system time information; Information indicating the transmission slot that was being transmitted at the time of inputting the packet including the system time information input from the digital multiplexing means and information indicating the transmission slot assigned to the packet including the system time information According to, the parameter storage means for writing and reading the various parameters input from the selection means, and the correction amount for outputting the correction amount corresponding to the various parameters read from the parameter storage means to the correction means And a quantity output means, and That claims 163 or
164. A digital multiplex transmission apparatus according to 164 . 166. The slot allocation operation speed in the digital multiplexing means and the correction amount generating operation speed in the correction amount generating means are one of slot clock signals defining a multiplexing output speed in the digital multiplexing means. 163. / 163 (k is an integer) and is defined using a 1 / k slot clock signal synchronized with the slot clock signal.
165. A digital multiplex transmission device according to any one of 165 . 167. The slot allocation operation speed in the digital multiplexing means and the correction amount generation operation speed in the correction amount generation means are one of slot clock signals defining a multiplexing output speed in the digital multiplexing means. The digital multiplex transmission apparatus according to any one of claims 163 to 165 , characterized in that the half-slot clock signal is synchronized with the slot clock signal at a cycle of / 2. 168. The various parameters are a first parameter indicating the number of cycles of a system clock from the completion of input of a packet including the system time information to the next rise of the 1 / k slot clock signal, and the input. A second parameter indicating the pulse position of the 1 / k slot clock signal at the time of completion, and the first amount of time corresponding to the first parameter and the second parameter from the correction amount output means. 166. The digital multiplex transmission apparatus according to claim 166 , wherein a quantity representing is output. 169. The various parameters are a first parameter indicating the number of cycles of the system clock from the time when the input of the packet including the system time information is completed to the next rising edge of the half slot clock signal, and the time when the input is completed. A second parameter indicating a logical level of the half slot clock signal, and the correction amount output means outputs a quantity representing the first time corresponding to the first parameter and the second parameter. 167. The digital multiplex transmission device according to claim 167, wherein: 170. The various parameters are assigned to the packet containing the system time information from the transmission slot immediately after the transmission slot being sent from the digital multiplexing means at the time when the input of the packet containing the system time information is completed. 166 , wherein the correction amount output means outputs the second time period corresponding to the third parameter, including a third parameter indicating the number of transmission slots up to the transmission slot. 169. The digital multiplex transmission device according to any one of 169 . 171. Further, the correction parameter generating means outputs a correction valid signal relating to a timing at which the packet including the system time information is multiplexed in a transmission slot in the digital multiplexing means, and the correction valid signal is valid. When the period is indicated, the selection means outputs the first parameter, the second parameter, and the third parameter input from the correction parameter generation means to the parameter storage means. The digital multiplex transmission apparatus according to claim 170 . 172. The correcting means arithmetically adds the correction amount to the system time information of the packet containing the system time information multiplexed and output from the digital multiplexing means, and outputs the packet. The digital multiplex transmission device according to any one of claims 163 to 171 . 173. The correction amount output means is composed of a read-only memory that stores the correction amount for each address, and the first parameter, the second parameter, and the third parameter are input to the address. The digital multiplex transmission according to any one of claims 170 to 172 , wherein the correction amount corresponding to the first parameter, the second parameter, and the third parameter is output by outputting the correction amount. apparatus. 174. When a plurality of output rates are used as the multiplexed output rate in the digital multiplexing means, the multiplex is performed on a bit different from the first parameter, the second parameter and the third parameter. The address to which the value indicating the converted output speed is further input is input to the correction amount output means, and the correction amount output means is based on the input of the address to which the value indicating the multiplexed output speed is further added,
The digital multiplex transmission apparatus according to any one of claims 170 to 173 , wherein the correction amount according to the multiplexed output speed is output. 175. The PID, which is provided for each of the at least one input digital stream, selectively passes only packets of a program to be multiplexed from the input digital stream.
A filter / conversion means, and each of the PID filters / conversion means,
A buffer memory for temporarily storing the packet that has passed through the D filter / conversion means, a stuffing packet memory for storing null packets, and a P memory provided for each PID filter / conversion means.
Packet input detecting means for detecting an input completion time point of the packet passing through the ID filter / converting means to the buffer memory and outputting an input detection signal; and based on the input detection signals outputted from the respective packet input detecting means, A slot allocation information generating unit for generating, in units of one multiplexing group transmission time, slot allocation information indicating allocation of transmission slots to be multiplexed with respect to a packet which has been input to the buffer memory, and the slot allocation information generating unit. Based on the slot allocation information generated by the above, the packet is read from the buffer memory, or the null packet is read from the stuffing packet memory, and a transmission slot to be multiplexed with the packet or the null packet is allocated. And means Claims 163, wherein the door
174. The digital multiplex transmission device according to any one of 174 . 176. The slot allocation information generating means is provided for each of the packet input detecting means, and the input detection signal and the 1 / k from the packet input detecting means are provided.
Retiming means including a slot clock signal as an input and converting the input detection signal into a signal having a pulse width of one cycle time of the 1 / k slot clock signal and outputting the signal; the 1 / k slot clock signal and the slot A clock signal is input, and a first pulse signal having the same number of pulse generation positions as the retiming means is different for each cycle of the 1 / k slot clock signal, and the pulse signal is for each cycle of the slot clock signal. Is provided for each of the retiming means and pulse generating means for generating a second pulse signal which is different from the first pulse signal at a different pulse generating position, and the retiming means. Input and the output of the pulse generating means,
Each of the first AND gates includes a first AND gate that controls passage of the first pulse signal by inputting the pulse signal from the retiming means, and an output of each of the first AND gates as an input. A stream number encoder for generating information indicating a digital stream corresponding to each input of the first pulse signal from the AND gate, and an OR gate including an output of each of the first AND gates as an input, A slot number counter that outputs a slot counter value that counts the pulses of the slot clock signal for each transmission time of one multiplexing group, and that outputs a carry signal each time the slot counter value returns from the maximum value to the initial value; It is composed of a counter having a number of digits larger than that of a slot number counter, and the first pulse signal is inputted through the OR gate. Each time it is input, the write address value is incremented by 1, and the write address value is output as a write address signal in the same format as the slot number counter, the slot counter value, and the slot counter. The value and the lower digit of the write address value having the same digit are compared, and when the lower digit of the write address value is smaller than the slot counter value as a result of the comparison, the true value 1 is output. A second logic for inputting the magnitude comparison means and the output of the magnitude comparison means and the output of the pulse generation means, and controlling the passage of the second pulse signal by inputting the true value 1 from the magnitude comparison means. AND gate, the pulse signal passing through the second AND gate is given to the stream number encoder and the OR gate, and the second pulse signal is the stream signal. Signal encoder, the stream number encoder generates information indicating stuffing, and when the second pulse signal is applied to the OR gate, the second pulse signal passes through the AND gate. The write address counter is provided to count the write address value so that the write address value is incremented by 1, and the slot allocation information generating means further includes the digital stream output from the stream number encoder. Or storage information in which the information indicating the stuffing is written in the address indicated by the write address signal, and a conversion means for performing a predetermined conversion on the carry signal output from the slot number counter. , The signal output from the conversion means and the slot counter value The read address to be read is inputted to the storage means, and the information indicating the digital stream or the information indicating the stuffing stored before the transmission time of one multiplexing group is read from the storage means. Item 175. The digital multiplex transmission device according to Item 175 . 177. The retiming means comprises the 1 / k slot clock signal, a logic level 0 signal,
And inputting the input detection signal, presetting the output value to 1 every time the input detection signal is input, and reading the logic level 0 signal by the subsequent rising edge of the 1 / k slot clock signal. A first flip-flop that outputs an output value of 0, an output of the first flip-flop, and the 1 / k slot clock signal as inputs, and the first rising edge of the 1 / k slot clock signal Output value 1 from the flip-flop of 1 and output value 1
179. A digital multiplex transmission apparatus according to claim 176 , further comprising: a second flip-flop for outputting to the selecting means as. 178. The correction parameter generating means receives the PCR detection signal and a system clock having a predetermined frequency as input, and clears the count value to zero each time the PCR detection signal is input, and the system clock. A first counter that counts and outputs a count value; the output of the first counter and the 1 / k slot clock signal are input, and the first counter is input by the rising edge of the 1 / k slot clock signal. A first register for holding the output of the counter and outputting the held signal as the first parameter to the selecting means; and synchronizing with the 1 / k slot clock signal every one cycle of the slot clock signal. 0 to k-1 at the timing
Up to a second counter, and the count value by the second counter and the PCR detection signal are input, and the count value in the second counter is held each time the PCR detection signal is input, A second register for outputting the held count value, an output of the second register and the 1 / k slot clock signal as inputs, and the second input by the rising input of the 1 / k slot clock signal A third register for holding the output of the register and outputting the held signal as the second parameter signal to the selecting means, the output of the slot number counter and the PCR detection signal as inputs, and the PCR Each time a detection signal is input, the slot counter value at the time of input is held, and the held signal is output. Of the fourth register and the output of the fourth register and the 1 / k slot clock signal are input, and the output of the fourth register is held by the input of the rising edge of the 1 / k slot clock signal, and the holding is performed. A fifth register for outputting the signal, and the output of the fifth register and the write address value of the lower digit as input, and the write address value of the lower digit is output from the output value of the fifth register. A subtracter that outputs a value obtained by subtracting 1 from the subtracted value to the selecting means as the third parameter signal, the 1 / k slot clock signal, the logic level 0 signal,
And the PCR detection signal as an input, the output value is preset to 1 every time the PCR detection signal is input, and the ethics level 0 signal is read and output by the subsequent input of the rising edge of the 1 / k slot clock signal. Value 0
And a third flip-flop that outputs the third flip-flop and the output of the third flip-flop and the 1 / k slot clock signal as input, and the third flip-flop by the rising input of the 1 / k slot clock signal. 178. A digital multiplex transmission apparatus according to claim 176 or 177 , further comprising: a fourth flip-flop for reading the output value 1 from the above and outputting it to the selecting means as the correction valid signal. 179. The slot allocation information generation means is provided for each of the packet input detection means, and includes the input detection signal and the half slot clock signal from the packet input detection means as inputs, and the input detection signal To a signal having a pulse width of one cycle time of the half-slot clock signal and outputting the half-slot clock signal, and the half-slot clock signal and the slot clock signal as input, for each cycle of the half-slot clock signal. The first pulse signal having the same number of pulse generation positions as that of the retiming means and the pulse generation position differ from the pulse signal every one cycle of the slot clock signal, and the pulse generation position is the first pulse signal. Pulse generating means for generating a second pulse signal rearward of Wherein provided in each retiming means, receives the output of the output and the pulse generating means of the retiming means,
Each of the first AND gates includes a first AND gate that controls passage of the first pulse signal by inputting the pulse signal from the retiming means, and an output of each of the first AND gates as an input. A stream number encoder for generating information indicating a digital stream corresponding to each input of the first pulse signal from the AND gate, and an OR gate including an output of each of the first AND gates as an input, A slot number counter that outputs a slot counter value that counts the pulses of the slot clock signal for each transmission time of one multiplexing group, and that outputs a carry signal each time the slot counter value returns from the maximum value to the initial value; It is composed of a counter having a number of digits larger than that of a slot number counter, and the first pulse signal is inputted through the OR gate. Each time it is input, the write address value is incremented by 1, and the write address value is output as a write address signal in the same format as the slot number counter, the slot counter value, and the slot counter. The value and the lower digit of the write address value having the same digit are compared, and when the lower digit of the write address value is smaller than the slot counter value as a result of the comparison, the true value 1 is output. A magnitude comparison means, and a second logic which receives the output of the magnitude comparison means and the output of the pulse generation means and controls passage of the second pulse signal by inputting a true value 1 from the magnitude comparison means. AND gate, the pulse signal passing through the second AND gate is given to the stream number encoder and the OR gate, and the second pulse signal is the stream signal. Signal encoder, the stream number encoder generates information indicating stuffing, and when the second pulse signal is applied to the AND gate, the second pulse signal passes through the OR gate. Given to the write address counter, the write address counter counts the write address value so as to advance by one, and the slot allocation information generating means further includes the digital stream output from the stream number encoder. Or storage information in which the information indicating the stuffing is written at the address indicated by the write address signal, and a conversion means for performing a predetermined conversion on the carry signal output from the slot number counter. , The signal output from the conversion means and the slot counter value The read address to be read is input to the storage means, and the information indicating the digital stream or the information indicating the stuffing stored before the transmission time of one multiplexing group is read from the storage means. Item 175. The digital multiplex transmission device according to Item 175 . 180. The retiming means comprises the half slot clock signal, a logic level 0 signal,
And inputting the input detection signal, presetting the output value to 1 each time the input detection signal is input, and reading the logical level 0 signal and outputting the output value by the subsequent rising edge input of the half slot clock signal. A first flip-flop that outputs 0, and the output of the first flip-flop and the half-slot clock signal are input, and the rising edge of the half-slot clock signal causes the first flip-flop to Output value 1 is read and output value 1
179. A digital multiplex transmission apparatus according to claim 176 , further comprising: a second flip-flop for outputting to the selecting means as. 181. The correction parameter generating means receives the PCR detection signal and a system clock having a predetermined frequency as inputs, clears a count value to zero each time the PCR detection signal is input, and outputs the system clock. A counter that counts and outputs a count value, an input of the output of the counter and the half-slot clock signal, holds the output of the counter by the input of the rising edge of the half-slot clock signal, and holds the held signal. A first register for outputting to the selection means as the first parameter, the PCR detection signal and the slot clock signal are input, and each time the PCR detection signal is input, the slot clock signal at the time of the input is input. Holds the logic level and outputs the held logic level A second register, the output of the second register and the half-slot clock signal are input, and the output of the second register is held by the rising input of the half-slot clock signal, and the held A third register for outputting a signal to the selecting means as the second parameter signal, the output of the slot number counter and the PCR detection signal are input, and each time the PCR detection signal is input, A fourth register that holds the slot counter value and outputs the held signal, and an output of the fourth register and the half slot clock signal are input, and a rising edge of the half slot clock signal is input. A fifth register for holding the output of the fourth register and outputting the held signal And inputting the output of the fifth register and the write address value of the lower digit, subtracting the write address value of the lower digit from the output value of the fifth register, and further subtracting 1 from the value. A subtracter for outputting the selected value as the third parameter signal to the selecting means, the half slot clock signal, a logic level 0 signal,
And inputting the PCR detection signal, presetting the output value to 1 each time the PCR detection signal is input, and reading the ethics level 0 signal and outputting the output value 0 by inputting the rising edge of the half slot clock signal thereafter.
Output from the third flip-flop, and the output of the third flip-flop and the half-slot clock signal as input, and the output value from the third flip-flop by the rising input of the half-slot clock signal. 178. A digital multiplex transmission apparatus according to claim 176 or 177 , further comprising: a fourth flip-flop that reads 1 and outputs the correction valid signal to the selection means. 182. The first pulse signal that has passed through each of the first AND gates is given to the selecting means, and the selecting means outputs from the correction parameter generating means corresponding to the first pulse signal. 176. The method of claim 176 , wherein the first parameter, the second parameter, the third parameter, and the correction valid signal are input .
181. The digital multiplex transmission apparatus according to any one of 181 . 183. The slot counter value and the write address value are given to the parameter storage means,
183. The digital multiplex transmission apparatus according to any one of claims 176 to 182 , wherein the parameter storage means performs write and read operations for the same address as the storage means.