JP2000196462A - Parallel/serial converting circuit and synchronous multiple transmission device having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure a setup margin and to enable high-speed operation by reading parallel data out of a flip-flop(F/F) according to a signal with the change point of input parallel data as a reference. SOLUTION: An edge detecting signal TPG of a timing pulse having the change point coincident with parallel data is inputted from an edge detecting circuit 32 to a counter 34. Besides, (n) pieces of parallel data are inputted to an F/F 36 and latched. The F/F 36, to which a timing controlled enable signal EN from the counter 34 is inputted, outputs the parallel data to a selector 38. The selector 38 fetches selection signal 1-N from the counter 34 and when the selection signal is 'H', relevant data are selected and outputted to an F/F 40. The selector 38 successively outputs the parallel data of 1/n cycle to the F/F 40. The F/F 40 outputs these data as serial data through retiming.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for converting a digital signal into parallel / serial data.
It relates to a circuit for performing serial conversion.

[0002]

2. Description of the Related Art SONET (Synchronous Optical Network)
ork) network or SDH (Synchronous Digital Hierarchy)
In synchronous multiplex transmission equipment used in networks, STS-N
(Synchronous Transport-N) and STM-N (Synchr
When outputting an onous Transfer Mode-N) signal to a line, it is common to convert a low-speed signal into a high-speed signal in parallel / serial.

FIG. 7 is a configuration diagram of a conventional parallel / serial conversion circuit. As shown in FIG. 1, a parallel / serial conversion circuit 10 includes a flip-flop 14 to which parallel data from a parallel operation circuit 12 is input, a selector 16 to output the parallel data as serial data, and retiming of data output from the selector. Flip-flops 18 and 14
And a counter 20 that generates an enable signal to the selector 16 and a selection signal to the selector 16. The high-speed clock 24
Is supplied to each unit, and a clock having a 1 / n cycle is supplied to the parallel operation circuit 12 via the frequency dividing circuit 22. The parallel / serial conversion circuit 10 and the parallel operation circuit 12 are each generally constituted by an LSI.

FIG. 8 is a time chart showing the operation of the parallel / serial conversion circuit 10. The operation of the parallel / serial conversion circuit 10 will be described with reference to FIG. 1 / n
The n parallel data (b) output from the parallel operation circuit 12 according to the clock (a) is
4, the flip-flop 14 latches the data, and the enable signal E input from the counter 20 is input.
Output at the timing of N (c).

The output parallel data (d) is selected by the selector 16 when the selection signal (e) is “H”, and the output (f) from the selector 16 is re-timed by the flip-flop 18 so that The serially converted signal (g) is output.

[0006]

However, in the above-described parallel / serial conversion circuit according to the prior art, the phase of the enable signal input to the flip-flop 14 is not specified with respect to the change in the parallel data.
As shown in the time chart of FIG. 2, at the time of high-speed operation, the transition point between the enable signal and the parallel data approaches, the setup margin is insufficient, and there is a problem that stable operation cannot be guaranteed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a parallel / serial conversion circuit capable of securing a setup margin and operating at high speed, and a synchronous multiplex transmission apparatus having the same. .

[0008]

To achieve the above object, the present invention is configured as follows. The present invention relates to a parallel / parallel circuit including a flip-flop that latches input parallel data, a signal generation circuit that outputs a selection signal, and a selector that outputs parallel data read from the flip-flop as serial data in accordance with the selection signal. A serial conversion circuit for reading the parallel data from the flip-flop according to a signal based on a change point of the input parallel data.

According to the present invention, a change point of a signal having a change point at the same timing as a change point of input parallel data is used as a reference.
The problem that the setup margin is insufficient because the phase difference between the input and the output cannot be specified is solved, the data can be read from the flip-flop with the setup margin secured, and a higher-speed parallel / serial conversion circuit is provided. It becomes possible.

To achieve the above object, the present invention may be configured as follows. The present invention relates to a parallel / parallel circuit including a flip-flop that latches input parallel data, a signal generation circuit that outputs a selection signal, and a selector that outputs parallel data read from the flip-flop as serial data in accordance with the selection signal. A serial conversion circuit, wherein the parallel / serial conversion circuit has an edge detection circuit for detecting a change point of the signal, and the edge detection circuit outputs a signal having a change point at the same timing as the change point of the input parallel data. A signal for receiving and detecting a change point of the signal, and the signal generation circuit reading the parallel data from the flip-flop at a timing when a setup margin is secured with reference to an output signal from the edge detection circuit. And sends the signal to the flip-flop.

According to the present invention, the edge detection circuit receives a signal having a change point at the same timing as the change point of the input parallel data, detects the change point of the signal, and uses the signal of the detection result as a reference. Since the signal generation circuit sends a signal to the flip-flop at a timing at which a setup margin at the time of reading can be secured, the shortage of the setup margin at the time of reading, which was a problem with the conventional technology, is eliminated, and a parallel operation that can operate at higher speed and more stably. / Serial conversion circuit can be provided.

In order to achieve the above object, the present invention may be configured as follows. The present invention is a synchronous multiplex transmission device having the parallel / serial conversion circuit in a line interface unit. According to the present invention, the parallel / serial conversion circuit multiplexes the parallel data and outputs the multiplexed parallel data to the line as high-speed serial data without the shortage of the setup margin unlike the related art. Therefore, it is possible to provide a synchronous multiplex transmission device capable of high-speed and stable operation.

[0013]

FIG. 1 is a block diagram of a parallel / serial conversion circuit 30 according to an embodiment of the present invention. As shown in the figure, a parallel / serial conversion circuit 30 receives an input of a timing pulse, detects an edge thereof, and receives an edge-detected signal to generate an enable signal and a selection signal. A counter 34 as a circuit, a flip-flop 36 for latching the input parallel data, a selector 38 for sequentially outputting the parallel data from the flip-flop 36 in accordance with a selection signal input from the counter 34, and a signal from the selector 38 are retimed. And a flip-flop 40 for outputting as serial data.

The timing pulse input to the edge detection circuit 32 may be a timing pulse at which a bit change point of the input parallel data appears. For example, a clock (a high-speed clock of a high-speed clock) used by the parallel operation circuit for data output. It may be a timing pulse of (1 / n cycle clock). FIG. 2 is a time chart showing the operation of the parallel / serial conversion circuit 30. The operation of the parallel / serial conversion circuit 30 will be described with reference to FIGS. Although the number of parallel data shown in FIG. 2 is n, it is assumed to be one in the description of FIG.

The timing pulse (TP) (b) at which the transition point coincides with the parallel data (a) is supplied to the edge detection circuit 32.
, And the timing pulse is edge-detected by the edge detection circuit 32, and the edge-detected signal (TPG)
(C) is input to the counter 34. The flip-flop 36 receives and latches n parallel data (a).

The counter 34 outputs an enable signal (EN) (d) whose timing has been adjusted (initialized by TPG) so that data can be read at the center of the parallel data input to the flip-flop 36 or at a position where a setup margin can be secured. Then, the enable signal (d) is input to the flip-flop 36. Note that TP
The timing adjustment by G need not be performed every time.

The flip-flop 36 receives the enable signal and outputs the parallel data to the selector 38 (e). The selector 38 outputs the selection signals 1 to N (f) to the counter 3
4 and when the selection signals 1 to N are “H”,
The corresponding data is selected and output (g) to the flip-flop 40. The pulse width of the selection signal is 1 / n of the pulse width of the parallel data, and periodically becomes "H". The selector 38 sequentially outputs 1 / n cycle parallel data to the flip-flop 40. The flip-flop 40 retiming the data and outputs (h) as serial data.

As described above, in the prior art, it is difficult to secure a setup margin during high-speed operation because there is no reference as to where the input data is to be read. Recognize and, based on that,
The setup margin can be secured by an enable signal that is read at a position where the setup margin of the input data is secured.

FIG. 3 is a diagram showing an example of a synchronous multiplex transmission apparatus to which the parallel / serial conversion circuit of the present invention is applied. As shown in the figure, a transmission device 50 includes line interface units 52 to 58 having an interface function with a line, such as demultiplexing of a signal, an STS signal processing unit 60 that performs various processes of an STS signal, and various types of ATM signals. , An ATM cross-connect unit 64 for cross-connecting the ATM signal, and a control unit 66 for controlling each unit. The line interface units 52 to 58 are respectively STS-12 ( 600M), S
TS-3 (155M), DS3 (45M), DS1
(1.5M) signal is input and output.

The parallel / serial conversion circuit of the present invention is mounted on the interface units 52 and 54 which are required to operate at high speed, and multiplexes parallel data from the STS signal processing unit 60 into serial data to be output to a line. Used for FIG.
FIG. 3 is a diagram illustrating a circuit configuration of a portion that multiplexes a signal from an STS signal processing unit and outputs the multiplexed signal to a line in an interface unit that inputs and outputs a 5 Mb / s signal. This circuit is LS
I.

As shown in FIG. 1, the circuit includes an output unit 70,
It is composed of blocks of a timing transfer section 72 and an input section 74. The output unit 70 supplies a timing pulse to the parallel / serial conversion circuit 76 according to the present invention, a flip-flop 78 for performing retiming, a frequency division circuit 80 for making the supplied clock a cycle of 1/8, and a parallel / serial conversion circuit 76. A counter 81 for performing the operation. Also, parallel data and timing pulses of another system used at the time of the signal loopback test are input. The timing transfer section 72 has a dual-port RAM 82 serving as a buffer for clock transfer, and the input section 74 has a disconnection detection section 84 having a function of detecting a disconnection of the input and transmitting a specific bit. The operation of this circuit will be described next.

A 19.44 Mb / s.times.8 parallel STS-3 signal and a 19.44 MHz clock are input to an input unit 74, which is checked by a disconnection detection circuit 84 and output to the timing transfer unit 72 as it is. Is done. In the timing transfer section 72, the input section 74 is stored in the RAM 82.
Write data and clock from. On the other hand, the output unit 70
The clock switching is performed by reading with the clock from.

The master clock of the output unit 70 is 155.
Although the frequency is 52 MHz, the frequency is divided by 8 and output as a read clock for the RAM 82. The data read from the timing transfer section 72 (19.44 Mb /
s × 8) is once retimed by the flip-flop 78 of the output unit 70, input to the parallel / serial conversion circuit 76, multiplexed and output as 155 Mb / s serial data.

FIG. 5 shows a configuration of the parallel / serial conversion circuit 76 according to the present invention used in the output section 70 of FIG. In the figure, data a is a timing transfer unit 72.
Is a timing pulse generated by the counter 81 in the output unit 70, and the timing pulse in this case is the same as the frame pulse of the SONET signal. Data b and TPb are input of the above-mentioned separate timing pulse and parallel data.

The parallel / serial conversion circuit 76 has a selector 90, an edge detection circuit 92, a counter 94, a flip-flop 96, a decoder 98, a selector 100, and a flip-flop 102. The selector 90 has a function of selecting either the data a or TPa or the data b or TPb according to the control signal. Also, the decoder 98
Has a function of receiving a timing pulse from the counter 94 and generating an enable signal (EN) at a timing at which a setup margin can be secured. Other components are the same as those described in FIG.

FIG. 6 is a time chart showing the operation of the parallel / serial conversion circuit 76 shown in FIG. The operation of the parallel / serial conversion circuit 76 will be described next with reference to FIGS. In the selector 90, data a and TPa or data b and TPb are selected according to the control signal. Here, the selected signals are data c and TPc. The timing pulse TPc is input to the edge detection circuit 92 to detect an edge. The edge detected signal TPd is input to the counter 94. The counter 94 generates a selector select signal SEL. The select signal SEL is input to the decoder, and when the value is 7, the enable signal EN is generated. By setting the decode value of the decoder 98 to 7, the timing of the enable signal EN is adjusted so that reading is performed at the center of the parallel data input to the flip-flop 96 or at a position where a setup margin is secured. The parallel data is read out with a setup margin secured. The read data d is input to the selector 100. The selector 100 converts the parallel data into serial data according to the selector signal SEL and inputs the parallel data to the flip-flop 102. The flip-flop 102 retiming outputs the data e which is serial data. You.

In the above embodiment, the example of the synchronous multiplex transmission apparatus corresponding to the SONET signal has been described. However, the parallel / serial conversion circuit of the present invention can be applied to any other apparatus which performs parallel / serial conversion at high speed. It is possible. It should be noted that the present invention is not limited to the above-described embodiment, but can be variously modified and applied within the scope of the claims.

[0028]

According to the prior art, it is difficult to secure a setup margin at the time of parallel data writing / reading at the time of high-speed operation. However, according to the present invention, as described above, a change point of input data is recognized. By generating an enable signal that is read at a position where the setup margin of the input data is secured, the setup margin can be secured.

Therefore, the shortage of the setup margin at the time of reading the parallel data as in the prior art is solved, and a parallel / serial conversion circuit capable of operating at higher speed and stably can be provided. Further, by using a line interface unit using the parallel / serial conversion circuit of the present invention for a transmission device, it is possible to provide a transmission device capable of operating at higher speed and more stably.

[Brief description of the drawings]

FIG. 1 is a diagram showing a parallel / serial conversion circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing an operation of the parallel / serial conversion circuit of one embodiment according to the present invention.

FIG. 3 is a diagram showing an example of a synchronous multiplex transmission device having a parallel / serial conversion circuit according to the present invention.

FIG. 4 is a diagram showing an example of a circuit having a parallel / serial conversion circuit according to the present invention.

FIG. 5 is a diagram showing a parallel / serial conversion circuit in the circuit shown in FIG. 4;

FIG. 6 is a time chart illustrating an operation of the parallel / serial conversion circuit illustrated in FIG. 5;

FIG. 7 is a diagram showing a parallel / serial conversion circuit according to the related art.

FIG. 8 is a time chart showing an operation of the parallel / serial conversion circuit according to the related art.

[Explanation of symbols]

10, 30, 76 parallel / serial conversion circuit 12 parallel operation circuit 14, 18, 36, 40, 96, 102 flip-flop 16, 38, 90, 100 selector 20, 34, 81, 94 counter 22, 80 frequency divider 24 High-speed clock 32,92 Edge detection circuit 50 Synchronous multiplex transmission device 52,54,56,58 Line interface unit 60 STS signal processing unit 62 ATM signal processing unit 64 ATM cross connect unit 66 Control unit 70 Output unit 72 Timing transfer unit 74 Input unit 78 flip-flop 82 RAM 84 disconnection detection circuit 98 decoder

Claims (3)

[Claims] A flip-flop that latches input parallel data, a signal generation circuit that outputs a selection signal, and a selector that outputs parallel data read from the flip-flop as serial data in accordance with the selection signal. A parallel / serial conversion circuit, wherein the parallel data is read from the flip-flop in accordance with a signal based on a change point of the input parallel data. 2. A parallel circuit comprising: a flip-flop for latching input parallel data; a signal generation circuit for outputting a selection signal; and a selector for outputting parallel data read from the flip-flop as serial data in accordance with the selection signal. / Serial conversion circuit, wherein the parallel / serial conversion circuit has an edge detection circuit for detecting a change point of the signal, and the edge detection circuit has a change point at the same timing as the change point of the input parallel data. For detecting a change point of the signal, and the signal generation circuit reads the parallel data from the flip-flop at a timing when a setup margin is secured with reference to an output signal from the edge detection circuit. Generating a signal and transmitting the signal to the flip-flop. Parallel / serial conversion circuit. 3. A synchronous multiplex transmission apparatus having the parallel / serial conversion circuit according to claim 1 in a line interface unit.