JP2010118789A - Serial communication system, transmission apparatus, drive device, image reading apparatus, and serial communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a frequency of a signal transmitted by a serial communication system, and reduce a radiation noise. <P>SOLUTION: The system includes: a conversion means which converts a parallel signal composed in a predetermined permutation to a serial signal; a transmitting means to transmit the serial signal; a receiving means to receive the serial signal; and a restoration means to restore the serial signal received by the receiving means to the original parallel signal. In particular, the conversion means creates the serial signal showing a changing point of the parallel signal. The restoration means restores the parallel signal composed in the predetermined permutation based on the serial signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a serial communication technique applicable to, for example, a motor drive device, an image reading device, or a copying device.

  In the image reading apparatus, an image of a document is read by moving an optical system with respect to the document by a stepping motor. In general, a control circuit for a stepping motor is divided into a main board and a motor driver board, and the main board and the motor driver board are connected by parallel signal lines. A CPU that generates a number of phase signals for controlling the stepping motor is mounted on the main board. On the other hand, a motor driver IC that converts a phase signal with an amplitude of 3.3 V into a phase signal with an amplitude of 24 V is mounted on the motor driver board.

  By the way, it is not uncommon for an image reading apparatus to use ten or more stepping motors. In this case, since the number of phase signals is 40 to 50 or more, the number of parallel signal lines and the number of phase signals are complicated.

Therefore, it has been proposed to replace the parallel signal line with a serial signal line (Patent Documents 1 and 2). If such a serial signal line is used, the degree of freedom of the search is secured.
Japanese Patent Laid-Open No. 5-48998 JP-A-5-37908

  Incidentally, in order to increase the speed of the image reading apparatus, it is required to increase the rotation speed of the motor. In general, the frequency of the clock signal used for serial communication is the same as the frequency of the system clock used in the main board or a frequency obtained by dividing it several times. In general, the frequency of the system clock is several MHz to several tens of MHz, but the frequency of the phase signal is only about 5000 PPS (= 5 kHz). Therefore, if the frequency difference is about this level, it is difficult to cause a problem even if the clock is transmitted together with the serial signal.

  On the other hand, when the frequency of the phase signal becomes 10,000 PPS (= 10 kHz) or more, the frequency of the clock signal must be set to a frequency of several MHz. Otherwise, four signals (A, A *, B, B *) having different phases may not be transmitted by serial communication, and reproduction accuracy on the receiving side may not be ensured.

  However, when the frequency of the clock signal is on the order of several MHz, there is a possibility of causing malfunction of the unit or malfunction of other devices outside the equipment due to radiation noise from the cable connecting the main board and the motor drive board.

  Therefore, an object of the present invention is to solve at least one of such problems and other problems. For example, it aims at reducing the frequency of the signal transmitted by serial communication, and reducing radiation noise. Other issues can be understood throughout the specification.

  The present invention can be applied to, for example, a serial communication system. The system includes a conversion unit that converts a parallel signal composed of a predetermined permutation into a serial signal, a transmission unit that transmits the serial signal, a reception unit that receives the serial signal transmitted by the transmission unit, and a reception unit. Restoring means for restoring the received serial signal to the original parallel signal. The converting means generates a serial signal representing a displacement point of the parallel signal, and the restoring means restores to a parallel signal composed of a predetermined permutation based on the serial signal.

  According to the present invention, the frequency of a signal transmitted by serial communication is reduced by generating a serial signal that represents a displacement point of the parallel signal and restoring the parallel signal configured by a predetermined permutation based on the serial signal. In addition, radiation noise is also reduced.

  An embodiment of the present invention is shown below. The individual embodiments described below will help to understand various concepts, such as the superordinate concept, intermediate concept and subordinate concept of the present invention. Further, the technical scope of the present invention is determined by the scope of the claims, and is not limited by the following individual embodiments.

[Related technologies]
In order to understand the present invention, first, related techniques of the present invention will be described. This related technique is not necessarily a known technique.

  FIG. 1 is a diagram illustrating a schematic configuration of the image reading apparatus 100. A document 204 is placed on a document table glass 203 and illuminated by a document illumination lamp 201 from below. The image of the original 204 is imaged on the CCD 209 via the first mirror 205, the second mirror 206, the third mirror 207, and the lens 208. The CCD 209 reads a line image of the document 204. The optical system such as the document illumination lamp 201 and the first mirror 205 is moved relative to the document 204 by a stepping motor. The optical systems such as the second mirror 206 and the third mirror 207 move in the same manner. As a result, the distance (optical path length) from the document surface to the CCD 209 is kept constant. The read line image is input to an image processor circuit (not shown) and converted into image data. The image data is sent to a printer or a host computer. In the copying apparatus, the image signal acquired by the image reading apparatus is transferred to the image forming apparatus, and the image forming apparatus forms an image on a sheet according to the image signal.

  FIG. 2 is a diagram showing a stepping motor driving apparatus employing parallel transmission. Here, it is assumed that the main board 301 and the motor driver board 307 perform parallel transmission.

  A CPU 302 that controls the image reading apparatus 100 shown in FIG. 1 is mounted on the main board 301. The CPU 302 operates in accordance with a system clock having a predetermined frequency generated by the system clock oscillator 303. The CPU 302 is driven with a voltage of 3.3V, for example. Therefore, each signal output from the CPU 302 is also a digital signal having an amplitude of 3.3V.

  The CPU 302 has several output ports. Four of them output a phase signal group 304 that drives the stepping motor 312. The amplitude of the phase signal group 304 is 3.3V.

  The stepping motor 312 is, for example, a two-phase stepping motor. In this case, the phase signal group 304 includes four signals of four phase signals A, A *, B, and B *.

  The main board 301 is provided with a connector 305, and one end of a cable 306 is connected thereto. On the other hand, the motor driver board 307 is provided with a connector 308 to which the other end of the cable 306 is connected. The phase signal group 304 is transmitted from the main board to the motor driver board via the connector 305, the cable 306, and the connector 308. The connector 308 is connected to the motor driver IC 310 by a wiring pattern 309.

  A voltage of 24V is applied to the motor driver IC 310. The motor driver IC 310 converts the phase signal group 304 having an amplitude of 3.3V into a signal of 24V amplitude that can drive the stepping motor 312 and outputs the signal. The phase signals A, A *, B, and B * converted into the amplitude of 24V are input to the stepping motor 312 via the connector 311. The stepping motor 312 is controlled according to the input phase signal.

  By mounting the motor driver IC 310 on the main board 301, the motor driver board 307 can be eliminated. However, in this case, a signal of 24V amplitude is transmitted by the cable 306, and the longer the cable, the higher the possibility that radiated noise will be generated from the cable swirling in the image reading apparatus. In addition, in order to transmit a signal with 24V amplitude, it is necessary to form a cable with a thicker electric wire as compared with a signal with 3.3V amplitude. This is also disadvantageous in terms of cost. In addition, since the stiffness of the cable is strong (that is, the flexibility is small), the degree of freedom of the work is also reduced. Therefore, when the configuration of FIG. 2 is adopted, the motor driver board 307 and the stepping motor 312 must be arranged as close as possible.

  Although only one stepping motor is shown in FIG. 2, in practice, as many as ten or so may be required. Therefore, the number of phase signals of the motor system output from the main board 301 is 40 to 50 or more. This increases the number of bundles constituting the cable 306 and further complicates the cable twisting.

  FIG. 3 is a diagram showing a stepping motor driving apparatus employing serial communication as a related technique. Compared with parallel communication, serial communication can reduce the number of bundled wires that constitute a cable, and can also increase the degree of freedom of cable connection. For simplicity of explanation, only two stepping motors 410A and 410B are shown here. However, in reality, there may be more than a dozen motors.

  A CPU 302A, two parallel serial converters 402A and 402B, and a connector 403 are mounted on the main board 301A. The motor driver board 307A is connected to the main board 301A via the cable 404. The motor driver board 307A is provided with a connector 405 for the cable 404, two serial / parallel converters 406A and 406B, two motor driver ICs 408A and 408B, and two connectors 409A and 409B for the stepping motor. The serial / parallel converter 406A outputs the restored phase signal group 407A to the motor driver IC 408A. The serial / parallel converter 406B outputs the restored phase signal group 407B to the motor driver IC 408B.

  The CPU 302A outputs a phase signal group 401A (1A, 1A *, 1B, 1B *) for driving the two-phase stepping motor 410A. Further, the CPU 302A outputs a phase signal group 401B (2A, 2A *, 2B, 2B *) for driving the two-phase stepping motor 410B. Here, two phase signal groups 401A and 401B are shown. However, if the number of stepping motors increases, phase signal groups proportional to the number of step signal motors are required. Note that the number of output ports of the CPU 302A is also limited. Therefore, the phase signal may be output from an output port such as an ASIC (not shown) connected to the CPU 302A.

  The phase signal group 401A is input to the parallel-serial converter 402A. The phase signal 401B is input to the parallel-serial converter 402B. The CPU 302A further outputs a signal CLK, which is a clock signal for serial communication, and a signal LOAD indicating the data loading timing. The signal CLK and the signal LOAD are input to the parallel / serial converters 402A and 402B. These signals may also be output from an output port such as an ASIC (not shown).

  FIG. 4 shows details of the parallel-serial converters 402A and 402B. Reference numerals 501A to 501D denote D-type flip-flops that operate according to the signal CLK. 502A to 502D are selectors.

  The selectors 502A to 502D select the connected flip output when the signal LOAD is 0, and select and output the input phase signal when the signal LOAD is 1. The signal output from the selector 502A is input to the flip-flop 501A. The signal output from the flip-flop 501A is input to the selector 502B. The signal output from the selector 502B is input to the flip-flop 501B. The signal output from the flip-flop 501B is input to the selector 502C. The signal output from the selector 502C is input to the flip-flop 501C. The signal output from the flip-flop 501C is input to the selector 502DB. The signal output from the selector 502D is input to the flip-flop 501D. The signal SOUT output from the flip-flop 501A is the output of the parallel-serial converter.

  FIG. 5 is a timing chart of the parallel-serial converter. From the top, signal CLK, signal LOAD, phase signals A, A *, B, B *, and output signal SOUT are shown.

  The signal LOAD is a signal that becomes one pulse for every four pulses of the signal CLK. At the timing t1 shown in the figure, the signal LOAD becomes 1 (High). Therefore, at timing t1, the selectors 502A to 502D load the phase signals A to B *.

  Further, at the timing t1 when the load is executed, the flip-flop 501D outputs the value of the phase signal B * as the output signal SOUT. Each time the next pulse for the signal CLK is input, the flip-flop 501D outputs the values of the phase signals B, A *, A as the output signal SOUT. Each time the signal LOAD becomes 1 again, the phase signal B * is output in order. In this way, parallel-serial conversion is executed.

  Returning to FIG. 3, the description will be continued. The serial output signal SOUT of the parallel-serial converters 402A and 402B is transmitted (output) to the motor driver board 307A through the connector 403, the cable 404, and the connector 405 together with the signal LOAD and the signal CLK.

  Serial / parallel converters 406A and 406B are mounted on the motor driver board 307A. Two serial signals, a signal LOAD and a signal CLK, are input to the serial / parallel converters 406A and 406B, respectively.

  FIG. 6 is a diagram showing details of the serial / parallel converters 406A and 406B. The D-type flip-flops 701A to 701D sequentially shift register the input serial signal SIN at the rising timing of the pulse of the input signal CLK and output it. The output signal of the flip-flop 701A is input to the flip-flop 701B and the 4-bit D-type flip-flop 702. The output signal of the flip-flop 701B is input to the flip-flop 701C and the flip-flop 702. The output signal of the flip-flop 701C is input to the flip-flop 701D and the flip-flop 702.

  The flip-flop 702 restores a parallel signal composed of the phase signals A, A *, B, and B * by latching data input at the falling timing of the pulse of the signal LOAD.

  FIG. 7 is a timing chart of the serial-parallel converter. The signal CLK, serial signal SIN, output signals A to D from each flip-flop, signal LOAD, and output signals A, A *, B, and B * from the flip-flop 702 are shown in order from the top. As can be seen from FIG. 7, the phase signals A, A *, B, and B * are reproduced as parallel signals with a delay of one pulse of the signal LOAD (four pulses of the signal CLK).

  The phase signal group 407A reproduced by the serial / parallel converter 406A and the phase signal group 407B reproduced by the serial / parallel converter 406B are input to the corresponding motor driver ICs 408A and 408B, respectively. The motor driver ICs 408A and 408B convert the input phase signal into a 24V amplitude motor drive pulse and output it to the corresponding stepping motor.

  The serial-parallel converters 406A and 406B generate a delay corresponding to four pulses of the signal CLK. This delay is solved by the CPU 302A sending out the phase signal earlier by four pulses.

  As described above, the number of bundled wires constituting the cable can be reduced by performing the parallel-serial conversion on the phase signal group, so that the cost reduction and the simplification of the cable winding can be realized.

[Embodiment 1]
In the related art, although reduction in cost and simplification of cable routing can be realized, there is room for improvement with respect to the increase in the frequency of the transmitted signal and the accompanying radiation noise.

  FIG. 8 is a block diagram illustrating an example of a stepping motor driving apparatus according to the embodiment. The same reference numerals are assigned to the same portions as those already described.

  According to FIG. 8, on the transmission device side, coders 901A and 901B are employed instead of the parallel-serial converters 402A and 402B. Similarly, on the receiving apparatus side, decoders 905A and 905B are employed instead of the serial / parallel converters 406A and 406B. Further, signal lines for transmitting the signal CLK and the signal LOAD are deleted from the cable 903 connecting the connector 902 of the main board 301A and the connector 904 of the motor driver board 307A. The main board 301A is an example of a first board, and the motor driver board 307A is an example of a second board. The motor driver ICs 408A and 408B are an example of a drive unit that is mounted on the second substrate and drives the motor based on the parallel signal restored by the restoration unit.

  FIG. 9 is a diagram illustrating an example of the coders 901A and 901B according to the embodiment. 101A to 101D are D-type flip-flops. 102A to 102D are two-input XOR gates. Reference numeral 103 denotes a 4-input OR gate. Reference numeral 105 denotes a 2-input AND gate. Reference numeral 104 denotes a delay buffer for timing adjustment.

  The signal CLK is input to each of the flip-flops 101A to 101D and the delay buffer 104. The phase signal A is input to the flip-flop 101A and the XOR gate 102A. The output signal of the flip-flop 101A is input to the XOR gate 102A. The output signal of the XOR gate 102A is input to the OR gate 103. The phase signal A * is input to the flip-flop 101B and the XOR gate 102B. The output signal of the flip-flop 101B is input to the XOR gate 102B. The output signal of the XOR gate 102B is input to the OR gate 103. The phase signal B is input to the flip-flop 101C and the XOR gate 102C. The output signal of the flip-flop 101C is input to the XOR gate 102C. The output signal of the XOR gate 102C is input to the OR gate 103. The phase signal B * is input to the flip-flop 101D and the XOR gate 102D. The output signal of the flip-flop 101D is input to the XOR gate 102D. The output signal of the XOR gate 102D is input to the OR gate 103. The output signal of the OR gate 103 and the output signal of the delay buffer 104 are input to the AND gate 105.

  The circuit 107 includes a flip-flop 101A and an XOR gate 102A. The circuit 107 is an example of a detection unit that detects a displacement point of each signal constituting the parallel signal. The OR gate 103 is an example of a logical sum operation element that generates a logical sum from exclusive OR of parallel signals. The AND gate 105 is an example of an AND operation element that generates a logical product of a logical sum and a clock signal as a serial signal. Furthermore, the OR gate 103 and the AND gate 105 are an example of a generating unit that generates a pulse signal when a detecting unit detects a displacement point.

  FIG. 10 is a timing chart of the circuit 107. From the top, the signal CLK, the phase signal A, and the signal 108 obtained by delaying the phase signal A by a time corresponding to one pulse of the signal CLK, the output signal 106 of the XOR gate 102A, and the output signal CLKE from the AND gate 105 are shown. Has been. The output signal 106 is an exclusive OR.

  In the circuit 107, the flip-flop 101A delays the input phase signal A by one pulse of the signal CLK, and generates and outputs an output signal 108. The output signal 108 corresponds to the phase signal A delayed by one pulse of the clock signal. As described above, the flip-flops 101A to 101D are examples of delay elements that delay each signal of the parallel signal.

  The XOR gate 102A calculates an exclusive OR of the output signal 108 and the phase signal A, and generates and outputs a signal 106. Therefore, the XOR gates 102A to 102D are an example of an exclusive OR operation element that generates an exclusive OR of each signal of the parallel signal and each signal delayed by the delay element.

  The output signal 106 is a signal that becomes 1 (High) at the transition point of the phase signal A from 0 to 1 or from 1 to 0. That is, the circuit 107 is a circuit that detects or extracts a displacement point of the input phase signal A.

  The output signal 106 from the XOR gate 102A is input to the OR gate 103. The OR gate 103 outputs the output signal 106 as it is to the AND gate 105 if any of the input signals other than the output signal 106 (output signals from the XOR gates 102B to 102D) is zero. In this manner, the OR gate 103 is an example of a logical sum operation element that generates a logical sum of an exclusive OR for the first single signal and an exclusive OR for the second single signal.

  The AND gate 105 calculates and outputs a logical product of the output signal of the OR gate 103 and the signal CLK intentionally generated by the delay buffer 104. The output signal CLKE of the AND gate 105 becomes an output signal (that is, a serial signal) of the coder 901A or the coder 901B. As described above, the AND gate 105 is an example of an AND operation element that generates a logical product of the logical sum and the clock signal as a serial signal.

  FIG. 11 is a timing chart showing the waveform of the serial signal CLKE in a state where a general 1-2 phase excitation pattern is input to the coder 901A or 901B. The excitation pattern shown in FIG. 11 is a pattern for rotating the motor at a constant speed. FIG. 11 also shows that the number of pulses of the serial signal CLKE is appropriately thinned out with respect to the signal CLK. It can also be seen that the serial signal CLKE is a periodic pulse signal.

  The serial signal CLKE is a periodic pulse, but its frequency is significantly lower than that of the CLK. In general, the lower the frequency of the signal transmitted through the cable, the lower the energy of the radiated noise.

  FIG. 12 is a timing chart showing the waveform of the serial signal CLKE when the 1-2 phase excitation pattern is an acceleration pattern. According to FIG. 12, the number of pulses of the serial signal is appropriately reduced with respect to the signal CLK. Further, the serial signal CLKE is not a periodic pulse signal. By making the serial signal CLKE such a pulse signal, almost no radiation noise is generated. Generally, when the frequency component of radiation noise is biased only to a specific frequency, the level of radiation noise tends to increase. In the present embodiment, since such a bias is alleviated, radiation noise is reduced.

  Returning to FIG. The output signals of the coders 901A and 901B are transmitted (output) to the motor driver board 307A via the connector 902, the cable 903, and the connector 904. As described above, the coders 901A and 901B function as a conversion unit that converts a parallel signal composed of a predetermined permutation into a serial signal and a transmission unit that transmits the serial signal.

  The received output signals (serial signals) of the coders 901A and 901B are input to the decoders 905A and 905B mounted on the motor driver board 307A, respectively. The decoder 905A or 905B functions as a receiving unit that receives the serial signal transmitted by the transmitting unit, and a restoring unit (reproducing unit) that restores the serial signal received by the receiving unit to the original parallel signal.

  FIG. 13 is a diagram illustrating an example of the decoder 905A or 905B. The selector 1301 is a selector having nine input terminals and four output terminals. The bit width of each input terminal is 4 bits or 3 bits. The bit width of each output terminal is 1 bit. The registers 1302A to 1302H are connected to any one input terminal of the selector 1301, respectively. When a control element such as a CPU is not mounted on the motor driver board 307A, each register may be configured to output a fixed value.

  The counter 1303 is a counter that performs counting in accordance with the input serial signal CLKE. The count value is 3 bits and is input to the selector 1301.

  FIG. 14 is a timing chart showing a general 1-2 phase excitation pattern. One cycle of the excitation pattern is a range indicated by an arrow. The excitation pattern (phase signal group) can be regarded as a 4-bit signal. At this time, the phase signal A is assigned to the most significant bit. Similarly, the phase signal A * is assigned to the second bit. Phase signal B is assigned to the third bit. Phase signal B * is assigned to the least significant bit. Thus, if the excitation pattern (phase signal group) is regarded as a 4-bit signal, the excitation pattern repeats changing in the order of 9, 8, A, 2, 6, 4, 5, 1 in hexadecimal ( FIG. 14). Therefore, the registers 1302A to 1302H store 9, 8, A, 2, 6, 4, 5, 1 in hexadecimal.

  The counter 1303 counts up for each pulse of the input serial signal CLKE, and outputs a 3-bit count value. The output 3-bit count value is input to the selector 1301. The selector 1301 selects and outputs one of the signals input from the registers 1302A to 1302H according to the input count value.

  Note that the count value of the counter 1303 starts from 0 and changes to 1, 2, 3, 4, 5, 6, 7, 0, 1, 2,. The numerical value shown for each input terminal of the selector 1301 corresponds to the count value of the counter 1303. Therefore, the counter 1303 selects the output value from the register connected to the input terminal corresponding to the count value, and outputs it as A, A *, B, B * in order from the upper bit. That is, among the 4-bit output values from the register, the most significant bit corresponds to A, the second bit corresponds to A *, the third bit corresponds to B, and the least significant bit to B *. It corresponds.

  Thus, the counter 1303 is an example of a counter that performs counting according to the serial signal received by the receiving unit. Similarly, the selector 1301 is an example of a reproducing unit that reproduces the original parallel signal from the serial signal in accordance with the count value of the counter.

  Returning to FIG. The phase signal groups restored by the decoders 905A and 905B are amplified by the corresponding motor driver ICs 408A and 408B, and output to the stepping motors 410A and 410B via the connectors 409A and 409B, respectively. The stepping motors 410A and 410B are controlled (driven) to rotate according to the input phase signals.

  According to the present embodiment, by converting a parallel signal composed of a plurality of phase signals into a serial signal, it is not necessary to transmit / receive a synchronous clock that has been conventionally required simultaneously with the serial signal. In particular, according to the present embodiment, a serial signal representing a displacement point of a parallel signal is generated and restored to a parallel signal composed of a predetermined permutation based on the serial signal. Therefore, the frequency of the signal transmitted by serial communication is reduced, and radiation noise is also reduced. In addition, since the number of bundled wires required for transmission and reception can be reduced, the configuration of the bundled wires can be simplified and the cost can be reduced.

  According to the present embodiment, the conversion means can be realized by a delay element or a logic operation element, so that the cost can be easily reduced. Similarly, according to the present embodiment, the restoration means can be realized by a counter, a register, a selector, and the like, so that the cost can be easily reduced.

  In addition, since the serial communication system and serial transmission device of the present embodiment can be mounted on a stepping motor drive device, an image reading device, and a copying device, it is easy to achieve both high-speed processing and reduced malfunction due to radiation noise. Let's go. The stepping motor is merely an example, and other motors may be employed.

[Embodiment 2]
Since most of the motors used in the image forming apparatus have one direction of rotation, the driving device of Embodiment 1 can be employed. On the other hand, the image reading apparatus is required to rotate the motor forward or backward. Therefore, in the second embodiment, a serial communication system and a driving device that can reversely rotate a motor will be described.

  FIG. 15 is a diagram illustrating an example of the drive device according to the embodiment. The parts already described are given the same reference numerals to simplify the description. In particular, according to FIG. 15, designation signals 1CW and 2CW for designating forward rotation or reverse rotation are output from the CPU 302A on the main board 301B. The designation signals 1CW and 2CW are input to the motor driver board 307B. The designation signal 1CW is a rotation direction designation signal that designates the rotation direction of the stepping motor 410A. The designation signal 2CW is a rotation direction designation signal that designates the rotation direction of the stepping motor 410B. When the designation signals 1CW and 2CW are 0, it means that the motor rotates forward, and when it is 1, it is a logic signal that means reverse rotation.

  These designation signals 1CW and 2CW are input to the decoders 1505A and 1505B via the connector 1502, the cable 1503, and the connector 1504, respectively. Compared to the first embodiment, in the second embodiment, the cable 1503 also includes signal lines for transmitting the designation signals 1CW and 2CW.

  FIG. 16 is a diagram illustrating an example of the decoder 1505A or 1505B according to the embodiment. The parts already described are given the same reference numerals to simplify the description. In particular, the counter 1601 is an up / down counter that switches whether to count up or down according to a rotation direction designation signal.

  The counter 1303 shown in FIG. 13 is an up counter that performs counting such as 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2,. On the other hand, the up / down type counter 1601 shown in FIG. 16 counts up when the designation signal CW is 0, and counts down when it is 1.

  FIG. 17 is a timing chart showing the relationship between the phase signals A, A *, B, B * reproduced by the selector 1301 and the designation signal CW. The count value of the counter 1601 starts from 0. The selector 1301 selects and outputs the input signal “9” corresponding to 0 that is the count value. Each time a pulse of the serial signal CLKE is input, the counter 1601 counts up 1, 2, 3, 4, and so on. The selector 1301 selects and outputs an input signal from an input terminal corresponding to the count value.

  At the timing when the rotation direction designation signal CW changes from 0 to 1, that is, when the count value of the counter 1601 is 1, the counter 1601 functions as a down counter. Therefore, when the next pulse of the serial signal CLKE is input, the counter 1601 outputs 0 and sequentially outputs 7, 6, 5, 4, 3, 2, 1, 0, 7, 6.

  The selector 1301 selects the registers 1302A to 1302H according to the input count value, and reproduces and outputs the phase signals A, A *, B, and B *.

  According to this embodiment, by adding one signal line for designating the rotation direction of the motor per motor, the rotation direction of the motor can be controlled.

  In particular, the rotation direction can be controlled by switching whether the counter 1601 counts up or down according to a rotation direction designation signal that designates whether the motor is rotated forward or reverse. Therefore, although the necessary minimum signal lines are added, the designation signals 1CW and 2CW do not have frequency components, so that it is possible to maintain the radiation noise reduction effect as in the first embodiment.

FIG. 2 is a diagram illustrating a schematic configuration of an image reading apparatus 100. It is the figure which showed the drive device of the stepping motor which employ | adopted parallel transmission. It is the figure which showed the drive device of the stepping motor which employ | adopted serial communication. It is the figure which showed the detail of parallel serial converter 402A and 402B. It is a timing chart of a parallel serial converter. It is the figure which showed the detail of parallel serial converter 402A and 402B. It is a timing chart of a serial-parallel converter. It is the block diagram which showed an example of the drive device of the stepping motor which concerns on embodiment. It is a figure which shows an example of the coders 901A and 901B which concern on embodiment. 10 is a timing chart of the circuit 107. It is the timing chart which showed the waveform of the serial signal CLKE in the state which input the general 1-2 phase excitation pattern to the coder 901A or 901B. It is the timing chart which showed the waveform of the serial signal CLKE when the 1-2 phase excitation pattern is an acceleration pattern. It is a figure which shows an example of decoder 905A or 905B. It is the timing chart which showed the general 1-2 phase excitation pattern. It is the figure which showed an example of the drive device which concerns on embodiment. It is a figure which shows an example of the decoder 1505A or 1505B which concerns on embodiment. 4 is a timing chart showing the relationship between phase signals A, A *, B, B * reproduced by a selector 1301 and a designation signal CW.

Explanation of symbols

101A to 101D ... D type flip-flops 102A to 102D ... XOR gate 103 ... OR gate 104 ... delay buffer 105 ... AND gates 301 and 301A ... main substrates 302 and 302A ...・ CPU
303 ... System clocks 307 and 307A ... Motor driver boards 310 and 408A to 408B ... Motor driver ICs
312 and 410A-410B ... stepping motors 402A-402B ... parallel-serial converters 406A-406B ... serial-parallel converters 501A-501D ... D type flip-flops 502A-502D ... selectors 701A- 701D ... D-type flip-flop 702 ... 4-bit flip-flop 901A-901B ... coder 905A-90B ... decoder 1301 ... selector 1302A-1302H ... register 1303 ... counter

Claims (9)

A serial communication system,
Conversion means for converting a parallel signal composed of a predetermined permutation into a serial signal;
Transmitting means for transmitting the serial signal;
Receiving means for receiving the serial signal transmitted by the transmitting means;
Restoring means for restoring the serial signal received by the receiving means to the original parallel signal,
The serial communication is characterized in that the conversion means generates a serial signal representing a displacement point of the parallel signal, and the restoration means restores the parallel signal composed of the predetermined permutation based on the serial signal. system. The converting means includes
Detecting means for detecting a displacement point of each signal constituting the parallel signal;
The serial communication system according to claim 1, further comprising: a generation unit that generates a pulse signal when the displacement unit is detected by the detection unit. The detection means includes
A delay element for delaying each of the parallel signals;
An exclusive OR operation element that generates an exclusive OR of each signal and each signal delayed by the delay element;
The generating means includes
A logical sum operation element for generating a logical sum from the exclusive OR of the signals;
The serial communication system according to claim 2, further comprising: a logical product operation element that generates a logical product of the logical sum and the clock signal as the serial signal. The restoration means includes
A counter that performs counting according to the serial signal received by the receiving means;
4. The serial communication system according to claim 1, further comprising reproduction means for reproducing the original parallel signal from the serial signal in accordance with a count value of the counter. A signal line for transmitting a rotation direction designation signal for designating whether the motor controlled by the serial signal is rotated forwardly or reversely;
The serial communication system according to claim 4, wherein the counter switches whether to count up or down according to the rotation direction designation signal. A transmission device used in a serial communication system,
Conversion means for converting a parallel signal composed of a predetermined permutation into a serial signal;
Transmission means for transmitting the serial signal,
The transmission device, wherein the conversion means generates a serial signal representing a displacement point of the parallel signal. A driving device for driving a motor,
A first substrate;
A second substrate;
Conversion means mounted on the first substrate and converting a parallel signal including a plurality of phase signals for controlling the motor into a serial signal;
Transmitting means mounted on the first substrate and transmitting the serial signal;
Receiving means mounted on the second substrate and receiving a serial signal transmitted by the transmitting means;
Restoring means mounted on the second substrate and restoring the serial signal received by the receiving means to the original parallel signal;
Drive means for driving the motor based on the parallel signal mounted on the second substrate and restored by the restoration means;
The conversion unit generates a serial signal representing a displacement point of the parallel signal, and the restoration unit restores the parallel signal composed of the predetermined permutation based on the serial signal. . An image reading device,
A motor for moving the optical system relative to the document;
An image reading apparatus comprising: the driving device according to claim 7 that drives the motor. A serial communication method,
A conversion step of converting a parallel signal composed of a predetermined permutation into a serial signal;
A transmission step of transmitting the serial signal;
A receiving step for receiving the serial signal transmitted by the transmitting step;
A restoration step of restoring the serial signal received by the reception step to the original parallel signal,
The conversion step includes a step of generating the serial signal representing a displacement point of the parallel signal, and the restoration step includes a step of restoring the parallel signal composed of the predetermined permutation based on the serial signal. A serial communication method characterized by the above.

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