JP3841331B2 - Image reading apparatus and image processing apparatus including the image reading apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image reading apparatus that can be applied to an image processing apparatus such as a scanner, a digital copying machine, and a facsimile. More specifically, the present invention relates to processing image data while reducing radiation noise caused by a drive clock used for processing read image data. The present invention relates to image data processing technology that reduces transmission errors and improves image data quality.
[0002]
[Prior art]
2. Description of the Related Art Image reading apparatuses that image a target image such as a document on a line image sensor by a scanning optical system and perform photoelectric conversion and image processing are conventionally known. In a conventional image reading apparatus, photoelectric reading of an image, and A series of image data processing is performed to convert and process the read image signal into usable data.
This series of image data processing is performed while synchronizing under the control of the CPU that controls the whole. For this reason, the CPU controls the timing generator to generate an operation clock used for driving each conversion / processing circuit based on the reference clock generated by the reference oscillator. Therefore, the harmonics of the reference clock generated by each operation clock generated by the timing generator may be generated at a level that cannot be ignored as radiation noise, and reduction of such radiation noise is required.
[0003]
As a countermeasure against such radiated noise, a method of reducing the radiated noise by frequency-modulating a reference clock and generating each timing signal based on the modulated clock is considered.
FIG. 8 shows an example of the prior art of an image data processing circuit of a low radiation noise image reading apparatus employing this method.
This image data processing circuit is mounted on one substrate, and as shown in FIG. 8, a CCD linear image sensor (or CCD line image sensor, hereinafter referred to as “CCD”) 1, SH (sample hold) & line clamp ( Alternatively, a pixel clamp) 21, a GCA (gain control amplifier) 22, a DRV (driver) & line clamp 23, an analog signal processing circuit 2, an ADC (analog / digital converter) 3, and an LVDS (Low Voltage Differential Signals). Conversion) circuit 4, reference oscillator 6, jitter generation circuit 7 'and timing generator 5.
In the preceding example shown in FIG. 8, the DC potential after the AC coupling is sampled and held by the SH & line clamp 21 with respect to the output signal of the CCD 1 having two outputs (even and odd) to suppress the fluctuation of the signal. Each time the potential is clamped to define the signal. The image signal output of the SH & line clamp 21 is adjusted to the output amplitude of the ADC 3 by the GCA 22, and the offset generated by the GCA 22 is absorbed by the line clamp again by the DRV & line clamp 23, and the ADC 3 is driven by the DRV. Further, the output of the ADC 3 is converted into a low-amplitude serial differential signal by the LVDS circuit 4 and output to the outside of the substrate.
The operations of these conversion / processing circuits are controlled by timing signals generated by the timing generator 5. The timing generator 5 operates each conversion / processing circuit based on the output (REF_CK) of the reference oscillator 6 and based on the clock (JIT_CK) provided with jitter by the jitter generation circuit 7 '(frequency modulated). The timing signal to be generated is generated.
[0004]
FIG. 10 illustrates the configuration of the circuit on the driver side of the LVDS circuit 4. FIG. 11 is a timing chart of signals at various parts in the driver side circuit of the LVDS shown in FIG.
As shown in FIG. 10, this circuit includes a clock generator 42 having a clock frequency multiplication rate corresponding to the number of bits to be converted to serial, and a parallel-serial converter 41 for converting a parallel input signal into a serial signal.
The clock generation unit 42 generates an operation clock for the parallel-serial conversion unit 41 based on the input clock CKI, and at the same time as the output of serial data transmission from the parallel-serial conversion unit 41, the timing clock SCK is sent to the next stage (receiver). Side). Therefore, PC (phase comparator) 421, LP (loop filter) 423, VCO (voltage control oscillator) 422, 8SP (8-bit serial-parallel conversion circuit) 424, 7NOR425, 4NOR426, 1LH (1-bit latch) 427 and output A buffer 428 is provided as a component.
The parallel-serial conversion unit 41 converts the input parallel data DI7: 0 into serial data SDO according to the operation clock (LCK, CLK) from the clock generation unit 42, and transmits it to the next stage (receiver side). Therefore, 8LH (8-bit latch) 411, 8PS (8-bit parallel-serial conversion circuit) 412 and an output buffer 413 are provided as components.
[0005]
The operation of the LVDS driver will be described with reference to the timing chart of FIG.
First, the parallel data DI7: 0 input to the parallel-serial converter 41 is latched into the 8LH 411 according to the latch clock LCK generated based on the clock CKI input to the clock generator 42.
Next, the data DI7: 0 latched and output in the 8LH 411 is input to the 8PS 412, converted into serial data SDO by the operation clock CLK generated based on the clock CKI, and output. In this case, the clock CLK for operating the 8PS 412 is an operation clock having a frequency multiplication factor obtained by multiplying the input clock CKI by 8 since the input parallel data is 8-bit data, and is composed of the PC 421, the LP 423, and the VCO 422. Output from the PLL circuit. Thereafter, the serial data SDO output from the 8PS 412 is transmitted to the receiver side as SD +/− via the output buffer 413.
In parallel with the operation of outputting the operation clock to the parallel-serial conversion unit 41, the clock generation unit 42 generates the timing clock SCK synchronized with the input / output operation of the parallel data unit in the parallel-serial conversion unit 41 by the 1LH 427, and outputs the output buffer 428. To the receiver side as SC +/−.
[0006]
FIG. 12 illustrates a circuit configuration on the receiver side of the LVDS circuit 4. FIG. 13 is a timing chart of signals at various parts in the receiver side circuit of the LVDS shown in FIG.
As shown in FIG. 12, this circuit includes a clock generator 82 having a clock frequency multiplication rate corresponding to the number of bits to be converted in parallel, and a serial-parallel converter 81 for converting a serially input signal into a parallel signal.
The clock generation unit 82 generates an operation clock of the serial-parallel conversion unit 81 based on the timing clock CKI transmitted from the LVDS driver as SC +/− and input via the input buffer 828, and from the serial-parallel conversion unit 81. The timing clock CKO is output to the processing circuit at the next stage in synchronization with the output of the parallel data. Therefore, PC (phase comparator) 821, LP (loop filter) 823, VCO (voltage control oscillator) 822, 8SP (8-bit serial-parallel conversion circuit) 424, 8SP [1] (8-bit serial-parallel conversion circuit) 824, 7NOR825, 4NOR826, and 1LH (1-bit latch) 827 are provided as constituent elements.
Further, the serial-parallel converter 81 is transmitted as SD +/− from the LVDS driver, and the serial data SDI input through the input buffer 813 is converted into parallel data DO7: 0 according to the operation clock (CLK, CKO) from the clock generator 82. Convert and output to the processing circuit of the next stage. Therefore, 8SP [2] (8-bit serial-parallel conversion circuit) 811 and 8LH (8-bit latch) 812 are provided as constituent elements.
[0007]
The operation of the LVDS receiver will be described with reference to the timing chart of FIG.
First, the serial data SDI input to the serial-parallel converter 81 is sequentially shifted to the 8SP [2] 811 register in accordance with the operation clock CLK generated based on the clock CKI input to the clock generator 82, and parallel. Expand to data. In this case, the clock CLK for performing the shift operation in 8SP [2] 811 is an operation clock having a frequency multiplication factor obtained by multiplying the input clock CKI by 8 according to the number of bits since the input parallel data is 8-bit data. This is output from a PLL circuit composed of the PC 821, LP 823, and VCO 822.
Next, the parallel data DI0-7 developed at 8SP [2] 811 and appearing at the outputs D0-7 are input to 8LH812, latched by the operation clock CKO generated based on the clock CKI, and output parallel. Data DO7: 0 is output to the subsequent processing stage.
Further, in parallel with the operation of outputting the operation clock to the serial-parallel conversion unit 81, the clock generation unit 82 generates the timing clock CKO synchronized with the input / output operation of the parallel data unit in the serial-parallel conversion unit 81 by 1LH827, and the subsequent processing Output to stage.
[0008]
[Problems to be solved by the invention]
In the read image data processing circuit including the above LVDS circuit, as shown in FIG. 8, the entire processing circuit is operated with reference to a clock having jitter, so that the spectrum of radiated noise is diffused. The radiation noise intensity is reduced, and the image can be read with low radiation noise.
However, the timing of the generated clock varies depending on the jitter modulation width, which may cause malfunction. FIG. 9 is a timing chart of signals in the circuit of FIG. 1, and hatched lines are written in the respective signal diagrams of FIG. 1, and this period represents the fluctuation range of jitter. As shown in FIG. 9, since the parallel data (Dad_e, Dad_o) and the operation clock ADCLK input to the LVDS circuit 4 both have a fluctuation range due to jitter, serial data (converted by the LVDS circuit 4 and output) DIv_e, DIv_o) and the internal multiplication clock (Iv_clk) also have a fluctuation range due to jitter. Therefore, the timing margin between the serial data to be output and the LVDS internal multiplication clock is reduced, and a data transmission error occurs in some cases.
The present invention has been made in view of the above-described problems of the prior art in an image reading apparatus having an image data processing circuit with low radiation noise, and its object is to suppress data transmission errors while suppressing radiation noise. An image reading apparatus capable of improving the quality of image data by processing read image data that can reduce the influence of errors or an image processing apparatus (for example, a scanner) including the image reading apparatus Digital copiers, facsimiles, etc.).
[0009]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided an image processing circuit including at least a line image sensor, an AD converter for converting an image signal output from the line image sensor into digital image data, and converting the digital image data into a low-amplitude serial differential signal. An image reading apparatus comprising a serial signal conversion circuit for outputting and outputting, and an operation clock generation circuit for generating a clock for operating the image processing circuit and the serial signal conversion circuit, wherein the operation clock generation circuit includes a reference clock and the reference clock An image reading apparatus characterized by generating a modulation clock having a predetermined frequency modulation applied thereto, outputting the generated modulation clock to the image processing circuit, and outputting a reference clock to the serial signal conversion circuit. is there.
[0010]
According to a second aspect of the present invention, there is provided an image processing circuit including at least a line image sensor, an AD converter for converting an image signal output from the line image sensor into digital image data, and converting the digital image data into a low-amplitude serial differential signal. In an image reading apparatus comprising a serial signal conversion circuit for outputting and an operation clock generation circuit for generating a modulation clock obtained by applying a predetermined frequency modulation to a reference clock as a clock for operating the image processing circuit and the serial signal conversion circuit, The serial signal conversion circuit is an image reading apparatus in which input data is serially converted by changing the order of data bits for each processing unit data between the LSB side and the MSB side.
[0011]
According to a third aspect of the present invention, there is provided an image processing circuit including at least a line image sensor, an AD converter for converting an image signal output from the line image sensor into digital image data, and converting the digital image data into a low-amplitude serial differential signal. In an image reading apparatus comprising a serial signal conversion circuit for outputting and an operation clock generation circuit for generating a modulation clock obtained by applying a predetermined frequency modulation to a reference clock as a clock for operating the image processing circuit and the serial signal conversion circuit, The serial signal conversion circuit is an image reading apparatus in which input data is multiplexed in bit units and serially converted.
[0012]
According to a fourth aspect of the present invention, in the image reading apparatus according to the third aspect, the multiplexing is performed on a bit portion on the MSB side of the input data.
[0013]
A fifth aspect of the present invention is an image processing apparatus comprising the image reading apparatus according to any one of the first to fourth aspects.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described based on the following examples shown with the accompanying drawings.
FIG. 1 shows a configuration of an embodiment of an image data processing circuit of a low radiation noise image reading apparatus according to the present invention. Note that the same reference numerals and designations are used for the same components as in the preceding example (FIG. 8), and the preceding example is referred to for the description thereof.
In FIG. 1, the processing of the read image data up to the CCD 1, the analog processing circuit 2 and the ADC 3 is performed by the timing signal generated by the timing generator 5 based on the clock provided with jitter by the jitter generating circuit 7 as in the prior art. The action is performed.
The difference from the previous example was that a clock with jitter was input to the operation clock to the LVDS circuit following ADC 3 in the previous example, but in the LVDS circuit of this embodiment, a jitter generation circuit is used. It is operated by a clock (LVCLK) without modulation, that is, without jitter.
[0015]
FIG. 2 is a timing chart of signals in the circuit of FIG. 1. The parallel data (Dad_e, Dad_o) and the conversion clock ADCLK of the ADC 3 input to the LVDS circuit 4 of FIG. Although hatched lines are written in the diagram, LVCLK has no fluctuation range due to jitter. As shown in FIG. 2, the relationship between LVCLK and the conversion clock ADCLK is such that LVCLK is a clock having no jitter in phase opposite to that of ADCLK changing at the center of jitter of ADCLK. The center of the data change point that is not affected by jitter is latched. Therefore, in a series of image data processing, the processing after the LVDS circuit can be operated with a sufficient timing margin as in the case where there is no jitter in the reference clock as a whole, and a transmission error that may occur in the preceding example. Can be eliminated.
[0016]
Next, another embodiment of the image data processing circuit of the low radiation noise image reading apparatus will be described.
This embodiment is characterized by the configuration of the LVDS circuit, and is an LVDS circuit that is one of a series of image data processing circuits of an image reading apparatus operated by a timing signal generated based on a clock having jitter. The object of the present invention is to reduce the influence of a transmission error caused by jitter that can occur in the preceding example, which can be suitably implemented (for example, can be applied to the LVDS circuit of FIG. 8 shown as the preceding example).
FIG. 3 illustrates the circuit configuration of the driver side of the LVDS circuit of this embodiment.
FIG. 4 illustrates a circuit configuration on the receiver side of the LVDS circuit of this embodiment.
FIG. 5 is a timing chart of signals at various parts in the LVDS circuit shown in FIGS.
[0017]
As shown in FIG. 3, the driver-side circuit has two systems of 8LH_A401, 8LH_B402 (8-bit latches each enabling output), FF (flip-flop) 403, and LVDS DRV (8-bit parallel-serial converter). LVDS driver) 404.
As shown in FIG. 4, the circuit on the receiver side is composed of LVDS REC (LVDS receiver having two 8-bit serial-parallel conversion units) 801 and 8LH_A 802 and 8LH_B 803 (8-bit latches each enabling output).
[0018]
The detailed configuration of the LVDS circuit (driver and receiver) and its operation will be described with reference to the timing chart of FIG.
First, the parallel data DI7: 0 input to the driver circuit is connected to the input terminal D7: 0 of 8LH_A401 and also connected to the input terminal D0: 7 of 8LH_B402, that is, the upper and lower bits are inverted, respectively. Latch input.
The FF 403 outputs a signal obtained by dividing the input clock CKI from Q and QB, and inputs them to the OEs of 8LH_A 802 and 8LH_B 803, thereby enabling the latch outputs of 8LH_A 802 and 8LH_B 803 alternately every clock. .
The outputs Q7: 0 of 8LH_A 802 and 8LH_B 803 are connected in parallel to the input D07: 0 of LVDS DRV404, the output is valid when the OE signal is “H”, and becomes high impedance when “L”. The output is invalid. By this operation, the input D07: 0 of the LVDS DRV 404 becomes a data input in which the MSB side and the LSB side of the input parallel data DI7: 0 are switched every clock.
In addition, the OE signal of 8LH_A 802 (Q output of FF403) is also input to D17: 10 of LVDS DRV404.
8LH_A802, 8LH_B803 latched MSB side and LSB side data is alternately input to LVDS DRV404 input D07: 0 every CKI clock, and at the same time, 8LH_A802 OE signal is input to LVDSDRV404 D17: 10 These input data are converted by the two 8-bit parallel-serial converters of the LVDS DRV 404, respectively, and "H" and "L" in the serial data SDO +/- and 8-bit serial data units as shown in FIG. Data SD1 +/− that repeats “is transmitted to the receiver side.
Further, the timing clock CKI input as the operation clock of this circuit is also input to the LVDS DRV 404, the timing clock SC +/− is generated based on this clock, and this is output to the serial data SDO +/− and data SD1 +/−. Transmit to the receiver side as a synchronized operation clock.
[0019]
In the receiver circuit that receives data SDO +/−, SD1 +/− and timing clock SC +/− transmitted from the driver circuit, serial data SDO +/− corresponding to D07: 0 on the driver side and serial data corresponding to D17: 10 SD1 +/− is converted into parallel data D07: 0 and D17: 10 by two 8-bit serial-parallel converters of LVDS REC801 on the receiver side, and then D07: 0 is input in parallel to 8LH_A802 and 8LH_B803. As for D17: 10, D17 is input to the OE of 8LH_A802, and the inverted signal of D17 is input to the OE of 8LH_B803. The outputs of 8LH_A 802 and 8LH_B 803 are connected so that Q7 of 8LH_A 802 is connected to DO7 so that Q0 becomes DO0 in the order of data, and Q0 of 8LH_B 803 is connected to DO7, and so that Q7 becomes DO0 in the order of data. On the other hand, when D17 is “H”, the output of 8LH_A 802 is valid, and when it is “L”, the output of 8LH_B 803 is valid, so that DO7: 0 restores the input data DI7: 0 to the driver. In other words, the MSB side and the LSB side of the input parallel data DI7: 0 are switched at every clock on the driver side, and the original data is output as serial data by switching the MSB side and the LSB side at the receiver side. Return to parallel data in a row.
As described above, by transmitting by serial data in which the MSB side and the LSB side are exchanged, the bit order in the serial data is the order of bit 7/6/5/4/3/2/1/0 for DIn-1. Since the next data DIn is output in the order of bit 0/1/2/3/4/5/6/7, when an error occurs, the most significant MSB (bit 7) is the next data It is adjacent to the MSB, and even if an error occurs, the possibility of changing to the MSB of the next data increases. Since general image data has little change in the MSB, even if an error occurs, the influence on the image can be kept small.
[0020]
Next, another embodiment of the image data processing circuit of the low radiation noise image reading apparatus will be described.
This embodiment is characterized by the configuration of the LVDS circuit, and is an LVDS circuit that is one of a series of image data processing circuits of an image reading apparatus operated by a timing signal generated based on a clock having jitter. The object of the present invention is to reduce the influence of a transmission error caused by jitter that can occur in the preceding example, which can be suitably implemented (for example, can be applied to the LVDS circuit of FIG. 8 shown as the preceding example).
FIG. 6 exemplifies the configuration of the LVDS circuit of this embodiment. In FIG. 6, (A) shows the driver side, and (B) shows the receiver side.
FIG. 7 is a timing chart of signals at various parts in the LVDS circuit shown in FIG.
As shown in FIG. 6A, the driver side circuit includes an LVDS DRV (LVDS driver having a 16-bit parallel-serial conversion unit) 407.
Further, as shown in FIG. 6B, the circuit on the receiver side includes an LVDS REC (LVDS receiver having a 16-bit serial-parallel conversion unit) 807.
[0021]
The detailed configuration of the LVDS circuit (driver and receiver) and its operation will be described with reference to the timing chart of FIG.
The input parallel data of LVDS DRV407 is 8 bits of DI7: 0, and DI7: 4 therein is connected and multiplexed to D15: 13, D12: 10, D9: 7, and D6: 4, respectively. A timing clock CKI input as an operation clock together with input parallel data is multiplied for a 16-bit parallel-serial conversion operation and used as an operation clock.
The input parallel data partially multiplexed by the parallel conversion unit of the LVDS DRV407 is serial-converted, and the converted serial data is bit7 / 7/7/6/6/6/5/5 as shown in FIG. Are output in the order of / 5/4/4/4/3/3/2/1/0, and transmitted to the receiver side as serial data SD +/-. The timing clock CKI input as the operation clock of this circuit is simultaneously transmitted to the receiver side as the operation clock SC +/− synchronized with the serial data SD +/− output.
[0022]
In the LVDS REC 807, the serial data SD +/− transmitted from the LVDS DRV 407 is converted into 16-bit parallel data D15: 0 by a 16-bit serial-parallel conversion unit. The conversion operation is performed at the timing of the operation clock SC +/− transmitted at the same time. The 16-bit parallel data output of the conversion unit is bit7 / 7/7/6/6/6/5/5/5/5/4/4/4/3/2/1/0. The final output data is returned to the original 8-bit parallel data with D14 of the output of LVDS REC807 set to DO7, D11 set to DO6, D8 set to DO5, D5 set to DO4, and D3: 0 set to DO3: 0.
As described above, since DI7: 4 is multiplexed and transmitted as 16-bit serial data, even if an error occurs during transmission and serial-parallel conversion is shifted by 1 bit, DO7: 4 is not included in the serial signal. Since the adjacent bits are the same, the same DI7: 4 is output as a result. Therefore, even if the MSB side is multiplexed and a bit error occurs due to jitter, the demodulated data does not include an error, and even if an error occurs on the LSB side, the effect on the image is small. The effect on this can be greatly reduced.
[0023]
【The invention's effect】
(1) Effects corresponding to the invention of claim 1
According to the present invention, the operation clock of an image processing circuit including at least a line image sensor other than a serial signal conversion circuit (LVDS circuit) that converts digital image data into a low-amplitude serial differential signal (LVDS circuit) and an AD converter has jitter. Radiation noise is reduced compared to the case where the clock does not have jitter, and the LVDS circuit is operated with a reference clock without jitter, so bit errors caused by low-amplitude serial differential signals cause the clock to have jitter. This is similar to the case where there is no data transmission, can suppress the occurrence of a data transmission error, and can improve the image quality as compared with the case where a clock having jitter in the LVDS circuit is used.
(2) Effects corresponding to the invention of claim 2
According to the present invention, the LVDS circuit converts the bit order of the input data for each processing unit data by serially converting the LSB side and the MSB side, so that the MSB in the low-amplitude serial differential signal is the next. Since it is adjacent to the MSB of the next data, even if a bit error occurs due to jitter that occurs when the clock is jittered and the whole is operated, there is a high possibility that it will change to the next data MSB. Since the image data has little change in the MSB, the influence on the image can be reduced even if an error occurs.
(3) Effects corresponding to the inventions of claims 3 and 4
According to the present invention, the LVDS circuit multiplexes the input data bit by bit, that is, multiplexes in the time domain for serial conversion, so that even if an error occurs during transmission and the serial-parallel conversion is shifted by 1 bit, Since the adjacent bits in the low-amplitude serial differential signal are also the same, the possibility that the same data will be output as a result increases and errors are reduced, so the effect on the image can be reduced. I can do it. In addition, the influence can be reduced more effectively by multiplexing the MSB side.
(4) Effect corresponding to invention of Claim 5
By using the image reading apparatus according to any one of claims 1 to 4 as a component of an image processing apparatus, the effects (1) to (3) can be obtained by using an image processing apparatus such as a scanner, a digital copying machine, and a facsimile machine. In this case, the performance of the apparatus can be improved.
[Brief description of the drawings]
FIG. 1 shows a configuration of an embodiment of an image data processing circuit of a low radiation noise image reading apparatus according to the present invention.
FIG. 2 is a timing chart of signals related to the ADC and LVDS circuit shown in FIG.
FIG. 3 shows a configuration of an embodiment of an LVDS driver circuit for reducing the influence of a transmission error.
FIG. 4 shows a configuration of an embodiment of an LVDS receiver circuit for reducing the influence of a transmission error.
5 is a timing chart of signals at various parts in the LVDS circuit shown in FIGS. 3 and 4. FIG.
FIGS. 6A and 6B show the configuration of another embodiment of the LVDS circuit for reducing the influence of a transmission error. FIG. 6A shows the driver side and FIG. 6B shows the receiver side.
7 is a timing chart of signals at various parts in the LVDS circuit shown in FIG.
FIG. 8 shows a configuration of a prior example of an image data processing circuit of a low radiation noise image reading apparatus.
FIG. 9 is a timing chart of signals affected by jitter related to the ADC and LVDS circuit shown in FIG. 8;
10 shows a configuration example of a driver circuit of the LVDS shown in FIG.
11 is a timing chart of signals at various parts in the LVDS driver circuit shown in FIG.
12 shows a configuration example of the receiver circuit of the LVDS shown in FIG.
13 is a timing chart of signals at various parts in the receiver circuit of the LVDS shown in FIG.
[Explanation of symbols]
1 ... CCD linear (line) image sensor,
2 ... Analog processing circuit, 3 ... AD converter,
4 ... Low amplitude serial differential conversion (LVDS) circuit,
5 ... Timing generator, 6 ... Reference oscillator,
7, 7 '... Jitter generation circuit, 41 ... Parasiri conversion unit,
42, 82 ... clock generation unit, 81 ... serial-parallel conversion unit,
404, 407 ... LVDS DRV (driver) circuit,
801,807 ... LVDS REC (receiver) circuit.

Claims (5)

Line image sensor, image processing circuit including at least an AD converter for converting an image signal output from the line image sensor into digital image data, and a serial signal conversion circuit for converting the digital image data into a low-amplitude serial differential signal and outputting it And an operation clock generation circuit for generating a clock for operating the image processing circuit and the serial signal conversion circuit, wherein the operation clock generation circuit applies a predetermined frequency modulation to the reference clock and the reference clock. An image reading apparatus comprising: generating a modulation clock; outputting the generated modulation clock to the image processing circuit; and outputting a reference clock to the serial signal conversion circuit. Line image sensor, image processing circuit including at least an AD converter for converting an image signal output from the line image sensor into digital image data, and a serial signal conversion circuit for converting the digital image data into a low-amplitude serial differential signal and outputting it And an image reading apparatus including an operation clock generation circuit that generates a modulation clock obtained by applying a predetermined frequency modulation to a reference clock as a clock for operating the image processing circuit and the serial signal conversion circuit. An image reading apparatus characterized in that input data is serially converted by replacing the LSB side and the MSB side of the data bit sequence for each processing unit data. Line image sensor, image processing circuit including at least an AD converter for converting an image signal output from the line image sensor into digital image data, and a serial signal conversion circuit for converting the digital image data into a low-amplitude serial differential signal and outputting it And an image reading apparatus including an operation clock generation circuit that generates a modulation clock obtained by applying a predetermined frequency modulation to a reference clock as a clock for operating the image processing circuit and the serial signal conversion circuit. An image reading apparatus, wherein input data is multiplexed in bit units and serially converted. 4. The image reading apparatus according to claim 3, wherein the multiplexing is performed on the MSB side bit portion of the input data. An image processing apparatus comprising the image reading apparatus according to claim 1.

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