CN1315782A - Synchronous delay circuit and semiconductor integrated circuit device - Google Patents
Synchronous delay circuit and semiconductor integrated circuit device Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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Abstract
A synchronous delay circuit apparatus include two sets of synchronous delay circuits each including a first delay circuit chain for period measurement in which input clocks propagate and a second delay circuit chain for period reproduction and delay detection circuits for detecting the propagation delay time caused in propagating clocks from an input node to an output node of a clock propagation path to issue a control signal for halting propagation of the input clock signals to the respective synchronous delay circuits. Even if the propagation delay time in the clock propagation path becomes longer or shorter than the clock period, no discontinuity in the clocks supplied from the synchronous delay circuit to the clock propagation path.
Description
The present invention relates to a kind of clocking technique of semiconductor integrated circuit, the conductor integrated circuit device that particularly relates to a kind of synchronous delay circuit of control clock signal and have this synchronous delay circuit.
With the synchronous delay circuit of removing the clock frequency skew short lock in time, because of its simple circuit constitutes and less current sinking is applied in the high-frequency clock synchronous circuit.As this synchronous delay circuit, for example can be with reference to record document of the following stated etc.
[1] spy opens flat 8-237091 communique;
[2] spy opens flat 11-73238 communique;
[3] Jin-Man Han other, " Skew Minimization Techinique for256M-bit Synchronous DRAM and beyond. " 1996 Symp.onVLSI Circ.pp.192-193, pp.192-193.
[4] Richard B.Watson other, " Clock Buffer Chip with AbsoluteDelay Regulation Over pricrss and Environment Variations. " Proc.ofIEEE 1992 CICC (Custum Integrated Circuits Conference), 25.2.
[5] Yoshihiro OKAJIMA other., " Digital Delay Locked Loopand Design Technique for High-Speed Synchronous Interface. " IEICE TRANS.ELECTRON.., VOL.E79-C, NO.6 JUNE 1996pp.798-807.
Fig. 5 is the example that expression has the conductor integrated circuit device formation of synchronous delay circuit in the past.And formation shown in Figure 5 is based on that synchronous delay circuit that document [2] (spy opens flat 11-73238 communique) put down in writing constitutes.
The basic comprising of synchronous delay circuit 100 comprises: the cycle (delay) that clock pulse or pulse edge are advanced is measured the 1st delay circuit sequence 11 of usefulness; Pulse with the corresponding length of length of advancing in the 1st delay circuit sequence with pulse or pulse edge or the delay that pulse edge passes through are reproduced with the 2nd delay circuit sequence 12.
Formation shown in Figure 5 is: consider the skew etc. of the propagation delay time of clock trees 4, (tCTS is as Hou is stated to measure retardation tCTS with clock trees 4 with synchronous delay circuit 100, detect with delay detection circuit 5) time tCK-tCTS after from the clock cycle tCK of input clock 3, removing, even the propagation delay time tCTS of clock trees 4 changes, the clock that also can obtain input clock 3 and not have in fact to be offset.
When carrying out work such as semiconductor integrated circuit design, for the difference that makes the clock signal delay time minimizes, the most suitably insert and be used to make the buffer of clock signal cloth gauze delay equalizationization, carry out tree-shaped wires design, the designs that use is carried out according to so synthetic (Clock Tree Synthesis:CTS) methods etc. of clock trees of each clock use circuit such as clock signal being distributed to trigger etc., clock trees 4 is by being constituted by the clock routing circuit of tree-shaped wiring.And, in Fig. 5, be illustrated in the clock trees to the triangle symbol medelling of clock trees 4, for delay equalizationization and drive load and the buffer that inserts.And clock trees among the figure 4 is represented that by medelling much less, the progression of the buffer circuit that clock trees comprised is not limited to 4 grades.And in Fig. 5, A represents the input node of clock trees 4, B represent in the clock trees 4 as controlling object select fixed output node (for example the maximum delay node of clock trees 4 etc.).But, be configured in clock trees 4 locational clock transfer circuits and be not limited to utilize the clock of CTS method wiring etc. to transmit to use the signal routing circuit, also can be the wiring route of clock signal arbitrarily in semiconductor integrated circuit.
With reference to Fig. 5, in conductor integrated circuit device, when the input clock 3 (IN) that is provided by no illustrated clock driver etc. is input to the input node A of clock trees 4 by transducer 10, the delay detection circuit 5 that this clock signal is input to the 1st input should be exported D (also claiming " supervisory signal ") reset (also claiming dormant state), and delay circuit sequence 11 makes clock signal stop to advance.
Be input to the clock of the node A of clock trees 4, when after propagation delay time tCTS, arriving Node B, the delay detection circuit 5 of this clock signal being imported the 2nd input is accepted this output D to this output D set (calling the state of applying flexibly), and delay circuit sequence 11 is advanced clock.
Fig. 6 is the figure of formation one example of expression synchronous delay circuit 100 shown in Figure 5 and delay detection circuit 5.With reference to Fig. 6, it constitutes: synchronous delay circuit 100 comprises: constitute by a plurality of unit delay parts, transmit input clock (IN) pulse or pulse edge and can take out the 1st delay circuit sequence 11 of output from the optional position of transmission lines; Constitute by a plurality of unit delay parts, with clock pulse or pulse edge from the optional position input of transmission lines and the 2nd delay circuit sequence 12 that transmits; The control circuit sequence 18 that constitutes by a plurality of control circuits with signal input terminal, lead-out terminal and input and output control terminal; And the signal transmission line road of the 1st delay circuit sequence 11 and the 2nd delay circuit sequence 12 difference reverse configuration, by control circuit sequence 18, connect near the side of clock (IN) input of the 1st delay circuit sequence 11 and near the side of output terminal of clock of the 2nd delay circuit sequence 12 successively, after clock signal being imported the 1st delay circuit sequence 11, on the position of certain hour of having advanced, (imported the moment of next clock signal), signal is inputed to input and output control terminal to control circuit sequence 18 that should the position, the clock signal of in the 1st delay circuit sequence 11, advancing to position input that should advanced positions and be sent in the 2nd delay circuit sequence 12.
And, in the example shown in Figure 6, be reverse configuration though the formation that postpones to measure the delay circuit sequence 11 of usefulness and postpone used again delay circuit sequence 12 is set, much less be not limited to the formation in the described example.As well-known, utilize equidirectional a pair of delay circuit of advancing also can constitute synchronous delay circuit (can be with reference to above-mentioned each document etc.) about the details of other formations of synchronous delay circuit.
The 1st delay circuit sequence 11 of having imported clock pulse from input C, this clock pulse is advanced in the 1st delay circuit sequence 11, when importing the next clock pulse of this clock pulse, accept next clock pulse, control circuit sequence 18 is by activate, from the position that clock pulse is advanced in the 1st delay circuit sequence 11, by control circuit sequence 18 that should the position is sent to clock pulse in the 2nd delay circuit sequence 12, be sent to clock pulse in the 2nd delay circuit sequence 12 and the 2nd delay circuit sequence 12 in, advance, export towards the direction opposite with the direct of travel of clock pulse in the 1st delay circuit sequence 11.In example shown in Figure 7, clock at delay circuit sequence 11 inside-paints that postpone to measure usefulness in the hatched part delay circuit (3 delay circuit parts), advance to a direction (→), accept next clock input (IN), by having drawn hatched control circuit sequence 18, clock is sent to the used again delay circuit sequence 12 of delay, clock at delay circuit sequence 12 inside-paints hatched 3 delay circuits part advance, export to (←) in the other direction.
Delay detection circuit 5 is by the input node A that (R) terminal that resets is connected to clock trees 4, set (S) terminal is connected to the formations such as set-reset flip-floop (latch circuit) circuit of the output node B of clock trees 4, arrive the moment of the input node A of clock trees 4 in clock pulse, be reset, control signal D (supervisory signal) becomes low level, and work as the moment that clock pulse arrives the Node B of clock trees 4, and being set, control signal D becomes high level.
Below, with reference to the time variation diagram of Fig. 7 and Fig. 8 working condition with reference to the illustrated synchronous delay circuit in the past of Fig. 5 and Fig. 6 is described.
(tCTS＜tCK) became the time shown in Figure 7 and changes waveform than clock cycle tCK hour as the propagation delay time of clock trees 4 tCTS.In Fig. 7, IN represents input clock 3, and A represents the input node of clock trees 4, and B represents the clock signal waveform of the output node of clock trees 4.
At first, transducer 10 is selected clock 3 (IN), input node A from clock signal input clock tree 4, tCTS time of delay through clock trees 4, the output of delay detection circuit 5 is set to reset mode, unit delay part (clock control formula phase inverter) in the 1st delay circuit sequence 11 is set to closed condition, through after the tCTS, arrive the moment of the Node B of clock trees 4 when the clock signal, the output of delay detection circuit 5 is set to SM set mode, constitutes the state that the clock control formula phase inverter of the unit delay part in the 1st delay circuit sequence 11 becomes out.
In Fig. 7, the 1st clock of input clock IN, in the 1st delay circuit sequence 11, advanced moment of tCK-tCTS, accept the 2nd clock of input clock IN, from the position of (tCK-tCTS), through control circuit 18, be sent to the 2nd delay circuit sequence 12, the 2nd delay circuit sequence 12 makes clock advance, export in the recovery time (tCK-tCTS), is imported into the node A of clock trees 4 through transducer 10.
The rising edge clock that is imported into the node A of clock trees 4 is wanted the slow recovery time (tCK-tCTS) than input clock (IN).
Fig. 8 is the figure of the working condition of propagation delay time tCTS when tCK is big than the clock cycle of explanation clock trees 4.
At this moment, be input to moment of the node A of clock trees 4 from clock, through after the propagation delay time tCTS of clock trees 4, clock arrives Node B.Promptly, surpass 1 clock cycle (tCK), in the next clock cycle, to elapsed time tCTS-tCK deeply during, the 1st delay circuit sequence 11 is accepted the output of delay detection circuit 5, stopping clock transmitting, the moment of tCTS-tCK in the next clock cycle, the 1st delay circuit sequence 11 begins to transmit the clock (the 2nd clock of the input clock IN of Fig. 8) of input, before next clock pulse (the 3rd clock of the input clock IN of Fig. 8) is imported in the synchronous delay circuit 100, clock is advanced in the 1st delay circuit sequence 11 of synchronous delay circuit 100.
That is, clock (the 2nd clock of the input clock IN of Fig. 8) has been advanced the time in the 1st delay circuit sequence 11
The moment of tCK-(tCTS-tCK)=2tCK-tCTS, accept the input of next clock pulse (the 3rd clock of the input clock IN of Fig. 8), be sent to again used the 2nd delay circuit sequence 12 from the position of the minute 2tCK-tCTS of the 1st delay circuit sequence 11, after in the 2nd delay circuit sequence 12, transmitting this clock with recovery time 2tCK-tCTS, from 12 outputs of the 2nd delay circuit sequence, be imported into the node A (the 2nd clock of the A of Fig. 8) of clock trees 4 through transducer 10.And, the 3rd clock at Fig. 8 node A is: when the clock pulse of the 2nd clock of the input clock IN of Fig. 8 is imported in the 1st delay circuit sequence 11, turn back at minute, export from the 2nd delay circuit sequence 12 after transmitting the recovery time, and arrive the clock signal of the node A of clock trees 4.
After synchronously, at rising edge traveling time from input clock (IN)
In the moment (phase place) of tCK-(2tCK-tCTS)=tCTS-tCK, clock signal is offered the node A of clock trees 4.
As previously discussed, synchronous delay circuit be basically 1 group of forming by a pair of delay circuit sequence constitute.
And, the well-known formation that has 2 groups of synchronous delay circuits in addition, but in 2 groups of synchronous delay circuits, the cycle detection amount is used the retardation that equates.As known formation, formation shown in Figure 10 (with reference to opening flat 11-73238 communique as the spy) is for example arranged with 2 groups of synchronous delay circuits.Circuit shown in Figure 10 is to use clock pulse along measuring the clock cycle, prepares 2 groups of delay circuit sequences, carries out frequency division with 24 pairs of clocks of frequency divider 3, makes their alternations by per 1 cycle.
But, there is following problem in described synchronous delay circuit in the past: because of tCTS time of delay that sets clock trees 4 identical with clock cycle tCK, so, will on clock, produce discontinuity point when or in short-term because of the retardation of the fluctuating isochronon period ratio clock trees 4 of beating or length.
Be accompanied by the high speed of conductor integrated circuit device operating frequency, clock cycle, tCK shortened, on the other hand, be accompanied by the increase that clock uses circuit, tCTS time of delay of clock trees 4 increases, clock trees 4 time of delay tCTS and clock cycle tCK be that the situation of same degree can get more and more from now on.Therefore, just need positively avoid because of the generation of clock cycle than the retardation of clock trees 4 or the circuit erroneous action that loss of clock caused of length or generation in short-term etc.Below, this is elaborated.
Fig. 9 is the synchronous delay circuit in the past that is used for illustrating in reference Fig. 5 explanation, the propagation delay time tCTS of clock trees 4 and the clock cycle tCK of input clock 3 (IN) are almost equal, the figure of the time action when change such as tCTS＞tCK or tCTS≤tCK for example after synchronously, occurring such as rise and fall because of beating.
As shown in Figure 9, when tCTS＜tCK, rise edge delay recovery time tCK-tCTS from input clock (IN), the clock that rises is offered the node A of clock trees 4, when rising and falling because of beating etc., when the change of tCTS＞tCK occurring, the minute of the 1st delay circuit sequence 11 (with reference to Fig. 5), as previously discussed, become 2tCK-tCTS, accept the clock signal of input the 1st delay circuit sequence 11, be transferred to again used the 2nd delay circuit sequence 12 from this advanced positions, through after the recovery time 2tCK-tCTS,, offer the node A of clock trees 4 by change-over circuit 10 from 12 outputs of the 2nd delay circuit sequence.
At this moment, the node A in the clock trees 4 of accepting the clock supply from the output of synchronous delay circuit 100 produces loss of clock (discontinuity) phenomenon.
Like this, under the situation that produces loss of clock (discontinuity), in synchronous circuit, just cause the misoperation of circuit easily.
Therefore, the present invention is in view of the existence of described problem and constitute, its main purpose is: provide a kind of when the clock cycle is identical with the time of delay of clock transmission lines, even because of beating, under influences such as skew and deviation cause becoming the time of delay of clock trees than clock cycle or length or short situation, also can avoiding the synchronous delay circuit of discontinuous this problem of clock effectively.In addition purpose of the present invention, feature and advantage etc. directly give clear and definite by following embodiment record etc.
For reaching described purpose, the present invention have the 1st delay circuit sequence of utilizing being used to of making that input clock signal advances to postpone to measure measure transmit, poor between time of delay that the institute of output clock decides circuit or circuit and the input clock cycle, and utilize the reproduction of the 2nd delay circuit sequence and export many groups synchronous delay circuit of the time difference of described mensuration; Described many group synchronous delay circuits have 1 at least owing to insert delay, measure the retardation synchronous delay circuit different with other synchronous delay circuit, and has following function: promptly, even under the situation that described time of delay of deciding circuit or circuit and the magnitude relationship between the input clock cycle change, still can make from described synchronous delay circuit output, offer the described clock of deciding circuit or circuit and do not produce non-continuous event.
The present invention has and comprises the cycle that makes the 1st delay circuit sequence that is used for period measurement that input clock signal advances and clock signal with the corresponding length of length of advancing with clock signal is passed through reproduce many groups synchronous delay circuit with the 2nd delay circuit sequence in the 1st delay circuit sequence; Mensuration clock from the input node of fixed clock transmission lines be sent to the fixed needed propagation delay of output node time; Corresponding described synchronous delay circuit has and makes the corresponding described propagation delay time export the delay detection circuit that control respectively makes the control signal that the clock signal of described each synchronous delay circuit stops to advance; In described delay detection circuit, postpone by giving to insert in the input of at least 1 delay detection circuit, make the time of delay of utilizing described 1 delay detection circuit to detect inequality with the time of delay that the delay detection circuit that utilizes other detects; Make the cycle detection amount of synchronous delay circuit of corresponding described 1 delay detection circuit inequality with the cycle detection amount of the synchronous delay circuit of corresponding other each delay detection circuits; And has following function: promptly, even propagation delay time and clock cycle in described clock transmission lines are in a ratio of under the long or short situation, still can make the clock that offers described clock transmission lines from described synchronous delay circuit not produce non-continuous event.
Following brief description accompanying drawing.
Fig. 1 is the figure that expression one embodiment of the invention constitutes;
Fig. 2 is the time diagram that is used to illustrate one embodiment of the invention working condition;
Fig. 3 is the figure that the synchronous delay circuit of expression one embodiment of the invention constitutes;
Fig. 4 is the figure of expression one embodiment of the invention distortion;
Fig. 5 is the figure that represents that synchronous delay circuit in the past constitutes;
Fig. 6 represents that in the past synchronous delay circuit constitutes the figure of an example;
Fig. 7 is the time diagram that is used to illustrate synchronous delay circuit working condition in the past;
Fig. 8 is the time diagram that is used to illustrate synchronous delay circuit working condition in the past;
Fig. 9 is the time diagram that is used to illustrate synchronous delay circuit working condition in the past;
Figure 10 is the figure that represents other examples of synchronous delay circuit formation in the past;
Below symbol is described.
3-clock (input clock); The 4-clock trees; 5,7-delay detection circuit;
6,8-delay circuit (fixed delay circuit); The 10-transducer;
11-the 1st delay circuit sequence; 12-the 2nd delay circuit sequence;
13-the 3rd delay circuit sequence; 14-the 4th delay circuit sequence;
The 24-frequency divider; 100,101-synchronous delay circuit;
MP11～MP14-P channel MOS transistor;
MN11～MN14-N channel MOS transistor;
The VCC-power supply; The GND-earthing potential.
Embodiment
Below, the embodiment of the invention is described.Clock control circuit of the present invention, in its desirable embodiment, if with reference to Fig. 1, have: clock is from input node (A) input time of the clock transfer path (4) of regulation, till the moment of exporting from certain node (B) of clock transfer path (4), the cycle (delay) of output control signal (D) is measured the 1st delay detection circuit (5) of usefulness; The 1st delay circuit sequence (11) that clock signal is advanced; The clock signal that input is advanced in the 1st delay circuit sequence, and, only allow cycle (delays) reproduction that the described input clock signal of this length part passes through with the 2nd delay circuit sequence (12) corresponding to the length part of clock signal length of travel described in the 1st delay circuit sequence; Also have: according to control signal (D) from the 1st delay detection circuit (5) output, in the 1st delay circuit sequence (11), the 1st synchronous delay circuit (100) that stops to constitute for clock signal is advanced; Input node (A) input time at clock self-clock transfer path (4) rises, to the propagation delay time till node (B) output time of clock transfer path, during the time of delay of adding delay circuit (6), the 2nd delay detection circuit (7) of output control signal (D '); Make period measurement that clock signal advances with the 3rd delay circuit sequence (13); The clock signal that input has been advanced in the 3rd delay circuit sequence, corresponding to the length part of clock signal length of travel described in the 3rd delay circuit sequence, the cycle that only allows this length described input clock signal partly pass through reproduces with the 4th delay circuit sequence (14); Also have: the control signal (D ') according to from the 2nd delay detection circuit (7) output in the 3rd delay circuit sequence (13), is the 2nd synchronous delay circuit (101) that makes advancing of clock signal stop to constitute; Switch the output of the 2nd, the 4th delay circuit sequence (12,14) and the switch (10) of input clock (3); The output of switch (10) is connected with the input node (A) of clock transfer path (4).Between the 4th delay circuit sequence (14) output and switch (10), insert the regulation delay circuit (8) of time of delay.
In 1 embodiment of the present invention, the 1st, the 2nd delay detection circuit (5,7) to the input clock of clock transfer path (4) and from the clock of described clock transfer path output the time, also can constitute with the set-reset flip-floop of setting and setting again respectively.
In 1 embodiment of the present invention, so that the delay detection limit of the 2nd delay detection circuit (7) is different with the delay detection limit (the propagation delay time of=clock transfer path) of the 1st delay detection circuit (5), and make itself and synchronous delay circuit (100,101) the cycle detection amount in (measuring) difference with the mensuration retardation in the delay circuit, the propagation delay time (tCTS) of clock transfer path (4) compared with the clock cycle (tCK) of input clock, even under long or short situation, from synchronous delay circuit (100,101) clock that provides to clock transfer path (4) can not produce discontinuity point yet.
For above-mentioned the present invention is illustrated in more detail, below embodiments of the invention are described.Fig. 1 is the pie graph of 1 embodiment of the present invention.If with reference to Fig. 1, embodiments of the invention have: synchronous delay circuit 100, it comprises the 1st delay circuit sequence 11 that period measurement that clock signal pulse or pulse edge are advanced is used, with length part, the clock signal pulse of this length part or cycle that pulse edge passes through are reproduced with the 2nd delay circuit sequence 12 corresponding to clock signal pulse in the 1st delay circuit sequence 11 or pulse edge length of travel; Synchronous delay circuit 101, it comprises the 3rd delay circuit sequence 13 that period measurement that clock signal pulse or pulse edge are advanced is used, with the length part corresponding to clock signal pulse in the 3rd delay circuit sequence 13 or pulse edge length of travel, the cycle that clock signal pulse or pulse edge with this length part are passed through reproduces with the 4th delay circuit sequence 14; Make these two groups of synchronous delay circuits 100,101 corresponding, have the propagation delay time portion of transmission clock and clock trees 4 respectively and make pulse in the 1st, the 3rd delay circuit sequence 11,13 or the delay detection circuit 5,7 of advancing and stopping of pulse edge.
Between the output node B and delay detection circuit 7 of clock trees 4, insert the delay circuit 6 of fixed delay time (td), and the time of delay of detecting with delay detection circuit 7, be the time that in the propagation delay time of clock trees 4 (tCTS), adds the time of delay (td) of delay circuit 6, also make control signal (also being called [monitor signal]) (D ') between tCTS+td, become low level.
The long moment of the propagation delay time of clock trees 4 tCTS displacement ratio clock cycle tCK (changing constantly), from the output of synchronous delay circuit 100, even loss of clock (with reference to Fig. 9) takes place, export certain clock yet and offer the input node A of clock trees 4 from synchronous delay circuit 101, so that loss of clock (discontinuity point) does not take place in the clock that provides to the input node A of clock trees 4.
The output of the 4th delay circuit sequence 14 of synchronous delay circuit 101, by fixed delay time (=td) delay circuit 8, to commutation circuit 10 inputs, again by commutation circuit 10, offer the input node A of clock trees 4 with input clock 3, from one of the output clock of synchronous delay circuit 100,101 outputs.
In another embodiment of the present invention, delay detection circuit 5 and synchronous delay circuit 100 just can be realized with the same structure of circuit structure in the past with reference Fig. 5, Fig. 6 explanation.And delay detection circuit 7 and synchronous delay circuit 101 also have the identical structure of structure with delay detection circuit 5 and synchronous delay circuit 100.
Fig. 2 is, in another embodiment of the present invention since clock trees 4 time of delay tCTS and the clock cycle tCK of input clock about equally, beat etc., after synchronously, when tCTS＞tCK or tCTS＜tCK change, the figure of description time action.
As shown in Figure 2, when the state of tCTS＜tCK, from synchronous delay circuit 100, tCK-tCTS is postponed on rising edge edge from input clock (IN), and the output clock is from synchronous delay circuit 101,2tCK-(tCTS+td)+td is postponed on rising edge edge from input clock (IN), the output clock.
Owing to beat etc., when tCTS＞tCK, as mentioned above, minute in the 1st delay circuit 11 of synchronous delay circuit 100 is 2tCK-tCTS, accepts the signal of input in synchronous delay circuit 100, from this advanced positions, by control circuit 18, pass on the 2nd delay circuit sequence 12 to postponing to reproduce, when after recovery time 2tCK-tCTS, from 12 outputs of the 2nd delay circuit sequence.At this moment, loss of clock (discontinuity) does not take place in the output of synchronous delay circuit 100.
At this moment, also in synchronous delay circuit 101, by time of delay td delay circuit 7 (at this, time of delay, td was tCTS+td＞tCK), as what illustrate with reference to Fig. 7, recovery time 2tCK-(tCTS+td) is postponed on rising edge edge from input clock 3, from delay circuit sequence 13 output clocks, loss of clock does not take place.
The clock F that exports from the 4th delay circuit sequence 14 of synchronous delay circuit 101 is postponed at delay circuit 8 (td time of delay), rising edge edge from input clock IN, in recovery time 2tCK-(tCTS+td), add the part of td time of delay, be 2tCK-tCTS retardation time, offer the input node A of clock trees 4 from the clock of synchronous delay circuit 101 outputs.
Delay circuit 8, in synchronous delay circuit 101 1 sides, shorten the cycle detection amount, and it is different with the cycle detection amount of synchronous delay circuit 100 in order to make, (td) part time of delay of the delay circuit 6 that in the input of delay detection circuit 7, inserts, with respect to the recovery time 2tCK-(tCTS+td) that increases, at the moment 2tCK-tCTS that has offseted time of delay (td), the clock that rises is offered the input node A of clock trees 4 by commutation circuit 10.And, in application circuit, also can omit delay circuit 8 if there is no need.
With with above-mentioned same principle, when tCTS＞tCK, if owing to beat etc. and in the last variation of tCTS＜tCK, tCTS＞tCK, discontinuity point can take place in the output clock of synchronous delay circuit 100, but at this moment, the delay detection time of delay detection circuit 8, export synchronised clocks from the synchronous delay circuit 101 of tCTS+td to input clock 3, and it is offered the input node A of clock trees 4 by commutation circuit 10.
And, even tCTS+td＜tCK also can.At this moment, owing to beat etc., in tCTS+td＞tCK, change constantly, discontinuity point takes place in the output clock of synchronous delay circuit 101, but at this moment, export synchronised clocks from synchronous delay circuit 100 to input clock 3, and it is offered the input node A of clock trees 4 by commutation circuit 10.
Like this, in another embodiment of the present invention, when tCTS and tCK equal extent, from tCTS＞tCK to moment that tCTS＜tCK changes, even discontinuous situation takes place in the clock of exporting from a side synchronous delay circuit, owing to export clock, so the clock that provides from synchronous delay circuit can not broken off from the opposing party of different cycle detection amounts.
What Fig. 3 showed is in another embodiment of the present invention, to constitute the figure of the 1st delay circuit sequence 11 (the 3rd delay circuit sequence 13), control circuit 18 and the 2nd delay circuit sequence 12 (the 4th delay circuit sequence 14) 1 example.Unit delay part as the delay circuit sequence, be to constitute by clock control formula phase inverter, during clock pulse is passed through clock trees 4, delay detection circuit 5,7 with the clock of the input node A that accept to arrive clock trees 4, the control signal D that takes place is a low level, make MOS transistor MN11, MN12, MP11, the MP12 of delay circuit sequence 11 (13) be in the pass, i.e. the state of OFF is not so that clock pulse is advanced in delay circuit sequence 11 (13).
Promptly, when clock pulse during to the node A of clock trees 4 input, the delay detection circuit of being made up of set-reset flip-floop 5 (7) is set again, make signal D (D ') be in low level, in the moment of clock pulse along the arrival Node B, set delay detection circuit 5 set-reset flip-floop (delay detection circuit 7 be in further postponed time td after, set set-reset flip-floop), make signal D (D ') be in high level, MOS transistor MN11, MN12, MP11, the MP12 of delay circuit sequence 11 (13) are in out, i.e. the state of ON.
Like this, clock pulse or pulse edge make signal D be in low level by during the clock trees 4, and the clock control formula phase inverter of delay circuit sequence 11 becomes the pass, and promptly the OFF state stops clock and advances.And clock pulse or pulse edge be by (tCTS) during the clock trees 4 and in the time of delay of delay circuit 6 (td), signal D ' is in low level, and the clock of delay circuit sequence 13 becomes the pass, and promptly the OFF state stops clock and advances.
Constituting for the clock control formula phase inverter of delay circuit sequence 12 (14), is to equate time of delay for delay circuit sequence 11 (13) and be provided with, and is in out the ON state usually.Soon MOS transistor MN13, MN14, MP13, MP14 are set in out, i.e. the state of ON.
Below with reference to Fig. 3, n unit delay part described, output FIn with n-1 clock control formula phase inverter of delay circuit sequence 11, input NAND door (NAND11), simultaneously with not connecting in 2 input terminals of the NAND of control circuit 18 door with the terminal that control terminal C (control terminal C is connected with the input IN of input clock) connects, and the output MNn of the NAND door of control circuit 18, with 1 in 2 input terminals of n+1 the NAND door (not shown) of delay circuit sequence 11, be connected with the input terminal that does not have to be connected with the output FIn+1 output of n inverter INV12, simultaneously with 1 in 2 input terminals of the NAND door (NAND14) of delay circuit sequence 12, be connected with the input terminal that does not have to be connected with the output of the output BIn+1 of the inverter of leading portion.The output of the NAND door (NAND14) of delay circuit sequence 12 is connected with the input of the inverter INV13 of delay circuit sequence 12.BIn+1 to the output of the leading portion inverter of the NAND of delay circuit sequence 12 door (NAND14), import to NAND door (NAND14), be used as load simultaneously and adjust in 2 input terminals of NAND door (NAND15) of element 1, be not connected with earth connection the input terminal connection.And the output that the NAND15 of element is adjusted in load is not connected with any terminal.3rd, the formation of the 4th delay circuit sequence 13,14 too.
Like this, in the present invention, make the cycle detection amount in the synchronous delay circuit 100,101 different mutually, by the generation that prevents loss of clock from tCTS＜tCK to the variation of tCTS＞tCK.Delay circuit 6 for example as shown in Figure 4, also can insert between the node A of clock trees 4 and the input of delay detection circuit 7 (setting terminal R again).
In formation shown in Figure 4, when being in the state of tCTS＜tCK, synchronous delay circuit 100 is same with described embodiment, rising edge from input clock 3 (IN), postpone stipulated time tCK-tCTS, the output clock, and delay detection circuit 7, from postponing td time of delay to moment of the node A of clock trees 4 input clock, make control signal (monitor) D ' be in low level, during the tCTS-td, i.e. till the moment of the Node B of clock arrival clock trees 4, make control signal (monitor) D ' be in low level, the clock that stops the 3rd delay circuit sequence 13 is advanced.Therefore, the mensuration retardation of the 3rd delay circuit sequence 13 is tCK-(tCTS-td), postpone tCK-(tCTS-td)=tCK-tCTS+td from the rising edge of input clock 3, the reproduction retardation of the 4th delay circuit sequence 14 is Tck-(Tcts-td), provides clock to the input node A of clock trees 4.
State from tCTS＜tCK, by by the state variation of beating etc. to tCTS＞tCK, even can not lose from the clock of synchronous delay circuit 100 outputs, when tCTS-td＜tCK, postpone tCK-tCTS+td from the rising edge of the clock 3 of synchronous delay circuit 101 input, output clock F is not so the clock that provides to the input node A of clock trees 4 can be lost (discontinuity).
In the foregoing embodiments, though be illustrated with the example that constitutes with 2 groups of synchronous delay circuits, in the present invention, synchronous delay circuit is not limited to 2 groups certainly.For example possess 3 groups of above synchronous delay circuits, and correspond respectively to synchronous delay circuit and possess delay detection circuit, and postpone to insert in delay detection circuit, make the cycle detection amount difference in the synchronous delay circuit, such formation also is fine certainly.
In addition in the present invention, synchronous delay circuit, be not limited to by constituting, also can be applicable to certainly by constituting the situation of (opening flat 11-73238 communique) with reference to the spy with the unidirectional 1 pair of delay circuit sequence of the direct of travel of clock with the rightabout 1 pair of delay circuit sequence of the direct of travel of clock.
As the above-mentioned explanation of doing, according to the present invention, synchronous delay circuit with most groups, owing to can make the cycle detection amount difference in each synchronous delay circuit, so according to beating, oblique deviation etc., carry out the propagation delay time of the clock transfer path of detection time of delay, with clock cycle its size of variable ratioization mutually, even lose from the clock that a side synchronous delay circuit is exported, also since with clock synchronization from the input of the opposing party's synchronous delay circuit, when exporting clock again, just can make from synchronous delay circuit and discontinuity point not take place to the clock that the clock transfer path provides.According to the present invention, amass in the circuit arrangement at the semiconductor that makes the continuous high speed of operating frequency and circuit scale is constantly increased, can guarantee reliable clock control action, its practical value is high.
Claims (12)
1. synchronous delay circuit, have the 1st delay circuit sequence of utilizing being used to of making that input clock signal advances to postpone to measure measure transmit, poor between time of delay that the institute of output clock decides circuit or circuit and the input clock cycle, and utilize the reproduction of the 2nd delay circuit sequence and export many groups synchronous delay circuit of the time difference of described mensuration; It is characterized in that:
Described many group synchronous delay circuits have 1 group at least because additional delay, make and measure the retardation synchronous delay circuit different with other synchronous delay circuit, and has following function: promptly, even under the situation that described time of delay of deciding circuit or circuit and the magnitude relationship between the described input clock cycle change, still can make from described synchronous delay circuit output, offer the described clock of deciding circuit or circuit and do not produce non-continuous event.
2. synchronous delay circuit, have and comprise the cycle that makes the 1st delay circuit sequence that is used for period measurement that input clock signal advances and clock signal with the corresponding length of length of advancing with clock signal is passed through reproduce many groups synchronous delay circuit in described the 1st delay circuit sequence with the 2nd delay circuit sequence; It is characterized in that:
Has corresponding described synchronous delay circuit, detection clock from the input node of fixed clock transmission lines be sent to the fixed needed propagation delay of output node time, and the corresponding described propagation delay time export the delay detection circuit that control respectively makes the control signal that the clock signal of described each synchronous delay circuit stops to advance;
In described a plurality of delay detection circuits, postpone by giving to insert in the input of at least 1 delay detection circuit, make the time of delay of utilizing described 1 delay detection circuit to detect inequality with the time of delay that the delay detection circuit that utilizes other detects; Make the cycle detection amount of synchronous delay circuit of corresponding described 1 delay detection circuit inequality with the cycle detection amount of the synchronous delay circuit of corresponding other each delay detection circuits; Even propagation delay time and clock cycle in described clock transmission lines are in a ratio of under the long or short situation, still can make the clock that offers described clock transmission lines from described synchronous delay circuit not produce non-continuous event.
3. synchronous delay circuit, have to comprise and make the 1st delay circuit sequence that is used for period measurement that input clock signal pulse or pulse edge advance and make clock signal pulse or the cycle that pulse edge passes through reproduces 2 groups of synchronous delay circuits with the 2nd delay circuit sequence with the corresponding length of length of in described the 1st delay circuit sequence, advancing with clock signal pulse or pulse edge; It is characterized in that:
Have 2 described each synchronous delay circuits of correspondence, detection clock from the input node of fixed clock transmission lines be sent to propagation delay time of fixed output node, and the corresponding described propagation delay time exports respectively, and control makes the clock signal pulse of described each synchronous delay circuit or the delay detection circuit of the control signal that pulse edge stops to advance;
In described 2 delay detection circuits, postpone by giving to insert in the input of 1 delay detection circuit, make the time of delay of utilizing described i delay detection circuit to detect inequality with the time of delay of utilizing another delay detection circuit to detect; Make mensuration cycle of synchronous delay circuit of corresponding described 1 delay detection circuit inequality with the mensuration cycle of the synchronous delay circuit of corresponding another each delay detection circuit; Even propagation delay time and clock cycle in described clock transmission lines are in a ratio of under the long or short situation, still can make the clock that offers described clock transmission lines from described synchronous delay circuit not produce non-continuous event.
4. according to claim 2 or 3 described synchronous delay circuits, it is characterized in that: the delay circuit element that constitutes described the 1st delay circuit sequence constitutes by control its open/close clock control formula phase inverter with described control signal.
5. according to claim 2 or 3 described synchronous delay circuits, it is characterized in that: have the described respectively output of the 2nd delay circuit sequence of described each synchronous delay circuit of conversion and the transducer of input clock, the output of described transducer connects the input node of described clock transmission lines.
6. according to claim 2 or 3 described synchronous delay circuits, it is characterized in that: described delay detection circuit is reset by receiving behind the clock of the input node of described clock transmission lines input, constitutes and receive the trigger that is set behind the clock of described clock transmission lines output node output.
7. a conductor integrated circuit device uses synchronous delay circuit to control the clock signal that offers the clock transmission lines;
Have and comprise the cycle that makes the 1st delay circuit sequence that is used for period measurement that input clock signal advances and clock signal with the corresponding length of length of advancing with clock signal is passed through reproduce many groups synchronous delay circuit in the 1st delay circuit sequence with the 2nd delay circuit sequence; It is characterized in that:
Has corresponding each described synchronous delay circuit respectively, mensuration clock from the input node of fixed clock transmission lines be sent to the fixed needed propagation delay of output node time, and the corresponding described propagation delay time export a plurality of delay detection circuits that control respectively makes the control signal that the clock signal of described each synchronous delay circuit stops to advance;
In described delay detection circuit, postpone (td) by giving to insert in the input of at least 1 delay detection circuit, make the time of delay of utilizing described 1 delay detection circuit to detect inequality with the time of delay that the delay detection circuit that utilizes other detects; Make the cycle detection amount of synchronous delay circuit of corresponding described 1 delay detection circuit inequality with the cycle detection amount of the synchronous delay circuit of corresponding other each delay detection circuits; Even the magnitude relationship between the clock cycle of propagation delay time of described clock transmission lines (tCTS) and input clock (tCK) changes, produce discontinuity point on the clock of certain the described synchronous delay circuit in described a plurality of synchronous delay circuits, also can offer described clock transmission lines from other the clock that described synchronous delay circuit is exported and input clock is synchronous.
8. a conductor integrated circuit device uses synchronous delay circuit to control the clock signal that offers the clock transmission lines; It is characterized in that:
Comprise: comprising the cycle that makes the 1st delay circuit sequence that is used for period measurement that input clock signal advances and clock signal with the corresponding length of length of advancing in the 1st delay circuit sequence with clock signal is passed through reproduces the 1st synchronous delay circuit with the 2nd delay circuit sequence;
Mensuration clock from the input node of fixed clock transmission lines be sent to the fixed needed propagation delay of output node time (tCTS), and the corresponding described propagation delay time export the 1st delay detection circuit that control respectively makes the 1st control signal that the clock signal of described each synchronous delay circuit stops to advance;
Comprising the cycle that makes the 3rd delay circuit sequence that is used for period measurement that input clock signal advances and clock signal with the corresponding length of length of advancing in the 3rd delay circuit sequence with clock signal is passed through reproduces the 2nd synchronous delay circuit with the 4th delay circuit sequence;
Detect described clock from the input node of fixed clock transmission lines be sent to the fixed needed propagation delay of output node time (tCTS), fixed time of delay (td) add during the described propagation delay time goes up, output control makes the 2nd delay detection circuit of the 2nd control signal that the described clock signal of described the 2nd synchronous delay circuit stops to advance;
By change-over circuit the described the 2nd and the output of the 4th delay circuit sequence be input in the described input node of described clock transmission lines.
9. conductor integrated circuit device according to claim 8 is characterized in that: between the input of the output node of described clock transmission lines and described the 2nd delay detection circuit, insert the 1st delay circuit of fixed delay time; Between the input of the output of described the 4th delay circuit sequence and described transducer, insert the 2nd delay circuit of described fixed delay time.
10. according to claim 7 or 8 described conductor integrated circuit devices, it is characterized in that: the delay circuit element that constitutes described the 1st delay circuit sequence constitutes by control its open/close clock control formula phase inverter with described control signal.
11. conductor integrated circuit device according to claim 8 is characterized in that: described the 1st, the 2nd delay detection circuit is by according to the output clock of the input clock of described clock transmission lines and described clock transmission lines and be reset respectively and the trigger that is set constitutes.
12. conductor integrated circuit device according to claim 10 is characterized in that: between one group of input of the output node of described clock transmission lines and described the 2nd delay detection circuit, insert the 1st delay circuit of fixed delay time; Between the input of the output of described the 4th delay circuit sequence and described transducer, insert the 2nd delay circuit of described fixed delay time.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000060101A JP3386031B2 (en) | 2000-03-06 | 2000-03-06 | Synchronous delay circuit and semiconductor integrated circuit device |
| JP060101/2000 | 2000-03-06 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1315782A true CN1315782A (en) | 2001-10-03 |
| CN1161881C CN1161881C (en) | 2004-08-11 |
Family
ID=18580463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011109769A Expired - Fee Related CN1161881C (en) | 2000-03-06 | 2001-03-06 | Synchronous delay circuit and semiconductor integrated circuit device |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6509775B2 (en) |
| EP (1) | EP1139565A1 (en) |
| JP (1) | JP3386031B2 (en) |
| KR (1) | KR100395467B1 (en) |
| CN (1) | CN1161881C (en) |
| TW (1) | TW502146B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347057A (en) * | 2011-08-09 | 2012-02-08 | 北京时代全芯科技有限公司 | Clock tree structure used for data path and memory with it |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4609808B2 (en) * | 2001-09-19 | 2011-01-12 | エルピーダメモリ株式会社 | Semiconductor integrated circuit device and delay lock loop device |
| JP3685786B2 (en) * | 2003-02-18 | 2005-08-24 | 誠 小川 | Semiconductor circuit |
| KR100546320B1 (en) * | 2003-02-27 | 2006-01-26 | 삼성전자주식회사 | Clock tree synthesis apparatus and method |
| KR100558554B1 (en) * | 2004-01-07 | 2006-03-10 | 삼성전자주식회사 | Internal clock generating apparatus |
| US7276946B2 (en) * | 2004-07-16 | 2007-10-02 | Micron Technology, Inc. | Measure-controlled delay circuits with reduced phase error |
| US7216322B2 (en) * | 2004-09-07 | 2007-05-08 | Chang Gung University | Clock tree synthesis for low power consumption and low clock skew |
| US7091764B2 (en) * | 2004-11-05 | 2006-08-15 | Infineon Technologies Ag | Duty distortion detector |
| KR100913330B1 (en) * | 2007-12-27 | 2009-08-20 | 주식회사 동부하이텍 | Apparatus for testing memory device |
| US7719334B2 (en) * | 2008-05-28 | 2010-05-18 | Micron Technology, Inc. | Apparatus and method for multi-phase clock generation |
| US7642827B2 (en) * | 2008-05-28 | 2010-01-05 | Micron Technology, Inc. | Apparatus and method for multi-phase clock generation |
| US9520865B2 (en) * | 2014-09-04 | 2016-12-13 | Qualcomm Incorporated | Delay circuits and related systems and methods |
| CN106960087B (en) * | 2017-03-13 | 2020-05-19 | 上海华力微电子有限公司 | Clock distribution network structure and generation method thereof |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3338744B2 (en) | 1994-12-20 | 2002-10-28 | 日本電気株式会社 | Delay circuit device |
| JPH1013395A (en) * | 1996-06-25 | 1998-01-16 | Toshiba Corp | Phase synchronization circuit |
| DE69733108T2 (en) * | 1996-09-13 | 2006-03-02 | Nec Electronics Corp., Kawasaki | Synchronous multiplexing delay circuit |
| JPH10150350A (en) * | 1996-11-18 | 1998-06-02 | Toshiba Corp | Phase synchronization circuit and storage device using the phase synchronization circuit |
| JP3072726B2 (en) | 1997-05-30 | 2000-08-07 | 日本電気株式会社 | Synchronous delay circuit |
| US6075395A (en) * | 1997-05-30 | 2000-06-13 | Nec Corporation | Synchronous delay circuit |
| JP3039466B2 (en) * | 1997-08-12 | 2000-05-08 | 日本電気株式会社 | Clock recovery circuit |
| JP3019814B2 (en) * | 1997-09-18 | 2000-03-13 | 日本電気株式会社 | Clock recovery circuit |
| JP3434682B2 (en) * | 1997-10-03 | 2003-08-11 | Ｎｅｃエレクトロニクス株式会社 | Synchronous delay circuit |
| JPH11112308A (en) * | 1997-10-06 | 1999-04-23 | Nec Corp | Synchronous delay circuit device |
| JP3052925B2 (en) * | 1998-02-27 | 2000-06-19 | 日本電気株式会社 | Clock control method and circuit |
| JP3579277B2 (en) * | 1998-12-28 | 2004-10-20 | 株式会社東芝 | Clock synchronization delay control circuit |
| KR100326809B1 (en) * | 1999-04-09 | 2002-03-04 | 박종섭 | Delay locked loop circuit |
-
2000
- 2000-03-06 JP JP2000060101A patent/JP3386031B2/en not_active Expired - Fee Related
-
2001
- 2001-02-15 TW TW090103392A patent/TW502146B/en not_active IP Right Cessation
- 2001-03-02 KR KR10-2001-0010801A patent/KR100395467B1/en not_active IP Right Cessation
- 2001-03-05 US US09/799,543 patent/US6509775B2/en not_active Expired - Fee Related
- 2001-03-06 CN CNB011109769A patent/CN1161881C/en not_active Expired - Fee Related
- 2001-03-06 EP EP01105577A patent/EP1139565A1/en not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347057A (en) * | 2011-08-09 | 2012-02-08 | 北京时代全芯科技有限公司 | Clock tree structure used for data path and memory with it |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010087275A (en) | 2001-09-15 |
| CN1161881C (en) | 2004-08-11 |
| US20010020859A1 (en) | 2001-09-13 |
| JP3386031B2 (en) | 2003-03-10 |
| KR100395467B1 (en) | 2003-08-25 |
| EP1139565A1 (en) | 2001-10-04 |
| TW502146B (en) | 2002-09-11 |
| US6509775B2 (en) | 2003-01-21 |
| JP2001249732A (en) | 2001-09-14 |
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