JP2725644B2 - Clock distribution system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution system in a synchronous digital data processing system.

[0002]

2. Description of the Related Art Special problems caused by variations in propagation time in synchronous data processing systems arise with the design of clock distribution systems. For example,
Variations in propagation time can cause significant skew on clocks applied to different parts of the system. To prevent this skew from causing timing issues,
Conventional solutions provide maximum skew with minimum system cycle time to ensure that all data signals arrive before the clock arrives at their destination, for example, a storage means such as a flip-flop. .
For example, in high performance systems such as computers and other systems designed with digital circuits, this increase in cycle time can have a very detrimental effect on system speed.

The first cause of skew in a data processing system is caused by a difference in propagation time between integrated circuit chips (hereinafter abbreviated as IC) due to a variation in a manufacturing process. In the case of clock distribution circuits, differences in propagation times between ICs are particularly problematic because they will create skew in clocks distributed throughout the system.

[0004] One solution to this skew problem is to improve the IC fabrication process to provide a more uniform I skew.
C is manufactured, and as a result, variation between ICs is reduced. However, this solution is economically impractical due to the increased cost required.

A second cause of skew in a data processing system is caused by a difference in propagation time caused by non-uniformity of a clock distribution path connecting ICs. Clock distribution circuits in large scale synchronous digital data processing systems using a large number of ICs are particularly problematic as the number of clock distribution paths for the entire system will be large.

One solution to the skew problem is to use a clock distribution circuit having a tree-like configuration based on a 1: 1 connection of clock distribution paths to each IC. In some cases, a more uniform clock distribution path is designed. However,
This solution is economically impractical because its hardware volume becomes very large and the required costs increase.
Further, an increase in the amount of hardware also causes an increase in skew due to characteristic variations, and is not very effective. Here, the clock distribution path is 1: n (plural)
The connection reduces the amount of hardware. However, the signal propagation delay time difference depending on the connection order and the load IC
The skew increases due to the influence of noise due to multiple reflection of a signal wave propagated between terminals.

[0007] Another solution used to minimize these skews is, for example, May 8, 1944.
SA Tag issued on the day
ue) U.S. Pat. No. 4,447,8 by other inventors
No. 70, "Apparatus for setting basic clock timing in a data processing system". In this patent publication, manual (or operator controlled) adjustment of the clock distribution system is provided. But,
This solution is uneconomic due to the increased labor and / or equipment required, in addition to the disadvantage that manual or operator controlled adjustments must be provided. Furthermore, such initial skew adjustment cannot compensate for skew due to factors that occur later, such as temperature fluctuations.

[0008]

When the above-mentioned conventional clock distribution system is employed in a large-scale synchronous digital data processing system, the skew of the clock signal becomes extremely large, and the performance of the system deteriorates. It was not suitable for practical use. In addition, the conventional clock distribution system for the purpose of skew reduction is economically disadvantageous but ineffective when employed in a large-scale synchronous digital data processing system.

It is an object of the present invention to provide a clock distribution system that reduces clock skew.

Another object of the present invention is to provide a clock distribution system capable of reducing the amount of hardware.

Another object of the present invention is to provide a clock distribution system for improving the performance of a large-scale synchronous digital data processing system.

[0012]

According to the first clock distribution system of the present invention, the initial amplitude waveform of the distributed clock signal reaches the circuit input terminal and then reaches the farthest end opposite to the transmission end of the transmission line. A detection circuit for detecting a time difference before the light is reflected and returned to the circuit input terminal; and an internal circuit which is delayed by half the time difference detected by the detection circuit after the initial amplitude waveform of the delay distribution clock signal reaches the circuit input terminal. An internal clock signal generating circuit for generating a clock signal.

A second clock distribution system according to the present invention comprises:
A first clock distribution circuit that distributes a basic clock signal to each of a plurality of circuit groups as a distribution clock signal via a first clock driving circuit and a first transmission line serially terminated at a sending end; A delayed clock signal obtained by delaying the basic clock signal by a predetermined time is delayed to each of the plurality of circuit groups via a second clock driving circuit and a second transmission line serially terminated at a transmitting end. A second clock distribution circuit configured to distribute as a distributed clock signal, wherein each of the plurality of circuit groups has an initial amplitude waveform of the distributed clock signal at an input terminal of each circuit of the circuit group. From the time of arrival to the time when the initial amplitude waveform of the distributed clock signal is reflected by the farthest end opposite to the sending end of the first transmission line and returns to the input end of each circuit of the circuit group. And an internal clock generating means for generating an internal clock signal delayed by half the time difference from the time when the initial amplitude waveform of the delay distribution clock signal reaches the input terminal of the circuit group. Is done.

A third clock distribution system according to the present invention comprises:
In the first clock distribution system, each of the plurality of circuit groups generates a time difference detection circuit for detecting the time difference and the internal clock signal delayed by half the time difference detected by the time difference detection circuit. And an internal clock signal generation circuit.

A fourth clock distribution system according to the present invention comprises:
In the first clock distribution system, each internal clock signal in each circuit is constant with respect to the basic clock signal without using the second clock distribution circuit by using the distribution clock signal itself instead of the delay distribution clock signal. Is synchronized with a delay of the phase difference of

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. First, a first clock distribution system according to the present invention will be described with reference to FIG. 1, FIG. 2 and FIG. Referring to FIG. 1, a first clock distribution circuit 1 according to a first embodiment of the present invention includes a first clock driving circuit 11, a first terminating resistor 13, and a transmitting end terminating at the first terminating resistor 13. And a first transmission line 12 for transmitting a basic clock signal K ₀ to a plurality of (n ≧ 2) IC3s.
Each of sequentially distributed as distribution clock signal K _M. In this embodiment, description will be made below with n = 5. The delay means 4 delays the basic clock signal K ₀ by a time t _{d and} outputs the delayed clock signal K _D. For example, a circuit such as a delay circuit in which delay lines and flip-flops are vertically connected is desirable. The second clock distribution circuit 2
Is composed of a clock driver circuit 21 and the second transmission line 22 which is sending-end terminated with a second termination resistor 23, the delayed clock signal K _D to each of the n (= 5) pieces of IC3,
Wherein in the same order as the distribution of the distributed clock signal K _M, distributed as delayed distribution clock signal K _DM. Here, the first
Clock distribution circuit 1 and the second clock distribution circuit 2
Are ideally exactly the same and practically almost the same, and are characterized in that they are clock distribution circuits terminated at the transmission ends.

[0017] Here, the time from the first clock distribution circuit 1 is the basic clock signal K ₀ is input, until it as the initial amplitude waveform of the distribution clock signal K _M, reaches the input end of a certain one of IC3 a and t _p. Furthermore, the initial amplitude waveform of the distribution clock signal K _M from reaching the input end of the IC3, of the IC3 is reflected by the transmission terminal of the first transmission line 12 reaches the farthest end that is opposite The round trip time before returning to the input end is _dt . As mentioned above,
The clock distribution circuit 2 is ideally and exactly the same as the first clock distribution circuit 1 and practically regarded as substantially the same. _D since the input, the initial amplitude waveform of the delayed distribution clock signal K _D of delayed distribution clock signal K _DM, the time to reach the input end of the IC3 t _p
Is almost equal to Furthermore, the initial amplitude waveform of the delay distribution clock signal K _DM from reaching the input end of the IC3, and the sending end of the second transmission line 22 is reflected by reaching the farthest end is opposite IC3 Is also substantially equal to _dt .

In addition, the speed at which the signal waveform propagates on the first transmission line 12 and the second transmission line 22 is ideally constant in any portion. It can be considered practically almost constant. Therefore, the time (t _p + d _t / 2) in each IC 3 is all from the time when the signal is input to the first clock distribution circuit 1 until the time when the signal reaches the farthest end of the first transmission line 12. The time is almost equal to the time from when the signal is input to the second clock distribution circuit 2 to when the signal reaches the farthest end of the second transmission line 22, and is substantially constant regardless of the position of each IC 3. Becomes

[0019] Each IC3 shown in FIG. 1, from the time the initial amplitude waveform of the distribution clock signal K _M to be dispensed by the first clock distribution circuit 1 reaches the input end of the IC3, the distribution clock signal the initial amplitude waveform of the K _M first
The time difference d _t from when the light reaches the farthest end, which is opposite to the sending end of the transmission line 12, is reflected and returns to the input end of the IC 3.
And the initial amplitude waveform of the delay distribution clock signal _KDM distributed by the second clock distribution circuit 2 is
Incorporating an internal clock generating means for generating an internal clock signal K _I only delayed half the difference d _t the time it reaches the input terminal as a base point (d _t / 2) of C3. That is, the internal clock signal K _I is generated with a delay of substantially the phase difference (t _d + t _p + d _t / 2) with respect to the basic clock signal K ₀ .

Here, the time (t) in each of the ICs 3 is described.
_p + d _t / 2) are substantially constant irrespective of the position of each IC 3, so that each of the internal clock signals K _I generated in each of the ICs 3 becomes the basic clock signal K _0.
With a delay of a substantially constant phase difference (t _d + t _p + d _t / 2).

Next, each IC 3 in the first embodiment of the present invention will be described.
An example of the internal clock generating means incorporated in the device will be described below in detail with reference to the drawings.

Referring to FIG. 2, the edge detection circuit 311
Is detectable compared to the first clock first row a rising edge of the distribution circuit distributing the clock signal K _M to be dispensed by 1 (Low) level reference signal V _RL shown in FIG. The edge detection circuit 312 outputs the distribution clock signal K _M
First rising edge of the first clock distribution circuit 1
Is detected by comparing with the high level reference signal V _RH when the signal reaches the farthest end, which is opposite to the sending end of the first transmission line 12, and rises again when reflected and returned. . Time difference detection circuit 32 detects the time difference d _t receives the respective output signals of the edge detection circuits 311 and 312, and outputs the time difference signal S _D to instruct half of said time difference (d _t / 2). The edge detection circuit 313 sets the first rising edge of the delay distribution clock signal _KDM distributed by the second clock distribution circuit 2 to low (Lo).
w) Detection is performed by comparing with the level reference signal _VRL . The variable delay means 331 delays the output signal of the edge detection circuit 313 by half the time difference (d _t / 2) according to the time difference signal _{SD and} outputs it as a set signal. The edge detection circuit 314
The first falling edge of the delay distribution clock signal _KDM distributed by the second clock distribution circuit 2 is set to high (Hi).
gh) Detected by comparing with the level reference signal V _RH . The variable delay means 332 delays the output signal of the edge detection circuit 314 by half the time difference ( _dt / 2) according to the time difference signal _{SD and} outputs the signal as a reset signal. Variable delay means 33
It is desirable that 1 and 332 be constituted by a variable delay line or a variable delay circuit. The flip-flop circuit 34
Each of the set signal and the reset signal is input to perform a set operation and a reset operation, thereby generating an internal clock signal K _I. With the above operation, the internal clock signal K _I, the time difference d _t half the time the initial amplitude waveform of the delayed distribution clock signal K _DM reaches the input end of the IC3 as a base point (d _t / 2) delayed Generated.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 3, K ₀ denotes the voltage waveform of the basic clock signal, the one with the K _M and K _DM IC
At third input terminal shows the voltage waveform of the distribution clock signal and the delayed distribution clock signal, K _I denotes the voltage waveform of the internal clock signal generated in the said IC3.

Referring to FIGS. 1 and 3, the distributed clock signal K _M are distributed via the first clock distribution circuit 1 based on the basic clock signal K _0. Here, since the clock distribution circuit 1 is terminated at the sending end, a certain 1
At the input terminals of the three ICs 3, the basic clock signal K ₀
Distribution clock signal K _M arriving from changing after a time t _p
, The initial amplitude is about 1 / max of the maximum amplitude
It becomes 2. Distribution clock signal K _M by reflected wave arrives from the farthest end to the transmitting end of the first transmission line 12 is opposite yet after a time d _t varies from the maximum amplitude. The first
The reflected wave reaching the sending end of the transmission line 12 does not reflect again due to the effect of the termination.

The delay distribution clock signal K _DM basic clock signal a second clock distribution is substantially the same structure only the clock distribution circuit 1 of the first delayed time t _d through the delay means 4 K0 based on It is distributed in the same manner as in the distribution clock signal K _M via the circuit 2. Therefore, as described above, at the input terminal of one IC3, the initial amplitude of the delayed distributed clock signal _KDM , which arrives after a time (t _d + t _p ) from the change of the basic clock signal K ₀ , that is, the initial amplitude, is When the reflected wave from the farthest end, which is opposite to the sending end of the second transmission line 22, arrives after about _{dt of the} maximum amplitude and after a time _dt , the delay distribution clock signal K
_DM varies up to the maximum amplitude. The reflected wave reaching the sending end of the second transmission line 22 does not reflect again due to the effect of the termination.

Next, the operation of one example of the internal clock generating means shown in FIG. 2 will be described in detail with reference to the drawings.

Referring to FIGS. 2 and 3, in each IC3, first, the distribution clock signal K _M which rises only the initial amplitude of the half of the maximum amplitude with a delay of time t _p from the rise time of the basic clock signal K ₀ Edge is low (L
ow) is detected by comparing the level reference signal V _RL and the edge detection circuit 311. This edge is after the time from the detection d _t of the detection circuit 311 detects by comparing the edge of the distribution clock signal K _M which rises up to the maximum amplitude again at a high (High) level reference signal V _RH and the edge detection circuit 312. The time difference _dt can be detected by the operation of detecting these two edges. Next, the basic clock signal K time from the rise time of ₀ (t _d + t _p) delayed low the edge of the delay distribution clock signal K _DM which rises only initial amplitude which is half of the maximum amplitude (Low) level reference signal V _RL
And an edge detection circuit 313 to detect them. Half of the time difference d _t already detected from the time (d _t / 2) to generate a rising edge of the internal clock signal K _I which is delayed only. On the other hand, the edge of the delayed distributed clock signal _KDM , which falls by the maximum amplitude 初期 the initial amplitude with a delay of time (t _d + t _p ) from the fall time of the basic clock signal K ₀ , is set to the high (High) level reference signal V _RH. And the edge detection circuit 314 detects the falling edge, and generates a falling edge of the internal clock signal K _{I which} is delayed from that time by half ( _dt / 2) of the detected time difference _dt .

By operating as described above,
Each of the internal clock signals K _I generated in each IC 3 is a signal delayed by a fixed phase difference (t _d + t _p + d _t / 2) with respect to the basic clock signal K ₀ .

Referring to FIGS. 1 and 3, in a first clock distribution circuit 1 according to a first embodiment of the present invention,
By designing the delay time t _d by the delay means 4 to be sufficiently larger than the maximum value of the time difference d _t that can be detected by each IC 3, from the beginning when the basic clock signal K ₀ starts to change,
A delay of a fixed phase difference (t _p + d _t / 2) of the internal clock signal K _I with respect to the basic clock signal K ₀ is guaranteed.

Next, a second clock distribution system according to the present invention will be described in detail with reference to FIGS. 4, 5 and 6.

A second embodiment of the present invention, which is one embodiment of the second clock distribution system of the present invention shown in FIGS. 4, 5 and 6, is shown in FIGS. 1, 2 and 3. Based on the first embodiment of the present invention, the delay distribution clock signal K
It is simplified by using the distributed clock signal K _M itself instead of _DM , that is, assuming that t _d = 0, without using the delay means 4 for the time t _d and the second clock distribution circuit 2. Features.

Referring to FIG. 4, a first clock distribution circuit 1 according to a second embodiment of the present invention comprises a first clock driving circuit 11, a first terminating resistor 13, and the first terminating resistor 13. It is composed of a first transmission line 12 that is sending end terminated, the basic clock signal K ₀ to each of the n (n ≧ 2) pieces of IC3, sequentially distributed as distribution clock signal K _M.
The second embodiment shows an example where n = 5.

[0034] Here, the time from the first clock distribution circuit 1 is the basic clock signal K ₀ is input, until it as the initial amplitude waveform of the distribution clock signal K _M, reaches the input end of a certain one of IC3 a and t _p. Furthermore, the initial amplitude waveform of the distribution clock signal K _M from reaching the input end of the IC3, of the IC3 is reflected by the transmission terminal of the first transmission line 12 reaches the farthest end that is opposite The round trip time before returning to the input end is _dt .

The speed at which the signal waveform propagates on the first transmission line 12 is ideally constant in any portion. Since it can be considered practically almost constant, the time (t _p + d _t / 2) in each of the ICs 3 is completely equal to the first transmission line 12 after the signal is input to the first clock distribution circuit 1.
About the time it takes for the signal to reach the farthest end of
It is almost constant irrespective of the position of C3.

[0036] Each IC3 shown in FIG. 4, from the time the initial amplitude waveform of the distribution clock signal K _M to be dispensed by the first clock distribution circuit 1 reaches the input end of the IC3, the distribution clock signal the initial amplitude waveform of the K _M first
The time difference d _t from when the light reaches the farthest end, which is opposite to the sending end of the transmission line 12, is reflected and returns to the input end of the IC 3.
Detects the difference d the time at which the initial amplitude waveform of the distribution clock signal K _M reaches the input end of the IC3 as a base point
_t is the internal clock signal K delayed by half (d _t / 2)
Built-in internal clock generation means for generating _I. That is, the internal clock signal K _I is generated with a phase difference (t _p + d _t / 2) substantially behind the basic clock signal K ₀ .

Here, as described above, since the time (t _p + d _t / 2) in each IC 3 is almost constant regardless of the position of each IC 3, each internal signal generated in each IC 3 is not changed. clock signal K _I are all substantially constant phase difference with respect to the basic clock signal _{K 0 (t d + d t} /
Synchronize with a delay of 2).

Next, each IC3 in the second embodiment of the present invention will be described.
An example of the internal clock generating means incorporated in the CPU will be described below in detail with reference to a block diagram.

Referring to FIG. 5, the edge detection circuit 311
Is detectable compared to the first clock first row a rising edge of the distribution circuit distributing the clock signal K _M to be dispensed by 1 (Low) level reference signal V _RL shown in FIG. The edge detection circuit 312 outputs the distribution clock signal K _M
First rising edge of the first clock distribution circuit 1
Is detected by comparing with the high level reference signal V _RH when the signal reaches the farthest end, which is opposite to the sending end of the first transmission line 12, and rises again when reflected and returned. . Time difference detection circuit 32 detects the time difference d _t receives the respective output signals of the edge detection circuits 311 and 312, and outputs the time difference signal S _D to instruct half of said time difference (d _t / 2). The variable delay means 331 delays the output signal of the edge detection circuit 311 by half ( _dt / 2) of the time difference according to the time difference signal _{SD and} outputs it as a set signal. Edge detection circuit 312 also high the first falling edge of the distributed clock signal K _M (Hig
h) Compare with the level reference signal V _RH to detect and output to the variable delay means 332. The variable delay unit 332 delays the input signal from the edge detection circuit 312 by half the time difference ( _dt / 2) according to the time difference signal _{SD and} outputs the signal as a reset signal. The variable delay means 331 and 332 are
It is desirable to be composed of a variable delay line or a variable delay circuit. The flip-flop circuit 34 receives the set signal and the reset signal and performs the set operation and the reset operation to generate the internal clock signal K _I. By the above operation, the internal clock signal K _I
An initial amplitude waveform of the distribution clock signal K _M is delayed by half of the difference d _t as a base point time has been reached to the input terminal of the IC3 (d _t / 2).

Next, the operation of the second embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 6, K ₀ indicates the voltage waveform of the basic clock signal, K _M indicates the voltage waveform of the distributed clock signal at the input terminal of one IC 3, and K _I is generated in the IC 3. 3 shows a voltage waveform of an internal clock signal.

Referring to FIGS. 4 and 6, the distributed clock signal K _M are distributed via the first clock distribution circuit 1 based on the basic clock signal K _0. Here, since the clock distribution circuit 1 is terminated at the sending end, a certain 1
At the input terminals of the three ICs 3, the basic clock signal K ₀
Distribution clock signal K _M arriving from changing after a time t _p
, The initial amplitude is about 1 / max of the maximum amplitude
It becomes 2. Distribution clock signal K _M by reflected wave arrives from the farthest end to the transmitting end of the first transmission line 12 is opposite yet after a time d _t varies from the maximum amplitude. The first
The reflected wave reaching the sending end of the transmission line 12 does not reflect again due to the effect of the termination.

Next, the operation of one example of the internal clock generating means shown in FIG. 5 will be described in detail with reference to the drawings.

Referring to FIGS. 5 and 6 , in each IC 3, first, the edge of the distributed clock signal KM which rises by an initial amplitude of の of the maximum amplitude is delayed by a time tp from the rising time of the basic clock signal K0. (L
ow) The level reference signal VRL is compared with the edge detection circuit 311 and detected. After a time dt from the detection of the edge detection circuit 311, the edge which rises again to the maximum amplitude is detected by comparing the high level reference signal VRH with the edge detection circuit 312. The time difference dt can be detected by the operation of detecting these two edges. next,
The edge of the distributed clock signal KM, which is delayed by the time tp from the falling time of the basic clock signal K0 and falls by the initial amplitude which is 1/2 of the maximum amplitude, is compared with the high (High) level reference signal VRH and the edge detection circuit 312. Half of the detected time difference dt (d
A falling edge of the internal clock signal KI delayed by t / 2) is generated. On the other hand, the edge of the distributed clock signal KM which rises by an initial amplitude which is の of the maximum amplitude with a delay of time tp from the rising time of the basic clock signal K0 in the next cycle is detected by comparing with the low level reference signal VRL. And the internal clock K delayed by half (dt / 2) of the detected time difference dt from that time.
Generates a rising edge on I.

By operating as described above,
Each of the internal clock signals K _I generated in each IC 3 becomes a signal with a certain phase difference (t _p + d _t / 2) behind the basic clock signal K ₀ .

However, since the detection of the time difference _dt has not been performed before the first rising edge at which the basic clock signal K ₀ starts to change, the basic clock of the internal clock signal K _I is not detected. A delay of a constant phase difference (t _p + d _t / 2) with respect to the signal K ₀ is not guaranteed.

Further, as a feature of the clock distribution system of the present invention, the time difference d is always set while the system is operating.
_Since the detection of _t can be performed and the constant phase difference of the internal clock signal K _I with respect to the basic clock signal K ₀ can be continuously set, the plurality of clock distribution circuit groups in the large-scale synchronous digital data processing system can be set. Skew due to factors that occur during operation, such as partial temperature fluctuations within, can also be compensated.

Although the foregoing has been described with reference to certain preferred embodiments of the invention, various modifications in construction, arrangement and use may be made without departing from the true scope and spirit of the invention. It will be appreciated that is possible. Stated examples with reference to specific configurations, the detection time difference d _t is performed utilizing the edge of the distribution clock signal K _M which corresponds to the rise of the basic clock signal K ₀ in the embodiment described above, the basic clock signal or performed by using the edge of the distribution clock signal K _M corresponding to the fall of K _0, or may be configured to implement both. Further, in the above-described embodiment, the detection of the time difference _dt is always performed while the system is operating. However, the detection may be performed only at a specific time, for example, immediately after the system starts operating. Further, the invention described herein can also be used to control or deskew delay differences and skews created between other types of signals other than clock signals, and can be used for other than integrated circuit chips (ICs). Control or deskew signal delay differences and skews between circuits of other types and scales, such as circuits mounted on a housing, cage or board, or circuits that are components in an integrated circuit chip It can also be used for:

Accordingly, the invention is to be considered as embracing all possible modifications and alterations that fall within the scope of the appended claims.

[0050]

The clock distribution system according to the present invention has an IC
A clock distribution system with a very small clock skew is provided by keeping the clock distribution paths for a plurality of circuit groups such as... can do. As a result, more economically than before, and
A large-scale synchronous digital data processing system with higher performance than before can be realized.

[Brief description of the drawings]

FIG. 1 is a clock distribution circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of an internal clock generating unit according to the first embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a clock distribution circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing an example of an internal clock generating means according to a second embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st clock distribution circuit 2 2nd clock distribution circuit 3 Integrated circuit chip (IC) 4 Delay means 11 1st clock drive circuit 12 1st transmission line 13 1st terminal resistor 21 2nd clock drive circuit 22 second transmission line 23 and the second termination resistor 32 the time difference detection circuit 34 of the flip-flop circuit 311, 312, 313, 314 edge detection circuit 331 and 332 variable delay circuit K ₀ basic clock signal K _M distribution clock signal K _D delayed clock Signal _KDM Delay distribution clock signal K _I Internal clock signal _SD Time difference signal V _RH High level reference signal V _RL Low level reference signal _dt Time difference _dt / 2 Half time difference t _d + t _p + d _t / 2 Constant phase difference _{(1) t p + d t} / 2 constant phase difference (2)

Claims (4)

(57) [Claims] 1. A time difference between when an initial amplitude waveform of a distributed clock signal reaches a circuit input terminal, reaches a farthest end opposite to a transmitting end of a transmission line, is reflected, and returns to the circuit input terminal. A detection circuit; and an internal clock signal generation circuit that generates an internal clock signal delayed by half the time difference detected by the detection circuit after the initial amplitude waveform of the delay distribution clock signal reaches the circuit input terminal. And a clock distribution system. 2. A first clock for distributing a basic clock signal as a distributed clock signal to each of a plurality of circuit groups via a first clock driving circuit and a first transmission line serially terminated at a sending end. A distribution circuit; and a delay clock signal obtained by delaying the basic clock signal by a predetermined time, via a second clock drive circuit and a second transmission line serially terminated at a sending end of the plurality of circuit groups. A second clock distribution circuit configured to distribute each of the divided clock signals as a delay distribution clock signal, wherein each of the circuit groups has an initial amplitude waveform of the distribution clock signal that is an input terminal of each circuit of the circuit group. The time difference from when the initial amplitude waveform of the distributed clock signal reaches the farthest end, which is opposite to the sending end of the first transmission line, is reflected from the time when the distributed clock signal reaches the circuit group input end. Internal clock generating means for generating an internal clock signal delayed by half the time difference from the time when the initial amplitude waveform of the delayed distributed clock signal reaches the input terminal of each circuit of the circuit group. Characterized clock distribution system. 3. The circuit according to claim 1, wherein the initial amplitude waveform of the distributed clock signal is
After reaching the input end, reach the farthest end opposite to the sending end of the transmission line
To detect the time difference before returning to the circuit input terminal
A detection circuit, and an initial amplitude waveform of the distributed clock signal is input to the circuit input terminal.
And only half of the time difference detected by the detection circuit
Internal clock signal generation with delayed internal clock signal generation
And a clock distribution system. 4. A basic clock signal is driven by a first clock.
Via the circuit and the first transmission line terminated in series at the sending end
Distributed clock signal to each of multiple circuit groups
A first clock distribution circuit for distributing the clock signal , wherein each of the circuit groups has an initial amplitude waveform of the distributed clock signal corresponding to that of the circuit group.
From the time at which the input terminal of each circuit is reached, the distribution clock signal
The initial amplitude waveform of the signal is opposite to the transmission end of the first transmission line.
When it reaches the farthest end, it reflects and returns to the input end of the circuit group.
The initial amplitude of the distributed clock signal
Time when the waveform reached the input of each circuit in the circuit group
The internal clock signal delayed by half the time difference
Internal clock generation means for generating
Clock distribution system