JP2006217488A - Parallel-serial conversion circuit and parallel-serial converting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a parallel-serial conversion circuit and a parallel-serial converting method capable of performing high-speed parallel-serial conversion with a low frequency clock. <P>SOLUTION: The parallel-serial conversion circuit for converting n-bit parallel data into serial data is provided with an inputting part 2 for inputting parallel data, a clock generating part 1 for generating an n-phase data clock group having phase difference obtained by equally dividing a parallel data frequency into n parts by the same frequency as an input frequency of the parallel data, a synchronizing part for synchronizing each bit of the parallel data with each phase of the n-phase data clock group and outputting it as a synchronous data group, and a signal selecting part 4 for selecting synchronous data corresponding to the state of the data clock group from the synchronous data group and outputting the synchronous data as serial data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a parallel-serial conversion circuit and a parallel-serial conversion method, and more particularly to a parallel-serial conversion circuit and a parallel-serial conversion method for converting parallel data into serial data and outputting the serial data.

  For example, a parallel-serial conversion circuit using a shift register is generally known. A parallel-serial conversion circuit using a shift register has a data clock for transmitting serial data, a symbol clock for inputting parallel data, and a load signal for loading parallel data.

  The symbol clock is a data clock divided by n. In other words, the data clock has a frequency n times that of the symbol clock. The load signal is asserted in synchronization with the rising edge of the symbol clock. The load signal is synchronized with the data clock.

  The parallel data input from the outside is once fetched by the symbol clock, and is loaded into the shift register when the load signal is asserted. If the load signal is not asserted, the shift register is shifted bit by bit by the data clock to perform parallel-serial conversion.

  In a parallel-serial conversion circuit using a shift register, serial data is generated in synchronization with a data clock. Therefore, in order to perform high-speed parallel-serial conversion, a high-speed data clock is required. In today's high-speed serial transmission, a high-frequency (several GHz band) clock is required as a data clock.

  However, it is not easy to create a circuit that can transmit a high-frequency clock, and the scale becomes large. Further, when the clock frequency is increased, power consumption is significantly increased due to a through current of the clock buffer.

In a conventional parallel-serial conversion circuit, parallel-serial conversion is performed by reducing the frequency of a clock used as a data clock (see, for example, Patent Documents 1 and 2).
Japanese Patent Laid-Open No. 11-2105010 JP 2000-252839 A

  However, in the parallel-serial conversion described in Patent Document 1, the frequency of the data clock is determined to be n / 2 times that of the symbol clock. There was a problem that a clock had to be used.

  In the parallel-serial conversion described in Patent Document 2, a signal to be selected as an output is determined based on input parallel data. However, as the number of bits of parallel data increases, the processing becomes more complicated. It will become something. In addition, when data is converted, defects such as so-called beards and cracks are generated, and it is necessary to add a circuit for removing the defects, so that there is a problem that the circuit scale becomes large.

  The present invention has been made in view of the above points, and an object thereof is to provide a parallel-serial conversion circuit and a parallel-serial conversion method capable of performing high-speed parallel-serial conversion with a low-frequency clock.

  In order to solve the above-described problem, the present invention provides a parallel-serial conversion circuit that converts n-bit parallel data into serial data, the input unit that inputs the parallel data, and the same frequency as the input frequency of the parallel data And a clock generator for generating an n-phase data clock group having a phase difference obtained by dividing the period of the parallel data into n equal parts, and synchronizing each bit of the parallel data with each phase of the n-phase data clock group. A synchronization unit that outputs as a synchronization data group; and a signal selection unit that selects synchronization data corresponding to the state of the data clock group from the synchronization data group and outputs the data as serial data.

  The present invention is a parallel-serial conversion circuit for converting parallel data of n × k (n ≧ 3, k ≧ 2) bits into serial data, the input unit for inputting the parallel data, A clock generator for generating an n-phase data clock group having a phase difference obtained by dividing the period by n at a frequency k times the input frequency of the parallel data, and a conversion for converting the parallel data into n-bit parallel data A synchronization unit that synchronizes each bit of the n-bit parallel data with each phase of the n-phase data clock group and outputs it as a synchronization data group, and corresponds to the state of the data clock group from the synchronization data group And a signal selection unit that selects the synchronization data to be output and outputs the data as serial data.

  The present invention is also a parallel-serial conversion method for converting n-bit parallel data into serial data, wherein the n-bit parallel data has the same frequency as the input frequency of the parallel data and the period of the parallel data is changed. Synchronized with each phase of an n-phase data clock group having a phase difference divided by n, and outputs as a synchronous data group, and selects synchronous data corresponding to the state of the data clock group from the synchronous data group, and serial data Is output as

  The present invention is also a parallel-serial conversion method for converting n × k (n ≧ 3, k ≧ 2) bits of parallel data into serial data, the frequency being k times the input frequency of the parallel data. The parallel data is converted into n-bit parallel data by a clock composed of n-phase, and the n-phase parallel data has a phase difference obtained by dividing the cycle by n at a frequency k times the input frequency of the parallel data. The data clock group is synchronized with each phase of the data clock group and output as a synchronous data group, and the synchronous data corresponding to the state of the data clock group is selected from the synchronous data group and output as serial data.

  In the present invention, high-speed parallel-serial conversion can be performed with a low-frequency clock by using a multi-phase clock. In addition, by using a multiphase clock with a small phase difference, desired serial data can be generated with time resolution that cannot be obtained with a simple clock.

  According to the present invention, it is possible to provide a parallel-serial conversion circuit and a parallel-serial conversion method capable of performing high-speed parallel-serial conversion with a low-frequency clock.

  Next, the best mode for carrying out the present invention will be described based on the following embodiments with reference to the drawings.

  FIG. 1 is a block diagram of a first embodiment of a parallel-serial conversion circuit according to the present invention. FIG. 2 is a timing chart of each signal in the parallel-serial conversion circuit. In the timing chart of FIG. 2, data clocks [0] to [3] represent the 0th to 3rd bits of the data clock, respectively, and the same applies to other signals. In the parallel data pattern of FIG. 2, LSB (0th bit) is on the right side. Further, in the first embodiment, an example in which 4-bit parallel data is converted into serial data will be described, but the present invention is not limited to this.

  The parallel-serial conversion circuit of FIG. 1 includes a clock generation unit 1, an input unit 2, a synchronization circuit 3, and a signal selection circuit 4. The clock generator 1 generates a symbol clock shown in FIG. 2A and inputs it to the input unit 2. The input unit 2 inputs parallel data shown in FIG. 2B to the synchronization circuit 3 in synchronization with the symbol clock. Specific examples of the input unit 2 include an appropriate logic circuit such as an image processing device.

  The clock generator 1 generates a data clock group shown in FIGS. 2C to 2F and inputs it to the synchronization circuit 3 and the signal selection circuit 4. The symbol clock has the same frequency as the data clock group and the same (substantially the same) phase as one data clock in the data clock group. Therefore, the parallel data is input to the synchronization circuit 3 in synchronization with one data clock in the data clock group.

  For example, in the timing chart of FIG. 2, parallel data is input to the synchronization circuit 3 in synchronization with the data clock [0], but this is not necessarily the case. A specific example of the clock generator 1 is a PLL (Phase Locked Loop) circuit or the like. For example, if the number of bits n of parallel data is an even number, the oscillation unit of the PLL circuit is configured by an n / 2-stage differential ring oscillator as shown in FIG. It is possible to generate a data clock group having a phase difference divided into n equal parts.

  In FIG. 1, the synchronization circuit 3 retakes the parallel data shown in FIG. 2 (b) so as to be synchronized with the data clock shown in FIGS. 2 (c) to 2 (f), and the synchronization shown in FIGS. 2 (g) to (j). The data group is output to the signal selection circuit 4. Each bit of the synchronization data is synchronized with the data clock having the same bit number. That is, the synchronization data [m] is output from the synchronization circuit 3 in synchronization with the data clock [m].

  For example, a specific example of the synchronization circuit 3 includes a flip-flop configuration as shown in FIG. As shown in the timing chart of FIG. 2, the synchronization circuit 3 can output a synchronized data group synchronized with each data clock.

  The signal selection circuit 4 selects one synchronous data whose output is valid from the synchronous data group based on the state of the data clock group, and outputs it as serial data shown in FIG. As a specific example of the signal selection circuit 4, as shown in FIG. 5, there is a configuration in which two switches are connected in series with respect to each synchronization data and the respective output nodes are connected.

  For example, it is assumed that the switch is turned on when a signal entering each switch is High (hereinafter simply referred to as H). In the case of a switch that selects the m-th synchronization data [m], for example, if the number of bits n of the parallel data is an even number, the data clock [m + 1] and the data clock [m + n / 2] are used as on / off signals for controlling the switch. And can be used. Even if the number of bits n of the parallel data is an odd number, an appropriate data clock can be used as an on / off signal for the switch.

  In the example of FIG. 5, the data clock [1] and the data clock [2] are used as ON / OFF signals of the two switches for the synchronous data [0], respectively. If both switches are on, the synchronization data [0] is output as serial data. If at least one of the switches is off, the output node becomes high impedance, the synchronization data [0] is not output, and any other synchronization data is output.

  Therefore, the serial data output from the parallel-serial conversion circuit according to the present invention is obtained by converting the input parallel data into serial data as shown in FIG. In this way, serial data having a faster frequency than the data clock can be output by performing parallel-serial conversion using the multi-phase data clock group.

  The parallel-serial conversion circuit of the present invention can perform parallel-serial conversion with a low-frequency data clock, and can reduce circuit scale and power consumption. In addition, since the phase difference of the multi-phase data clock group becomes the time resolution as it is, the serial data controlled in units of tens of picoseconds that cannot be obtained with a simple clock as shown in FIG. 6 is generated. You can also.

  In the parallel-serial conversion circuit of the first embodiment, since parallel-serial conversion is performed using a multi-phase data clock having a frequency lower than that of the serial data to be output, a circuit for using a high-frequency clock is unnecessary. This leads to a reduction in circuit scale and power consumption, thereby realizing cost reduction.

  FIG. 7 is a block diagram of a second embodiment of the parallel-serial conversion circuit according to the present invention. FIG. 8 is a timing chart of each signal in the parallel-serial conversion circuit. In the timing chart of FIG. 8, data clocks [0] to [3] represent the 0th to 3rd bits of the data clock, respectively, and the same applies to other signals. In the second embodiment, an example in which parallel data of 8 (4 × 2) bits is converted into serial data will be described, but the present invention is not limited to this.

  The parallel-serial conversion circuit of FIG. 7 includes a synchronization circuit 3, a signal selection circuit 4, an input unit 5, a conversion circuit 6, and a clock generation unit 7. The clock generation unit 7 generates a symbol clock a shown in FIG. 8A and inputs it to the input unit 5. The input unit 5 inputs 8-bit parallel data to the conversion circuit 6 in synchronization with the symbol clock a.

  The clock generation unit 7 generates a symbol clock b shown in FIG. 8B and inputs it to the conversion circuit 6. The conversion circuit 6 converts 8-bit parallel data into 4-bit parallel data in synchronization with the symbol clock b. The conversion circuit 6 inputs the converted 4-bit parallel data to the synchronization circuit 3 in synchronization with the symbol clock b.

  The clock generator 7 generates a data clock group shown in FIGS. 8C to 8F and inputs it to the synchronization circuit 3 and the signal selection circuit 4. Here, the symbol clock b has a frequency k times that of the symbol clock a, and the rising edge is synchronized with the rising edge of the symbol clock a. The symbol clock b has the same frequency as the data clock group, and is the same as the relationship between the symbol clock and the data clock group in the first embodiment.

  A specific example of the conversion circuit 6 includes a configuration in which n k-bit parallel-serial conversion units using a normal shift register are arranged in parallel. In the parallel-serial conversion circuit of the first embodiment, as many data clocks as the number of bits subjected to parallel-serial conversion are required. For this reason, in the parallel-serial conversion circuit of the first embodiment, not only the current consumption increases in proportion to the number of bits subjected to parallel-serial conversion, but also problems such as skew between data clocks due to layout become significant.

  In the parallel-serial conversion circuit of the second embodiment, the frequency band of the symbol clock b is selected so that the conversion circuit 6 can perform parallel-serial conversion with a margin so that the number of bits subjected to parallel-serial conversion can be increased. An increase in circuit scale and power consumption due to the increase can be avoided.

  In FIG. 7, the synchronization circuit 3 receives 4-bit parallel data similar to that of the first embodiment from the conversion circuit 6 in synchronization with the symbol clock b. Therefore, the processing of the synchronization circuit 3 and the signal selection circuit 4 is the same as that of the first embodiment, and the description is omitted.

  In the parallel-serial conversion circuit of the second embodiment, n × k (n ≧ 3, integers of k ≧ 2) bits of parallel-serial conversion can be performed without using a high-frequency data clock, and the circuit scale and power consumption. This can be realized with a configuration that suppresses this. In addition, the description about the same part as said parallel-serial conversion circuit was abbreviate | omitted suitably.

  FIG. 9 is a block diagram of a third embodiment of the parallel-serial conversion circuit according to the present invention. The parallel-serial conversion circuit of FIG. 9 has a configuration in which a selection signal generation circuit 8 is added to the parallel-serial conversion circuit of the first embodiment. The parallel-serial conversion circuit of FIG. 9 includes a clock generation unit 1, an input unit 2, a synchronization circuit 3, a selection signal generation circuit 8, and a signal selection circuit 9.

  The selection signal generation circuit 8 receives the 4-bit data clock group shown in FIGS. 2C to 2F from the clock generation unit 1 and outputs a 4-bit data based on the state of the 4-bit data clock group. A selection signal is generated and output to the signal selection circuit 9. The signal selection circuit 9 selects one synchronization data from the synchronization data group based on the 4-bit output selection signal input from the selection signal generation circuit 8 and outputs it as serial data.

  The signal selection circuit 9 in the parallel-serial conversion circuit of the third embodiment can be made simpler than the configuration of the signal selection circuit 4 in the parallel-serial conversion circuit of the first embodiment. For example, when the number of bits n of the parallel data is an even number, specific examples of the selection signal generation circuit 8 and the signal selection circuit 9 include a configuration as shown in FIG.

  If the number of bits n of the parallel data is an even number, the output selection signal for selecting the m-th synchronization data [m] can be a logical product of the data clock [m + 1] and the data clock [m + n / 2]. In other words, with the configuration shown in FIG. 10, one switch can be provided for each synchronization data. Even if the number of parallel data bits n is an odd number, an appropriate logical product of data clocks can be used as an output selection signal.

  Since the output of the signal selection circuit 9 is output as serial data as it is, simplifying the configuration of the signal selection circuit 9 affects the quality of the serial data. Specifically, there are effects such as jitter reduction. Therefore, in the parallel-serial conversion circuit of the third embodiment, the number of circuit elements serving as output signal loads can be reduced, so that the quality of serial data can be improved. In addition, the description about the same part as said parallel-serial conversion circuit was abbreviate | omitted suitably.

  FIG. 11 is a block diagram of a fourth embodiment of the parallel-serial conversion circuit according to the present invention. The parallel-serial conversion circuit of FIG. 11 has a configuration in which a selection signal generation circuit 8 is added to the parallel-serial conversion circuit of the second embodiment. The parallel-serial conversion circuit of FIG. 11 includes a synchronization circuit 3, an input unit 5, a conversion circuit 6, a clock generation unit 7, a selection signal generation circuit 8, and a signal selection circuit 9.

  The selection signal generation circuit 8 receives the 4-bit data clock group shown in FIGS. 8C to 8F from the clock generation unit 7 and outputs a 4-bit data based on the state of the 4-bit data clock group. A selection signal is generated and output to the signal selection circuit 9. The signal selection circuit 9 selects one synchronization data from the synchronization data group based on the 4-bit output selection signal input from the selection signal generation circuit 8 and outputs it as serial data.

  The signal selection circuit 9 in the parallel-serial conversion circuit of the fourth embodiment can be made simpler than the configuration of the signal selection circuit 4 in the parallel-serial conversion circuit of the second embodiment. Since the output of the signal selection circuit 9 is output as serial data as it is, simplifying the configuration of the signal selection circuit 9 affects the quality of the serial data. Specifically, there are effects such as jitter reduction.

  Therefore, in the parallel-serial conversion circuit of the fourth embodiment, the number of circuit elements serving as output signal loads can be reduced, so that the quality of serial data can be improved. In addition, the description about the same part as said parallel-serial conversion circuit was abbreviate | omitted suitably.

  FIG. 12 is a block diagram of a fifth embodiment of a parallel-serial conversion circuit according to the present invention. FIG. 13 is a timing chart of each signal in the parallel-serial conversion circuit. In the timing chart of FIG. 13, data clocks [0] to [3] represent the 0th to 3rd bits of the data clock, respectively, and the same applies to other signals. In the fifth embodiment, an example in which 4-bit parallel data is converted into serial data will be described. However, the present invention is not limited to this.

  The parallel-serial conversion circuit of FIG. 12 includes a clock generation unit 1, an input unit 2, a synchronization circuit 3, a data generation circuit 10, and an output signal generation circuit 11. The clock generator 1 generates a data clock group shown in FIGS. 13A to 13D and inputs it to the synchronization circuit 3 and the data generation circuit 10. The synchronization circuit 3 outputs an n-bit synchronization data group shown in FIGS. 13 (e) to 13 (h) to the data generation circuit 10.

  The data generation circuit 10 generates an n-bit data signal group shown in FIGS. 13 (i) to 13 (l) from an appropriate data clock corresponding to the synchronization data of each bit, and outputs it to the output signal generation circuit 11.

  As a specific example of a specific n-bit data signal group, there is a configuration in which it is H only when the serial data to be output is H, and L otherwise. The output signal generation circuit 11 can output the serial data shown in FIG. 13M by taking the logical sum of all the n-bit data signal groups.

  For example, if the number of bits n of the parallel data is an even number, the data signal output from the data generation circuit 10 is synchronized data [m], data clock [m + 1], and data clock [m + n / 2] as shown in FIG. ]. The output signal generation circuit 11 can obtain serial data from the logical sum of the generated n-bit data signal group. Even if the number of bits n of the parallel data is an odd number, an n-bit data signal group can be generated by selecting appropriate synchronization data and a data clock.

  In the parallel-serial conversion circuit of the fifth embodiment, the data signal is clocked and the output signal generation circuit 11 is directly driven by the data signal, so that high-precision serial data can be output at a higher speed. In addition, the description about the same part as said parallel-serial conversion circuit was abbreviate | omitted suitably.

  FIG. 14 is a block diagram of a sixth embodiment of the parallel-serial conversion circuit according to the present invention. In the sixth embodiment, an example in which 8-bit parallel data is converted into serial data will be described, but the present invention is not limited to this.

  The parallel-serial conversion circuit of FIG. 14 includes a synchronization circuit 3, an input unit 5, a conversion circuit 6, a clock generation unit 7, a data generation circuit 10, and an output signal generation circuit 11. The clock generation unit 7 generates a data clock group and inputs it to the synchronization circuit 3 and the data generation circuit 10. The synchronization circuit 3 outputs an n-bit synchronization data group to the data generation circuit 10. The data generation circuit 10 generates an n-bit data signal group from an appropriate data clock corresponding to the synchronization data of each bit, and outputs it to the output signal generation circuit 11.

  In the parallel-serial conversion circuit of the sixth embodiment, the data signal is clocked and the output signal generation circuit 11 is directly driven by the data signal. Therefore, high-precision serial data can be output at a higher speed. In addition, the description about the same part as said parallel-serial conversion circuit was abbreviate | omitted suitably.

  FIG. 15 is a block diagram of a seventh embodiment of a parallel-serial conversion circuit according to the present invention. The parallel-serial conversion circuit of FIG. 15 has two signal selection circuits 4 of the parallel-serial conversion circuit of the first embodiment, and outputs serial data as a differential signal. The synchronizing circuit 12 is a signal selection circuit for differentiating a synchronized data group in which the input parallel data is directly synchronized with the data clock group and an inverted data group in which the input parallel data is inverted and synchronized with the data clock group. 4 is output. The parallel-serial conversion circuit of FIG. 15 can output a normal signal and an inverted signal based on the same parallel data as differential serial data.

  For example, in today's high-speed serial transmission techniques such as PCI-Express and Serial-ATA, a technique called LVDS (Low Voltage Differential Signaling) with low power consumption and high noise resistance is often used. In LVDS, transmission using differential signals is the mainstream. In the parallel-serial conversion circuit of FIG. 15, the normal signal and the inverted signal are generated based on the same data clock, so that the signal-to-signal skew of the generated differential signal can be reduced.

  The parallel-serial conversion circuits of FIGS. 16 to 20 are different from the parallel-serial conversion circuits of the second to sixth embodiments in the difference between the output serial data as in the parallel-serial conversion circuit of FIG. It is a dynamic signal. In the parallel-serial conversion circuit of the seventh embodiment, parallel-serial conversion that can obtain a differential signal with little skew can be realized without using a high-frequency data clock.

  That is, the parallel-serial conversion circuit of FIGS. 16 to 20 can output a differential signal suitable for the LVDS transmission standard. In addition, the description about the same part as said parallel-serial conversion circuit was abbreviate | omitted suitably.

  The above-described parallel-serial conversion circuit includes the clock generation units 1 and 7. However, it is difficult to consider providing the clock generation units 1 and 7 for only one parallel-serial conversion circuit from the viewpoint of cost and the like. In actual circuits, modules having various functions are often combined to form one system. The clock supplied to all the modules is generally generated by a single clock generator.

  Therefore, for example, a distance of several hundred microns to several millimeters can be taken between the clock generator 1 constituting the parallel-serial conversion circuit of the first embodiment and each other circuit. In general, when the transmission distance of a signal becomes long, the influence of reflection due to impedance mismatching becomes significant and affects the quality of the transmitted signal. The long transmission distance referred to here is a length of approximately λ / 4 or more when the wavelength of the high frequency component included in the signal is λ.

  In the parallel-serial conversion circuit described above, reflection occurs due to impedance mismatch in the transmission path of the data clock group, and the phase relationship of the data clock group is disturbed. When the phase relationship of the data clock group input to the synchronization circuit 3 is disturbed, the parallel-serial conversion circuit has a problem that the jitter of the serial data output increases.

  Therefore, in the parallel-serial conversion circuit of the eighth embodiment, the clock transmission units of the clock generation units 1 and 7, the clock reception units of the synchronization circuits 3 and 12, the clock generation units 1 and 7 and the synchronization circuits 3 and 12 are provided. It is a requirement that impedance matching be achieved in each transmission line to be connected.

  Therefore, reflections occurring at both ends of transmission and reception can be reduced, and the data clock group received by the synchronization circuits 3 and 12 can maintain the same phase relationship as the original transmitted state, so that it is output. Jitter of serial data can be reduced.

  As an example of a transmission line considering such impedance matching, a configuration as shown in FIG. On the clock transmission side, the data clock to be transmitted is output from the buffer 21 and then output to the transmission line 23 through a resistor 22 having an appropriate impedance Z0 in series. By setting the layout of the transmission path 23 through which the data clock passes to have a constant line width w, the transmission path 23 can be considered as a strip line in the chip. Since the characteristic impedance of the strip line changes approximately in inverse proportion to the line width w, the line width w can be determined based on other device parameters, and the characteristic impedance of the transmission line 23 can be set to Z0.

  On the clock receiving side, the data clock is grounded by the resistor 24 having the impedance Z0 and received by the buffer 25. In the configuration as shown in FIG. 21, the characteristic impedance of each of the transmission side, transmission path, and reception side can be set to Z0, and a transmission path with impedance matching can be realized.

  In the parallel-serial conversion circuit according to the eighth embodiment, since the data clock is transmitted using the impedance-matched transmission path, the data-clock generation circuit and the parallel-serial conversion circuit are stable even if the distance is long. Quality serial data can be output, and versatility can be improved.

  FIG. 22 is a block diagram of a ninth embodiment of a parallel-serial conversion circuit according to the present invention. The parallel-serial conversion circuit of FIG. 22 has a configuration in which a multiphase clock generation unit 14 is added to the parallel-serial conversion circuit of the first embodiment. The parallel-serial conversion circuit of FIG. 22 includes a clock generation unit 1, an input unit 2, a synchronization circuit 3, a signal selection circuit 4, and a multiphase clock generation unit 14.

  The multiphase clock generation unit 14 receives the symbol clock from the clock generation unit 1 and generates a data clock group based on the symbol clock. The multiphase clock generation unit 14 inputs the generated data clock group to the synchronization circuit 3 and the signal selection circuit 4. The data clock group generated by the multiphase clock generation unit 14 has the same frequency as the symbol clock. One data clock in the data clock group is generated to have the same phase as the symbol clock. Therefore, the parallel data is input to the synchronization circuit 3 in synchronization with one data clock in the data clock group. A specific example of the multiphase clock generation unit 14 is a phase delay circuit such as a DLL circuit.

  With the circuit configuration as shown in FIG. 22, the clock output from the clock generator 1 may be a single phase clock. Therefore, the clock generator 1 can be placed on the IC chip at a position away from the parallel-serial conversion circuit. Further, since the clock output from the clock generator 1 can be supplied to other logic circuits, it can be easily used in combination with other circuits. Furthermore, since the multiphase clock is generated by the multiphase clock generation unit 14 in the parallel-serial conversion circuit, phase errors due to variations in clock transmission can be suppressed, and jitter of serial data to be output can be reduced.

  The parallel-serial conversion circuits of FIGS. 23 to 33 are the same as the parallel-serial conversion circuit of FIG. 22 in the parallel-serial conversion circuits of the second to seventh embodiments. This is a configuration in which 15 is added. In addition, the description about the same part as said parallel-serial conversion circuit was abbreviate | omitted suitably.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

1 is a configuration diagram of a first embodiment of a parallel-serial conversion circuit according to the present invention; FIG. It is a timing chart of each signal in a parallel-serial conversion circuit. It is a block diagram showing the specific example of a clock generation part. It is a block diagram showing the specific example of a synchronizing circuit. It is a block diagram showing the specific example of a signal selection circuit. It is the schematic showing the relationship between the phase difference of a multiphase data clock group, and the controlled serial data. It is a block diagram of 2nd Example of the parallel-serial conversion circuit by this invention. It is a timing chart of each signal in a parallel-serial conversion circuit. It is a block diagram of 3rd Example of the parallel-serial conversion circuit by this invention. It is a block diagram showing the specific example of a selection signal generation circuit and a signal selection circuit. It is a block diagram of 4th Example of the parallel-serial conversion circuit by this invention. It is a block diagram of 5th Example of the parallel-serial conversion circuit by this invention. It is a timing chart of each signal in a parallel-serial conversion circuit. It is a block diagram of 6th Example of the parallel-serial conversion circuit by this invention. FIG. 10 is a configuration diagram (No. 1) of a seventh embodiment of the parallel-serial conversion circuit according to the present invention; FIG. 10 is a configuration diagram (No. 2) of the seventh embodiment of the parallel-serial conversion circuit according to the present invention; FIG. 12 is a configuration diagram (No. 3) of the seventh embodiment of the parallel-serial conversion circuit according to the present invention; FIG. 11 is a configuration diagram (No. 4) of a seventh embodiment of the parallel-serial conversion circuit according to the present invention; It is a block diagram (the 5) of the 7th Example of the parallel-serial conversion circuit by this invention. FIG. 10 is a configuration diagram (No. 6) of a seventh embodiment of the parallel-serial conversion circuit according to the present invention; It is a block diagram which shows an example of the transmission line which considered impedance matching. It is the block diagram (the 1) of 9th Example of the parallel-serial conversion circuit by this invention. It is the block diagram (the 2) of 9th Example of the parallel-serial conversion circuit by this invention. It is a block diagram (the 3) of 9th Example of the parallel-serial conversion circuit by this invention. FIG. 14 is a configuration diagram (No. 4) of a ninth embodiment of the parallel-serial conversion circuit according to the present invention; It is a block diagram (the 5) of 9th Example of the parallel-serial conversion circuit by this invention. It is a block diagram (the 6) of the 9th Example of the parallel-serial conversion circuit by this invention. It is a block diagram (the 7) of 9th Example of the parallel-serial conversion circuit by this invention. It is a block diagram (the 8) of 9th Example of the parallel-serial conversion circuit by this invention. It is a block diagram (the 9) of the 9th Example of the parallel-serial conversion circuit by this invention. It is a block diagram (the 10) of the 9th Example of the parallel-serial conversion circuit by this invention. It is a block diagram (the 11) of 9th Example of the parallel-serial conversion circuit by this invention. It is a block diagram (the 12) of 9th Example of the parallel-serial conversion circuit by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,7 Clock generation part 2 Input part 3,12 Synchronous circuit 4,9 Signal selection circuit 5 Input part 6 Conversion circuit 8 Selection signal generation circuit 10,13 Data generation circuit 11 Output signal generation circuit 14,15 Multiphase clock generation part 21, 25 Buffer 22, 24 Resistance 23 Transmission path

Claims (16)

A parallel-serial conversion circuit for converting n-bit parallel data into serial data,
An input unit for inputting the parallel data;
A clock generation unit for generating an n-phase data clock group having a phase difference obtained by dividing the period of the parallel data by n at the same frequency as the input frequency of the parallel data;
A synchronization unit that synchronizes each bit of the parallel data with each phase of the n-phase data clock group, and outputs the synchronized data group as a synchronization data group;
A parallel-serial conversion circuit comprising: a signal selection unit that selects synchronous data corresponding to the state of the data clock group from the synchronous data group and outputs it as serial data.   2. The parallel-serial conversion circuit according to claim 1, wherein the number n of bits of the parallel data is 3 bits or more, and the n-phase data clock group is 3 phases or more. A parallel-serial conversion circuit for converting parallel data of n × k (n ≧ 3, k ≧ 2) bits into serial data,
An input unit for inputting the parallel data;
A clock generator for generating an n-phase data clock group having a phase difference obtained by dividing the period by n at a frequency k times the input frequency of the parallel data;
A conversion unit for converting the parallel data into n-bit parallel data;
A synchronizing unit that synchronizes each bit of the n-bit parallel data with each phase of the n-phase data clock group, and outputs the synchronized data group;
A parallel-serial conversion circuit comprising: a signal selection unit that selects synchronous data corresponding to the state of the data clock group from the synchronous data group and outputs it as serial data.   4. The characteristic impedance of a transmission path for transmitting the n-phase data clock group generated by the clock generation unit is the same value as the characteristic impedance on the transmission side and the reception side. The parallel-serial conversion circuit according to one item. The clock generator generates a symbol clock having a frequency equal to or k times the input frequency of the input parallel data;
5. The parallel according to claim 1, further comprising: a data clock generation unit configured to generate the n-phase data clock group having a phase difference obtained by dividing the symbol clock period into n equal parts based on the symbol clock. -Serial conversion circuit. A selection signal generation unit that generates an output selection signal based on the state of the n-phase data clock group;
6. The parallel-serial conversion circuit according to claim 1, wherein the signal selection unit selects synchronization data from the synchronization data group based on the output selection signal and outputs the data as serial data. .   A data generation unit that generates a signal group based on the data clock group and the synchronous data group; an output signal that generates an output signal based on the generated signal group and outputs the output signal as serial data; 6. The parallel-serial conversion circuit according to claim 1, wherein the parallel-serial conversion circuit is replaced with a generation unit.   8. The parallel-serial conversion circuit according to claim 1, wherein the serial data is output as a differential signal. A parallel-serial conversion method for converting n-bit parallel data into serial data,
The n-bit parallel data is output as a synchronized data group in synchronization with each phase of an n-phase data clock group having a phase difference obtained by dividing the period of the parallel data by n at the same frequency as the input frequency of the parallel data. And
A parallel-serial conversion method, wherein synchronous data corresponding to a state of the data clock group is selected from the synchronous data group and output as serial data.   10. The parallel-serial conversion method according to claim 9, wherein the number of bits n of the parallel data is 3 bits or more, and the n-phase data clock group is 3 phases or more. A parallel-serial conversion method for converting parallel data of n × k (n ≧ 3, k ≧ 2) bits into serial data,
The parallel data is converted into n-bit parallel data by a clock having a frequency k times the input frequency of the parallel data,
The n-bit parallel data is output as a synchronized data group in synchronization with each phase of an n-phase data clock group having a phase difference obtained by dividing the period by n at a frequency k times the input frequency of the parallel data. ,
A parallel-serial conversion method, wherein synchronous data corresponding to a state of the data clock group is selected from the synchronous data group and output as serial data.   12. The parallel-serial conversion according to claim 9, wherein a characteristic impedance of a transmission line that transmits the n-phase data clock group has the same value as a characteristic impedance of a transmission side and a reception side. Method. Generating a symbol clock having a frequency equal to or k times the input frequency of the input parallel data;
13. The parallel-serial according to claim 9, wherein the n-phase data clock group having a phase difference obtained by equally dividing the symbol clock period into n equal parts is generated based on the symbol clock. Conversion method. An output selection signal is generated based on the state of the n-phase data clock group,
14. The parallel-serial conversion method according to claim 9, wherein synchronous data is selected from the synchronous data group based on the output selection signal and is output as serial data. A signal group is generated based on the data clock group and the synchronous data group,
The parallel-serial conversion method according to any one of claims 9 to 13, wherein an output signal is generated based on the generated signal group and output as serial data.   16. The parallel-serial conversion method according to claim 9, wherein the serial data is output as a differential signal.

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