JP2006121247A - Signal transmission system and signal waveform conversion circuit and signal waveform restoration circuit for use therein - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent impact on other circuit when a transmission signal is transmitted by lowering signal frequency as much as possible, and to transmit a signal while removing noise. <P>SOLUTION: On the signal transmission side, frequency of a signal to be transmitted is divided using a frequency division circuit 20 functioning as a signal waveform conversion circuit and a pair of signals Q1 and Q2 having different phases are produced and transmitted through a transmission path. On the reception side, a level corresponding to the combination of level of the pair of signals is generated using a signal waveform restoration circuit 21 and the original signal is restored. Since the frequency of the signal is halved by frequency division on the transmission path, impact on other circuit is suppressed and since it is simply required to transmit a pair of signals from the transmission side to all reception side circuits, output pins can be decreased sharply on the transmission side. Furthermore, noise can be reduced by adding a noise removing function, i.e. a protective circuit 22 in the frequency division circuit 20. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a signal transmission system, a signal waveform conversion circuit and a signal waveform restoration circuit used therefor, and more particularly, a signal transmission system used between electronic circuits in an electronic device such as an information processing device and a communication device, and a signal waveform conversion circuit used therefor The present invention also relates to a signal waveform restoration circuit.

  An information processing apparatus includes a system configured as shown in FIG. That is, one host PLD (Programmable Logic Device) 1 and a plurality of slave PLDs 2a to 2e connected in parallel to the host PLD1 are provided. Each of these PLDs 2a to 2e includes, for example, two Each memory (shown as 3 in the figure) is connected. Accordingly, these PLDs 2a to 2e function as dual memory controllers. The host PLD1 is supplied with a clock CLK and a write enable signal WE, and these CLK and WE signals are distributed and transmitted to the PLDs 2a to 2e connected in parallel.

  In this way, when a PLD or the like is connected in parallel and a signal having a frequency at which the influence of the reflected wave or the like cannot be ignored is used, as shown in FIG. 8, the host PLD1 and each of the PLDs 2a to 2e are connected. The connection relationship between them is preferably a wiring that is 1: 1. However, in such a wiring method, the number of output pins of the PLD 1 increases, resulting in an increase in cost, and the number of wirings on the printed wiring board increases, resulting in a decrease in the degree of freedom in designing the board wiring. Become.

  Further, as the signal becomes higher in frequency, problems such as crosstalk noise with respect to other signal lines occur, and as a result, the difficulty level of the substrate wiring is further increased. Therefore, when distributing and transferring a signal to a plurality of electronic circuits such as PLDs connected in parallel, it has a noise removal function and has a signal frequency as low as possible to reduce crosstalk noise to other signal lines, etc. Therefore, a signal waveform conversion circuit having a waveform shaping function so as to eliminate the influence of the above is desired.

Here, referring to Patent Document 1, a clock signal abnormality detection circuit is disclosed. In this circuit, an input clock signal abnormality is detected by sampling the divide-by-2 signal at a timing that is obtained by delaying the divided-by-2 signal of the input clock signal by approximately ½ period of the input clock signal. It does not exclude adverse effects on peripheral circuits such as noise removal function and crosstalk noise.
JP 2002-026704 A

  Therefore, the present invention provides a signal transmission system having a noise removal function and capable of eliminating adverse effects on other signal lines by reducing the signal frequency as much as possible, and a signal waveform conversion circuit and a signal waveform restoration circuit used therefor. It is intended to provide.

  The present invention also provides a signal transmission system capable of reducing the number of signal pins and the number of wires when distributing and transmitting a signal to a plurality of electronic circuits, and a signal waveform conversion circuit and a signal waveform restoration circuit used therefor. It is an object.

  The signal waveform conversion circuit according to the present invention includes frequency dividing means that divides an input signal, converts the input signal into a pair of signals having mutually different phases, and outputs the signals. The frequency dividing means includes a first frequency dividing element that performs a frequency dividing operation in response to a rising edge of the input signal, and a second frequency divider that performs a frequency dividing operation in response to the falling edge of the input signal. A frequency divider, and outputs the outputs of the first and second frequency dividers as the pair of signals.

  The first and second frequency dividing elements are flip-flop circuits, and an output of the first frequency dividing element is supplied to a data input terminal of the flip-flop circuit of the second frequency dividing element. The output of the second frequency dividing element is supplied to the data input terminal of the flip-flop circuit of the first frequency dividing element. In addition, the output of the frequency dividing element is supplied to the data input terminal of the flip-flop via a delay unit.

  A signal waveform restoration circuit according to the present invention is a signal waveform restoration circuit that divides a signal to be transmitted and receives and restores a signal converted into a pair of signals having different phases, and the level of the pair of signals It has a means to generate | occur | produce the signal which has a level according to the combination of this, and decompress | restore the said signal which should be transmitted.

  The signal transmission system according to the present invention has the signal waveform conversion circuit on the signal transmission side and the signal waveform restoration circuit on the signal reception side. A plurality of the signal waveform restoration circuits are connected in parallel.

  The operation of the present invention will be described. In the signal waveform conversion circuit on the signal transmission side, a signal to be transmitted is frequency-divided using a frequency dividing element, converted into a pair of signals having different phases, and transmitted via a transmission line. On the receiving side, a signal waveform restoration circuit is used to generate a level corresponding to the combination of the levels of the pair of signals to restore the original signal. In the transmission line, the frequency of the signal is reduced to half by the frequency division process, so that the influence on other circuits is reduced, and even when there are multiple circuits on the receiving side, a pair of signals from the transmitting side are all transmitted. Since it only needs to be transmitted to the circuit on the reception side, the output pins on the transmission side are greatly reduced. Furthermore, noise can be reduced by adding a noise removal function to the signal waveform conversion circuit on the transmission side.

  According to the present invention, by dividing the input signal and reducing the frequency by half, it is possible to reduce adverse external effects such as crosstalk noise on peripheral circuits.

  According to the present invention, when dividing the input signal, both rising and falling edge components are divided with a protection circuit, so that noise such as ringing and other abnormal pulses are removed. There is an effect that a stable signal waveform can be output.

  According to the present invention, since the signal frequency is halved, the pattern design difficulty can be reduced, and there is an effect that various signal wirings such as 1: N (N is an integer of 2 or more) are facilitated. .

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention. Referring to FIG. 1, the present embodiment includes a frequency dividing circuit 20 as a signal waveform conversion circuit and a signal waveform restoration circuit 21 (simply referred to as a restoration circuit). The frequency divider circuit 20 divides the input signal IN1 (clock signal CLK and write enable signal WE) to be branched into 1/2 and outputs a pair of frequency-divided outputs Q1 and Q2 having the same frequency and different phases. And operates as a signal waveform conversion circuit having a noise removal function.

  The restoration circuit 21 has a function of deriving a signal OUT1 having the same frequency as that of the original signal (IN1) with the pair of divided outputs Q1 and Q2 from the frequency dividing circuit 20 as inputs.

  The frequency dividing circuit 20 is an inverting circuit 23 that inverts the input signal IN1, a frequency dividing FF (flip-flop) 24 that uses the output of the inverting circuit 23 as a clock input, and a frequency divider that uses the input signal IN1 as a clock input. It has an FF 25 and a protection circuit 22 for noise removal. The protection circuit 22 delays the Q output (Q1) of the FF 24 to delay the Q input (Q2) of the FF 25, the inverting circuit 26 that inverts the Q output (Q2) of the FF 25, and delays the inverted output. And a delay circuit 27 for inputting data to the FF 24.

  The restoration circuit 21 includes an exclusive OR circuit 29 having two outputs, the output Q1 of the FF 24 and the output Q2 of the FF 25, and an inverting circuit 30 that inverts the exclusive OR output and derives it as a restoration signal OUT1. Configured.

  Note that the inverting circuit 23 inverts the negative logic signal IN1 and inputs the inverted signal to the FF 24. Therefore, the FF 24 operates at the falling edge of the negative logic signal IN1. The FF 25 operates by the rising edge of the negative logic signal IN1. The delay circuits 27 and 28 are for extending the time range in which noise can be removed, and when only ringing, which is a kind of noise, is removed, this delay circuit may be omitted. This is because the delay time depends on the performance of PLD and the like, and the delay time plays the same role as the delay circuits 27 and 28. By appropriately setting the delay times by the delay circuits 27 and 28, almost all noise superimposed on the input signal can be removed.

  FIG. 2 shows an operation waveform example of each part of the circuit of FIG. In the figure, when the falling waveform of the signal IN1 is given to the frequency dividing circuit 20, the frequency-divided signal Q1 by the FF 24 has the same value as the protection signal D1 in which the frequency-divided signal Q2 of the FF 25 at that time is inverted and delayed. Works to be. Similarly, when a rising waveform of the signal IN1 is given, the frequency-divided signal Q2 operates so as to have the same value as the protection signal D2 in which the frequency-divided signal Q1 at that time is delayed.

  When the abnormal pulse 35, which is noise, is generated during the low level period of the signal IN1, the frequency of the frequency-divided signal Q2 is not changed by the protection signal D2 obtained by delaying the frequency-divided signal Q1, and noise can be removed. Since the time T1 during which the frequency-divided signal Q1 can be protected from noise depends on the time b during which the frequency-divided signal Q2 is delayed, the time b is delayed so as to approach immediately before the next falling waveform. Since the frequency-divided signal Q1 completely depends on the value of the protection signal D1, noise is completely removed in the range of the protection time T1.

  In addition, when an abnormal pulse 36 that is noise occurs during the high level period of the signal IN1, the frequency-divided signal Q1 is not changed in value by the protection signal D1 obtained by inverting and dividing the frequency-divided signal Q2, and noise is removed. be able to. Since the time T2 during which the frequency-divided signal Q2 can be protected from noise depends on the time a during which the frequency-divided signal Q1 is delayed, this time a is delayed so as to approach immediately before the next rising waveform. Since the frequency-divided signal Q2 completely depends on the value of the protection signal D2, noise is completely removed within the range of the protection time T2.

  The input signal IN1 is output as the frequency-divided signals Q1 and Q2 in a state where noise is removed, and then restored by the restoration circuit 21 and outputted as the restoration signal OUT1.

  More specifically, in FIG. 2, the inverted data of the divided output Q2 of the FF 25 is input to the data input D1 of the FF 24, and the divided output Q1 of the FF 24 is input to the data input D2 of the FF 25. And the output value of FF25 are protected from each other and do not change at the same time. When the FF 24 is operated by the clock input CK1 of the FF 24, even if an abnormal pulse occurs in the input IN1 in the time range until the output of the divided signal Q1 is confirmed and the value of the data input D2 of the FF 25 changes, the data input D1 and D2 do not change. Therefore, the FF 24 and FF 25 can remove the noise of the input IN1.

  That is, the frequency-divided signals Q1 and Q2 are output with noise removed. Further, since the frequency of the frequency-divided signals Q1 and Q2 is half that of the input signal IN1, it is possible to obtain a noise reduction effect on the peripheral pattern and the outside of the apparatus on the circuit board.

  FIG. 3 is a view showing another embodiment of the present invention, and the same parts as those in FIG. 1 are indicated by the same reference numerals. In this example, the basic configuration is the same as in the example of FIG. 1, but the type of signal to be applied is devised. In the example of FIG. 1, the input signal is negative logic, but in this example, the case of positive logic is shown. However, when the present invention is applied to a normal clock signal, there is no distinction between positive logic and negative logic, and the same effect can be obtained by applying any of the circuits in FIGS. .

  In FIG. 3, the positive logic input signal IN <b> 2 is directly applied to the clock input of the FF 24, and is applied to the clock input of the FF 25 via the inverting circuit 23. In the restoration circuit 21, the inverting circuit 30 in FIG. 1 is eliminated, and the output of the exclusive OR circuit 29 is directly used as the restoration signal output OUT2. Also in this circuit, the same effect as the circuit of FIG. 1 is obtained.

  FIG. 4 shows another configuration example of the restoration circuit 21 shown in FIG. 1, and a circuit 61 equivalent to the circuit shown on the upper side (the restoration circuit of FIG. 1) is shown on the lower side. That is, the high level VCC or the low level GND is selected by the multiplexer 62 according to the combination of the levels of the pair of signals Q1 and Q2, and is output to the restoration signal OUT1 (see FIG. 2) having the original frequency. Yes.

  FIG. 5 shows another configuration example of the restoration circuit shown in FIG. 3, and a circuit 61 equivalent to the circuit shown on the upper side (the restoration circuit of FIG. 3) is shown on the lower side. Also in this example, the high level or the low level is selected by the multiplexer 62 according to the combination of the levels of the pair of signals Q1 and Q2, and the restoration signal OUT2 is output.

  6 is a block diagram of a signal transmission system when the frequency dividing circuit 20 and the restoration circuit 21 which are signal waveform conversion circuits of the present invention are applied to the system configuration shown in FIG. Equivalent parts are indicated by the same reference numerals. In FIG. 6, the frequency dividing circuit 20 of FIG. 1 or 3 is mounted in the host PLD1, and the restoration circuit 21 of FIG. 1 or 3 is mounted in each of the plurality of PLDs 2a to 2e connected in parallel. The

  The write enable signal WE is frequency-divided by half by the frequency divider circuit 20 and output in common as a pair of signals Q1 and Q2 having different phases from the host PLD1 to a plurality of slave PLDs 2a to 2e connected in parallel. Then, the common output line branches to each of the PLDs 2a to 2e. Then, in the restoration circuit 21 in each of the PLDs 2a to 2e, these pair of signals Q1 and Q2 are exclusively ORed and restored to the original signal WE. As a result, the number of output pins and the number of signal wirings of the host PLD 1 are remarkably reduced compared to that of FIG. 8, and the signal frequency is also reduced to ½, so that the crosstalk noise is reduced. Noise is prevented by the operation of the protection circuit 22 in the frequency divider circuit 20.

  Referring to FIG. 7, the device 70 is connected to the device 71 by means such as a cable. The device 70 incorporates the frequency dividing circuit 20 that is the signal waveform conversion circuit of the present invention by a PLD or the like. The PLD or the like incorporates the restoration circuit 21 of the present invention.

  As shown in the figure, when data is transmitted from the device 70 to the device 71 using a total of 17 signal lines of 25 MHz data (16 lines) and a 50 MHz signal WE, only the signal WE of 50 MHz is used in the present invention. A pair of signals of 25 MHz is assumed to pass through the frequency divider circuit 20. In this case, the number of signal lines increases by one, but the maximum frequency of the signal passing through the cable is 25 MHz, which is half of 50 MHz.

  In the apparatus 71, the restoration circuit 21 restores a pair of 25 MHz signals and returns them to the original 50 MHz WE signal. The greatest advantage of this example is that the communication frequency can be reduced to half. In other words, the effect of double the transfer speed can be obtained with the same cable specification.

It is a circuit diagram which shows one embodiment of this invention. It is a figure which shows the example of an operation waveform of each part of the circuit of FIG. It is a circuit diagram which shows other embodiment of this invention. FIG. 6 is a diagram for explaining another example of the signal waveform restoration circuit of FIG. 1. FIG. 4 is a diagram for explaining another example of the signal waveform restoration circuit of FIG. 2. It is a figure which shows an example of the system configuration to which this invention is applied. It is a figure which shows the other example of the system configuration to which this invention is applied. It is an example of a system configuration for explaining conventional technology.

Explanation of symbols

20 frequency divider (signal waveform converter)
21 Signal waveform restoration circuit
22 Protection circuit 23, 26, 30 Inversion circuit 24, 25 FF (flip-flop)
27, 28 delay circuit
29 Exclusive OR circuit
62 Multiplexer

Claims (9)

  A signal waveform conversion circuit comprising frequency dividing means that divides an input signal, converts the signal into a pair of signals having different phases, and outputs the signal.   The frequency dividing means includes a first frequency dividing element that performs a frequency dividing operation in response to a rising edge of the input signal, and a second frequency dividing element that performs a frequency dividing operation in response to the falling edge of the input signal. 2. The signal waveform conversion circuit according to claim 1, wherein an output of the first and second frequency dividing elements is output as the pair of signals.   Each of the first and second frequency dividing elements is a flip-flop circuit, and supplies an output of the first frequency dividing element to a data input terminal of the flip-flop circuit of the second frequency dividing element. 3. The signal waveform conversion circuit according to claim 2, wherein the output of the second frequency divider is supplied to the data input terminal of the flip-flop circuit of the first frequency divider.   4. The signal waveform conversion circuit according to claim 3, wherein an output of the frequency dividing element is supplied to a data input terminal of the flip-flop via a delay unit.   A signal waveform restoration circuit that divides a signal to be transmitted and receives and restores a signal converted into a pair of signals having different phases, and a signal having a level corresponding to a combination of levels of the pair of signals And a means for restoring the signal to be transmitted.   6. The signal waveform restoration circuit according to claim 5, wherein the means is an exclusive OR circuit having the pair of signals as inputs.   6. The signal waveform restoration circuit according to claim 5, wherein the means is a multiplexer that selects and outputs a high level or a low level according to a combination of levels of the pair of signals.   A signal transmission system comprising the signal waveform conversion circuit according to any one of claims 1 to 4 on a signal transmission side and the signal waveform restoration circuit according to any one of claims 5 to 7 on a signal reception side. 9. The signal transmission system according to claim 8, wherein a plurality of the signal waveform restoration circuits are connected in parallel.

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