JPH117349A - Noise reducing electronic circuit and integrated circuit for bus wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extremely prevent the generation of ground bounce, cross talk, or radiation noise at the time of data transfer between IC. SOLUTION: In this noise reducing electronic circuit, parallel data transfer is operated by using a bus wiring 4 connected between plural integrated circuits 1 and 2. Parallel data d0-dn to be outputted from the integrated circuit 1 being a data transmitting side are delayed little by little between each data within one period of a clock signal in the integrated circuit. Then, parallel data dd0-ddn including the delay between each data are converted into co-phase data f0-fn by a signal with the same period as the clock signal in the integrating circuit 2 being a data receiving side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit and an integrated circuit for reducing noise in bus wiring.

[0002]

2. Description of the Related Art In recent years, the technology of integrated circuits has advanced, and it has become common for a plurality of integrated circuits such as ICs and LSIs to be mounted on a circuit board such as a printed board. In particular, when a CPU such as a microprocessor unit is used, many ICs managed by the CPU are often provided on the same circuit board.

FIG. 4 is a view showing a state in which a plurality of ICs are mounted on a circuit board. In the figure, on the circuit board 71,
CPU 72 as an IC, memory 73, peripheral IC (# 1)
The figure shows a state in which an IC 74 and a peripheral IC (# 2) 75 are mounted, and each IC is connected by a plurality of address lines 76 and a plurality of data lines 77.

[0004] Each signal line such as an address line 76 and a data line 77 shown in FIG.
The internal signal (data) of the IC is once input to the flip-flop, and the output signal is amplified and output to the conductor constituting each signal line on the circuit board.

FIG. 5 is a diagram showing a configuration example of an output circuit in an IC. As shown in the figure, data and a clock are input to a flip-flop 82 in an IC 81 such as a CPU, and input data is output from the flip-flop 82 at the rising timing of the clock.

The output data is amplified by the output circuit 83 to a level that can be transmitted as a signal on the circuit board 71, and transmitted from the terminal 84 to another IC such as a memory or a peripheral IC.

Here, when the IC is a CPU or an IC connected to the CPU via a bus, the data is transmitted to another IC at the same time in parallel. FIG.
FIG. 2 is a diagram showing a state in which data is transmitted between ICs via a bus.

In FIG. 1, IC (# 1) 91 to IC (# 1)
2) A state in which data transmission is performed in parallel to 92 is shown. That is, a plurality of flip-flops 93a, 93 provided at the output unit of IC (# 1) 91
b,. . . , 93n (hereinafter simply referred to as flip-flop 93).
), Corresponding data a0, a0
1,. . . , An are input, and the transmission-side clock CKa is input to each flip-flop 93. The description of the output circuit is omitted from FIG.

The signals A0, A1,... Output from the IC (# 1) 91 simultaneously from the flip-flops 93 at the rising timing of the clock CKa. . . , An are signal lines 94a, 94b,. . . , 94n via flip-flops 95a, 95b,... In IC (# 2) 92. . . , 95n (hereinafter, also simply referred to as flip-flop 95). Then, the data is transmitted from the flip-flop 95 at the timing of the receiving clock CKb to the data b0, b1,. . . , Bn.

FIG. 7 is a timing chart showing signal states in the circuit shown in FIG. As shown in the figure,
In the IC (# 1) 91, each input data a0, a at the rising timing of the transmission side clock CKa.
1,. . . , An are taken out simultaneously and the signals A0, A
1,. . . , An (see broken line in FIG. 3). On the other hand, in the IC (# 2) 92, the signals A0, A
1,. . . , An are input to the flip-flop 95, and the output data b0, b1,. . . , Bn.

As described above, in a personal computer, a workstation, or a bus for parallel processing of electronic circuits in various other electronic devices, the signal values always operate simultaneously.

[0012]

However, in such an electronic circuit, simultaneous switching in the IC (# 1) 91 is performed for a plurality of parallel wiring buses, so that ground bounce, crosstalk or radiation occurs. There is a problem that noise occurs.

First, there are a power supply, a ground, and a large number of outputs. If signals are sent to a large number of outputs at the same time, the potential of the ground may rise from an ideal potential (zero potential). Such a phenomenon is called ground bounce, and this ground bounce causes a circuit malfunction.

Signals output from the pins (terminals) of the IC on the address bus and data bus are input to another IC or connector through a copper foil pattern on a printed circuit board.
At this time, since a plurality of signal lines are switched at the same timing as described above, a large crosstalk occurs due to a wiring nearby (a wiring in the same layer or a neighboring layer with an insulating layer interposed). Crosstalk is a phenomenon in which a signal is generated from a signal line through which a signal should not originally pass, and is due to the influence of a signal transmitted to another signal line near the signal line. This crosstalk causes malfunction and noise.

Furthermore, when a plurality of wires, that is, bus wires having a long length, which are wired in parallel in this case, are switched in phase, a large radiation noise is emitted. The radiated noise not only causes a malfunction of the electronic circuit, but also has a bad influence on other electronic devices. Considering the influence on electronic devices in airplanes and the garbled data of electronic devices in hospitals, such radiation noise should be reduced as much as possible, and the radiation output of radiation noise is regulated by laws and regulations or standards.

As described above, the occurrence of the ground bounce, the crosstalk or the radiation noise should be prevented as much as possible, but the simultaneous switching has an extremely great advantage that a plurality of data can be transmitted simultaneously by a predetermined synchronization signal. Therefore, at present, an operation method based on simultaneous switching is generally used in data transmission between ICs or the like even though there is some adverse effect due to ground bounce, crosstalk, or radiation noise.

The present invention has been made in view of such circumstances, and a bus wiring capable of minimizing the occurrence of ground bounce, crosstalk, or radiation noise in data transmission between ICs and the like. It is an object of the present invention to provide a noise reduction electronic circuit and an integrated circuit.

[0018]

The gist of the present invention is that, when data transmission between ICs is performed by a bus, the timing of data transmission to each signal line constituting the bus wiring is shifted little by little to achieve ground bounce, An object of the present invention is to minimize the occurrence of crosstalk or radiation noise.

Further, the above-mentioned object can be more specifically achieved by the following means. First, an invention corresponding to claim 1 is an electronic circuit for performing parallel data transmission using a bus wiring connected between a plurality of integrated circuits, wherein the parallel data output from the integrated circuit on the data transmission side is provided. Is delayed little by little between each data within one cycle of the clock signal in the integrated circuit, and in the integrated circuit on the data receiving side, the parallel data including the delay between each data is converted into a signal having the same cycle as the clock signal. Is a noise reduction electronic circuit of the bus wiring which converts the data into the same phase data.

Since the present invention is provided with such means, the transmitted parallel data is slightly delayed, and simultaneous switching when transmitting parallel data and simultaneous signal transmission on the bus are prevented. As a result, occurrence of ground bounce, crosstalk, or radiation noise can be prevented as much as possible.

According to a second aspect of the present invention, there is provided an electronic circuit for performing parallel data transmission using a bus wiring connected between a plurality of integrated circuits, wherein the transmitting integrated circuit serving as the data transmitting side is A plurality of data, each of which is provided corresponding to each data of the parallel data to be transmitted, and which receives the internal signal of the transmitting integrated circuit and outputs the internal signal in accordance with the timing of the input clock signal A capture output means, a reference clock signal is supplied to the first data capture output means as an input clock signal,
A signal obtained by delaying a reference clock signal is supplied as an input clock signal to the next data acquisition / output means,
A signal delayed in sequence from the input clock signal supplied to the previous data capture / output means is supplied to each data capture / output means as an input clock signal to the next data capture / output means, and a reference clock A transmission-side clock supply means for setting a total delay time from a signal within one cycle of the clock signal, wherein the reception-side integrated circuit serving as the data reception side corresponds to each data of the parallel data received from the transmission-side integrated circuit. Are provided, and any of the received parallel data is input, and data corresponding to any of the parallel data is output as an internal signal of the receiving integrated circuit in accordance with the timing of the input clock signal. A plurality of pre-stage data acquisition / output means, and a reference clock signal to the first pre-stage data acquisition / output means; A signal obtained by delaying a reference clock signal is supplied as an input clock signal to the next preceding data acquisition / output means, and the input clock signal is sequentially supplied to the preceding preceding data acquisition / output means. The delayed signal is supplied to each pre-stage data acquisition / output unit as an input clock signal to the next pre-stage data acquisition / output unit, and the timing of each delay is determined by the delay of each input clock signal in the transmission-side clock supply unit. The receiving-side clock supply means and the preceding-stage data acquisition / output means are provided respectively, and the internal signal of the receiving-side integrated circuit output from the preceding-stage data acquisition / output means is input. And a plurality of post-stage data acquisition / output means for outputting the internal signals of the receiving integrated circuit in phase with the timing of the reference clock signal. A noise reduction electronics bus lines with and.

According to the present invention, since such means are provided, the same operation and effect as those of the invention corresponding to claim 1 can be obtained. According to a third aspect of the present invention, there is provided an integrated circuit serving as a data transmission side of an electronic circuit that performs parallel data transmission via a bus wiring, wherein each integrated circuit corresponds to each piece of parallel data to be transmitted. A plurality of data take-in / output means provided and receiving the internal signal, and outputting the internal signal in accordance with the timing of the input clock signal; and a reference clock signal serving as the first data take-in / output means. An input clock signal which is supplied as an input clock signal, a signal obtained by delaying a reference clock signal is supplied as an input clock signal to the next data acquisition / output means, and an input clock signal which is sequentially supplied to the previous data acquisition / output means Is supplied to each data acquisition / output means as an input clock signal to the next data acquisition / output means, and a reference clock An integrated circuit that includes a clock supply unit for the total delay time from the signal within one period of the clock signal.

Since the present invention is provided with such means, it is possible to provide an integrated circuit on the data transmission side used for the electronic circuit according to the first or second aspect of the present invention. Further, an invention corresponding to claim 4 is an integrated circuit that is a data receiving side of an electronic circuit that transmits parallel data delayed little by little via a bus wiring, and corresponds to each data of the received parallel data. A plurality of pre-stage data fetching and outputting means each of which is provided with one of the parallel data input and outputs data corresponding to any of the parallel data as its internal signal in accordance with the timing of the input clock signal And a reference clock signal is supplied as an input clock signal to the first preceding-stage data acquisition / output means, and a signal obtained by delaying the reference clock signal is supplied to the next preceding-stage data acquisition / output means as an input clock signal. A signal delayed from the input clock signal supplied and sequentially supplied to the preceding preceding stage data acquisition / output means is transmitted to the next preceding stage data. Clock supply means for supplying to each preceding data acquisition and output means as an input clock signal to the acquisition and output means, and timing of each delay corresponding to each delay of parallel data; A plurality of internal signals output from the preceding-stage data acquisition / output means are input, and the phases of the internal signals are output in accordance with the timing of a reference clock signal. This is an integrated circuit including a post-stage data acquisition / output unit. Since the present invention is provided with such means, it is possible to provide an integrated circuit on the data receiving side used in the electronic circuit according to the first or second aspect of the present invention.

[0024]

Embodiments of the present invention will be described below. FIG. 1 is a configuration diagram showing an example of a bus line noise reduction electronic circuit according to an embodiment of the present invention.

The noise reduction electronic circuit shown in FIG. 1 is a circuit on a circuit board of an electronic circuit used for a personal computer, a work station, or the like, and includes a plurality of integrated circuits (IC, LSI, etc.) which transmit data by a bus. ).

In FIG. 1, the integrated circuit includes an IC (# 1) 1 on the data transmission side and an IC (# 1) on the data reception side.
Only C (# 2) 2 is shown on the printed circuit board 3.
Each chip of the IC (# 1) 1 and the IC (# 2) 2 has signal lines 4a, 4b,. . . 4n are connected by a bus 4 and data transmission is performed between the two via the bus 4. Note that the signal lines 4a to 4n are parallel wiring.

The IC (# 1) 1 shows only a configuration for data transmission. That is, the flip-flops 5a, 5b, 5c,. . . , 5n (hereinafter, referred to as
A flip-flop 5 is representatively provided, and each output Q of the corresponding signal line 4a, 4b, via an output circuit and a terminal (not shown in FIG. 1) configured in the same manner as in FIG.
4b,. . . 4n.

Also, IC (# 1) 1 and IC (# 2) 2
Clock CK having the same timing as clock CK0 common to
a0 is input to the flip-flop 5a, and this clock CKa0 is supplied to the clock CKa via buffers 6a and 7a.
It becomes 1 and is input to the flip-flop 5b. Although the buffers 6a and 7a are operational amplifiers, they are used here merely for the purpose of delaying the clock signal.

Hereinafter, similarly, each flip-flop 5
c,. . . , 5n to be inputted to the clock CKa
2,. . . , CKan (hereinafter, representatively clock CKa)
) Are buffers 6b and 7b,. . . , 6n and 7n.

Each flip-flop 5 has a corresponding clock CKa and a signal from IC (# 1) 1 to IC (# 2).
Input data a0, a1, a that are data to be transmitted to
2,. . . , An corresponding data is input. The output data d is output from each flip-flop 5 at the rising timing of the corresponding clock CKa.
0, d1, d2,. . . , Dn are the corresponding signal lines 4a, 4b,. . Is output to

On the other hand, only the configuration for data reception is shown in IC (# 2) 2. Although not particularly shown, both the IC (# 1) 1 and the IC (# 2) 2 are provided with both a configuration for transmitting data and a configuration for receiving data.

The IC (# 2) 2 has precedent flip-flops 8a, 8b, 8c,. . . , 8n (hereinafter, also referred to as the preceding flip-flop 8) and the subsequent flip-flops 9a, 9b, 9 for data reception.
c,. . . , 9n (hereinafter, also referred to as a post-stage flip-flop 9).

Further, IC (# 1) 1 and IC (# 2) 2
Clock CK having the same timing as clock CK0 common to
b0 is input to the preceding flip-flop 8a, and this clock CKb0 is input to the preceding flip-flop 8b as the clock CKb1 via the buffers 10a and 11a. The buffers 10a and 11a are operational amplifiers, and are delay means used simply for delaying a clock signal, as in the case of the buffers 6a and 7a. Hereinafter, similarly, each of the preceding-stage flip-flops 8
c,. . . , 8n to be input to the clock CKb
2,. . . , CKbn are buffers 10b and 11
b,. . . , 10n and 11n.

On the other hand, the clock CKc having the same timing as the clock CK0 is supplied to all the subsequent flip-flops 9.
(9a, 9b, 9c,..., 9n).

Data dd0, d transmitted from the IC (# 1) 1 via the bus 4 are stored in each of the preceding flip-flops 8.
d1, dd2,. . . , Ddn are input, and the preceding stage F / F output data e0, e1, e2,. . . , En are output.

The output data e0, e1, e from the preceding flip-flops 8 are stored in the respective subsequent flip-flops 9.
2,. . . , En are input and the final receiving-side output data f0, f at the rising edge of the clock CKc.
1, f2,. . . , Fn.

Next, the operation of the electronic circuit for reducing noise in the bus wiring according to the embodiment of the present invention will be described with reference to FIGS. 2 and 3 are timing charts for explaining the operation of the bus line noise reduction electronic circuit according to the present embodiment.

The timings T1 to T6 in each figure correspond to I
Clock CK common to C (# 1) 1 and IC (# 2) 2
0, that is, the rising timings of the clocks CKa0, CKb0, and CKc are shown in chronological order.

First, as shown in FIG. 2, the IC (# 1) 1
The input data a0 on the transmission side, which is an internal signal of the transmission side, is fetched at the rising edge of the clock CKa0 in the flip-flop 5a and output as transmission-side output data d0 (T
1). In the example shown in the figure, the input data a0 is at the H level (high level) at this timing, so the output data d0 also goes to the H level. Since the level of the output data d0 before that is not known, both H level and L level (low level) are shown in the figure.

The input data a0 is similarly captured by the flip-flop 5a at timings T2, T3, T4, T5, and T6, and output on the bus 4 as data d0.

Next, the input data a1 is the clock CKa
1 is fetched by the flip-flop 5b, and the fetch timings T11, T21,. . . , T61
Is slightly delayed from the timings T1 to T6. This is because the clock CKa1 is stored in the buffer 6
This is because the clock is delayed from the clock CKa0 by a and 7a. Therefore, the transmission side output data d
1 is slightly delayed from the data d0.

This means that the switching timing for outputting the data d0 and the data d1 on the bus 4 is not simultaneous, and there is a slight shift. Also,
The data d0 and d1 transmitted on the signal lines 4a and 4b are not simultaneously parallel. As a result, ground bounce, crosstalk and radiation noise due to the output of the data d0 and d1 are extremely unlikely to occur.

Although the output of the data d0 and d1 has been described above, the following input data a2,. . . , An and corresponding output data d2,. . . , Dn are the same.

That is, as shown in FIG. 2, the clock CKa2 for taking in the data a2 is the clock CKa1.
The data an is further delayed slightly, and then the data an is fetched by the most delayed clock CKan, and output as data dn. Note that the input data a
2,. . . , An are taken in at timings T12 to T62,. . . , T1n to T6n. Note that each of the data d0 to d
In order to capture n in parallel with the same cycle, the interval between the first signal capture timing T1 and the last capture timing T1n needs to be shorter than the clock cycle.

In this manner, the parallel output from the IC (# 1) 1 onto the bus 4 is output as a signal delayed little by little, so that simultaneous switching and simultaneous parallel data transmission can be avoided while performing parallel data transmission. ing.

Next, the capture of the transmission-side output data d0 to dn transmitted on the bus 4 by the IC (# 2) 2 will be described with reference to FIG. In FIG. 3, at timing T1
1 to T61, T12 to T62, T1n to T6n are shown in FIG.
This is the same timing as shown in FIG.

In FIG. 3, data d0 to dn output from the IC (# 1) 1 are first shown, which are delayed during transmission on the bus 4, The signal is input to the IC (# 2) 2 in a state where the signal shape is distorted due to the capacity of the signal line of the bus composed of.

In FIG. 3, this state is represented by the data d0 to dn.
Are represented by data dd0 to ddn as signals slightly delayed from. As described above, the data dd0 to ddn input to the preceding flip-flops 8 of the IC (# 2) 2 are fetched by the clocks CKb0 to CKbn, respectively, and
Output as / F output data e0 to en. Thus, an external input signal is converted into an internal signal in the IC (# 2) 2.

Here, the data dd0, dd1, dd
2,. . . , Ddn are respectively taken at T1 to T6, T11 to T61, and T12 to T6.
2,. . . , T1n to T6n. Each of these timings is gradually delayed from T1 to T6. This is because the buffers 10 and 11 use the capture clock CK.
This is because b1 to CKbn are sequentially delayed, and this situation is the same as the case of the data transmission side described in FIG.

As described above, since the data is fetched in the preceding flip-flop 8 at the timing sequentially delayed with reference to the common clock CK0, the IC (#
1) Accurate data acquisition is possible even if the data dd0 to ddn received from 1 are delayed little by little.

The data dd0 to ddn are data d0
To dn, the preceding stage F / F output data e0 to en is delayed by one clock as compared with the output from the IC (# 1) 1.

Next, as shown in FIG. 3, the front-stage F / F output data e0 to en are input to the respective rear-stage flip-flops 9, and the reception-side output data f0 to fn are extracted at the rising timing of the clock CKc.

Here, the timing of the clock CKc is
This is the same timing as the common clock CK0. Also,
The output data e0 to en are gradually delayed from timing T2 at the same timing as the clock CKb0 (also at the same timing as the common clock CK0) to timing T2n, and the final T2n is the next clock CK.
Since there is no delay until the timing T3 of b0, when this is captured by the clock CKc, it is output as a parallel signal with the same phase at the next timing T3, that is, data f0 to fn shown in FIG. .

Therefore, the data e0 to en, which are quasi-parallel signals delayed little by little, are output as receiving-side output data f0 to fn having a uniform phase with a delay of about one clock cycle, and are output in the IC (# 2) 2. Will be used. Note that the data f0 to fn are delayed by a total of about two clock cycles compared to the data d0 to dn.

As described above, the electronic circuit for reducing noise in the bus wiring according to the embodiment of the present invention has the flip-flop 5 and the buffers 6, 7 provided in the IC (# 1) 1 and the output data d0 to dn. Is output little by little, and the receiving-side IC (# 2) 2 receives the delayed data by the flip-flop 8 and the buffers 10 and 11, and further aligns the phase by the flip-flop 9 to output the IC (# 2). )
2 is used as an internal signal, thereby preventing simultaneous switching when transmitting the parallel data d0 to dn and simultaneous signal transmission on the bus wiring to minimize occurrence of ground bounce, crosstalk, radiation noise, and the like. be able to.

As a result, malfunction of the electronic circuit and generation of noise can be prevented, and adverse effects on other electronic devices due to radiation noise and the like can be prevented. In the integrated circuit on the transmission side used in the noise reduction electronic circuit of the bus wiring according to the embodiment of the present invention, the flip-flop 5 and the buffers 6 and 7 are provided in the IC (# 1) 1 and the output data d0 is provided. To dn are output with a little delay, so that an integrated circuit for realizing the electronic circuit for reducing the noise of the bus wiring can be provided.

Further, the integrated circuit on the receiving side used in the noise reduction electronic circuit of the bus wiring according to the embodiment of the present invention uses the flip-flop 8 and the buffers 10 and 11 in the IC (# 2) 2 on the receiving side. Since the delay data is received, and the phase is further adjusted by the flip-flop 9 and used as an internal signal of the IC (# 2) 2, an integrated circuit for realizing the noise reduction electronic circuit of the bus wiring is provided. be able to. It should be noted that the present invention is not limited to the above-described embodiment, and can be variously modified without departing from the gist thereof.

[0058]

As described above in detail, according to the present invention, parallel data transmitted through the bus wiring is output with a little delay, so that ground bounce and crosstalk in data transmission between ICs and the like are achieved. Alternatively, it is possible to provide a bus line noise reduction electronic circuit and an integrated circuit that can minimize generation of radiation noise.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an example of a bus line noise reduction electronic circuit according to an embodiment of the present invention.

FIG. 2 is an exemplary timing chart for explaining the operation on the transmission side of the noise reduction electronic circuit of the bus wiring according to the embodiment;

FIG. 3 is a timing chart mainly explaining the operation of the receiving side of the noise reduction electronic circuit of the bus wiring according to the embodiment;

FIG. 4 is a diagram showing a state in which a plurality of ICs are mounted on a circuit board.

FIG. 5 is a diagram showing a configuration example of an output circuit in an IC.

FIG. 6 is a diagram showing how data is transmitted between ICs via a bus.

FIG. 7 is a timing chart showing signal states in the circuit shown in FIG. 6;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... IC (# 1) 2 ... IC (# 2) 3 ... Printed circuit board 4 ... Bus 4a-4n ... Each signal line of a bus 5,5a-5n ... Flip-flop 6,6a-6n, 7,7a-7n ... Buffers 8, 8a to 8n: front-stage flip-flops 9, 9, 9a to 9n: rear-stage flip-flops 10, 10a to 10n, 11, 11a to 11n: buffers a0 to an: transmission-side input data d0 to dn: transmission-side output data dd0 ddn: receiving side input data e0 to en: previous stage F / F output data f0 to fn: receiving side output data CK0, CKa0 to CKan, CKb0 to CKbn, C
Kc: Clock

Claims (4)

[Claims] An electronic circuit for performing parallel data transmission using a bus wiring connected between a plurality of integrated circuits, wherein parallel data output from an integrated circuit on a data transmission side is transferred to the internal circuit. In one cycle of the clock signal, each data is delayed little by little. In the integrated circuit on the data receiving side, the parallel data including the delay between the data is in phase with a signal having the same cycle as the clock signal. An electronic circuit for reducing noise in a bus line, wherein the electronic circuit converts the data into data of the same type. 2. An electronic circuit for performing parallel data transmission by using a bus wiring connected between a plurality of integrated circuits, wherein a transmission-side integrated circuit serving as a data transmission side includes respective data of parallel data to be transmitted. And a plurality of data fetching and outputting means for receiving the internal signal of the transmitting integrated circuit and outputting the internal signal in accordance with the timing of the input clock signal. A clock signal is supplied to the first data acquisition / output means as the input clock signal, and a signal obtained by delaying the reference clock signal is supplied to the next data acquisition / output means as the input clock signal. A signal delayed from the input clock signal supplied to the previous data acquisition / output means is used as an input clock signal to the next data acquisition / output means. And a transmission-side clock supply means for supplying a total delay time from the reference clock signal within one cycle of the clock signal, and a reception-side integrated circuit serving as a data reception side, Each of the parallel data received from the transmitting side integrated circuit is provided corresponding to each data, and any one of the received parallel data is input, and any one of the parallel data is synchronized with the timing of the input clock signal. A plurality of pre-stage data fetching and outputting means for outputting data corresponding to the data as an internal signal of the receiving side integrated circuit; and supplying a reference clock signal to the first pre-stage data fetching and outputting means as the input clock signal; A signal obtained by delaying the reference clock signal is supplied to the next preceding stage data acquisition / output means. Supplied as,
A signal delayed from the input clock signal supplied to the preceding pre-stage data acquisition and output means is sequentially supplied to each pre-stage data acquisition and output means as an input clock signal to the next pre-stage data acquisition and output means. The delay timing is provided corresponding to the delay of each input clock signal in the transmission clock supply means, the reception clock supply means, and each of the preceding stage data acquisition and output means, and A plurality of internal signals of the receiving-side integrated circuit output from the preceding-stage data fetching / outputting means are input and the phases of the internal signals of the receiving-side integrated circuit are output in accordance with the timing of the reference clock signal. A noise reduction electronic circuit for a bus wiring, comprising: 3. An integrated circuit on the data transmission side of an electronic circuit that performs parallel data transmission via a bus wiring, wherein an integrated circuit is provided corresponding to each data of the parallel data to be transmitted. A plurality of data acquisition / output means for receiving the internal signal and outputting the internal signal in accordance with the timing of the input clock signal; and a reference clock signal as the input clock signal to the first data acquisition / output means. And a signal obtained by delaying the reference clock signal is supplied as the input clock signal to the next data capture / output means, and the signal is sequentially delayed from the input clock signal supplied to the previous data capture / output means. The supplied signal is supplied to each data acquisition / output means as an input clock signal to the next data acquisition / output means, and the reference clock signal is supplied to each data acquisition / output means. Integrated circuit comprising the total delay time from click signal and a clock supply means to within one cycle of the clock signal. 4. An integrated circuit as a data receiving side of an electronic circuit for transmitting parallel data delayed little by little via a bus wiring, wherein the integrated circuit is provided corresponding to each data of the received parallel data, A plurality of pre-stage data input / output means for receiving any one of the parallel data and outputting data corresponding to any of the parallel data as an internal signal in accordance with the timing of an input clock signal; Is supplied as the input clock signal to the first pre-stage data fetch / output unit, and a signal obtained by delaying the reference clock signal is supplied to the next pre-stage data fetch / output unit as the input clock signal. Supply,
A signal delayed from the input clock signal supplied to the preceding pre-stage data acquisition and output means is sequentially supplied to each pre-stage data acquisition and output means as an input clock signal to the next pre-stage data acquisition and output means. The delay timing is provided corresponding to each of the delays of the parallel data, and a clock supply unit is provided corresponding to each of the preceding stage data fetching / outputting units. An integrated circuit, comprising: a plurality of post-stage data acquisition / output means for receiving the internal signal and outputting the internal signal in phase with the timing of the reference clock signal.