CN108694146B - Asynchronous/synchronous interface circuit - Google Patents
Asynchronous/synchronous interface circuit Download PDFInfo
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- CN108694146B CN108694146B CN201710231653.4A CN201710231653A CN108694146B CN 108694146 B CN108694146 B CN 108694146B CN 201710231653 A CN201710231653 A CN 201710231653A CN 108694146 B CN108694146 B CN 108694146B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
Abstract
An interface circuit 30 for connecting an asynchronous processor 10 to a synchronous peripheral 20 is disclosed. Class 3 asynchronous/synchronous interface circuits are provided that are suitable for dataless lanes, push lanes, and pull lanes, respectively. Before use in a synchronous environment, asynchronous request signals or data signals need to be processed synchronously, and buffer units or delay units are embedded to satisfy a 4-phase binding data handshake protocol based on a request-acknowledge mechanism. The present invention can be applied to various electronic devices.
Description
Technical Field
The present invention relates to digital circuits, and more particularly, to an interface circuit between an asynchronous circuit and a synchronous circuit.
Background
Generally, digital circuits are designed synchronously with a global clock, and even different modules may use frequency division and/or frequency multiplication of the global clock. Digital circuits employing such synchronous clocking have numerous advantages, particularly in the design and application of the circuits. However, if the global clock cannot be finely gated, a large amount of power consumption will be consumed.
In recent years, due to the demands of high security and low power consumption in many fields, asynchronous circuits have been gaining more and more attention. Compared with a synchronous circuit, the asynchronous circuit has the following advantages: the circuit has the advantages of low power consumption, high performance, elimination of a large amount of clock wiring and clock skew, high adaptability to process and environment changes, less electromagnetic noise radiation, better compatibility, modularization and the like.
Asynchronous circuits consume only static power if there is no data exchange between the two stages of the circuit. However, since the global clock having a fixed clock period is eliminated, it is difficult to implement a divider or a timer having a fixed delay using a design method of an asynchronous circuit. Therefore, if a frequency divider or a timer is included in the circuit, a circuit structure in which an asynchronous circuit is combined with a synchronous circuit is required. The present invention uses an asynchronous/synchronous interface circuit to control the communication of an asynchronous circuit and a synchronous circuit. A "handshake interface" of different circuit interfaces is described in U.S. Pat. No.0,164,929 (U.S. patent No.0,164,929).
To couple asynchronous circuit blocks into a globally synchronous circuitry, U.S. Pat. No.7,395,450 (U.S. patent No.7,395,450) discloses an asynchronous/synchronous interface circuit and electronic device that uses a Finite State Machine (FSM) to control communications between the synchronous bus and the asynchronous CPU in an event-driven manner, and a detection circuit to detect the opening of communications with each other.
In addition to using FSM schemes, another patent, U.S. Pat. appl.no.2007/0,277,053 (U.S. patent application No.2007/0,277,053), uses a blocking or non-blocking interface circuit for communication between asynchronous and synchronous sub-circuits. The data generated by the circuit needs to wait until it has been received before further operation, at which point the blocking interface is used. Once the data generated by a sub-circuit is registered by another sub-circuit, the next operation is performed without waiting for another sub-circuit, and the non-blocking interface is used.
Int.pat.pub.no.2006/056904 (international patent application publication No. 2006/056904) describes a globally asynchronous locally synchronous system in which an additional, suspendable clock, one or more input/output controllers are wrapped around each locally synchronous module, and an interface circuit between the first and second modules with a buffer array, such that a synchronized interface is provided between a central unit with non-tunable clock circuitry and a plurality of peripheral units with suspendable clocks. Between asynchronous modules, data is transferred using latches and registers controlled by an input/output controller or FSM, respectively.
Disclosure of Invention
However, these patents are relatively complex to implement and consume a large amount of power consumption. Based on low power consumption requirements and/or other considerations, the present invention seeks to provide a simple implementation of an interface circuit between an asynchronous processor and its synchronous peripherals, and accordingly a hybrid electronic device.
In an asynchronous/synchronous hybrid system, in addition to the initial request-acknowledge based handshaking, typically the first handshake (request) signal issued by the asynchronous environment needs to wait for a response (acknowledge) signal provided by the synchronous environment, while asynchronous/synchronous communication is accompanied by the transfer of data.
In 9 months 2001, three basic asynchronous channel types, namely no data channel, push channel and pull channel, were described in the book asynchronous circuit design principles-system perspective, edited by JENS and STEVEFURBER and published by kronell press.
The invention provides an asynchronous/synchronous interface circuit for connecting an asynchronous processor (10) to a synchronous peripheral (21, 22, 23), comprising:
at least one data channel-less asynchronous/synchronous interface circuit (31) connecting the asynchronous processor (10) to the synchronous peripheral (21), wherein the asynchronous processor (10) issues a request signal as an enable to the synchronous peripheral (21);
at least one push channel asynchronous/synchronous interface circuit (32) connecting the asynchronous processor (10) to the synchronous peripheral (22), wherein the asynchronous processor (10) initiates data communication;
at least one pull-channel asynchronous/synchronous interface circuit (33) connecting the asynchronous processor (10) to the synchronous peripheral (23), wherein the synchronous peripheral (23) initiates data communication.
Optionally, the datapath-less asynchronous/synchronous interface circuit (31) comprises a synchronizer (310) and a combining circuit (311), the synchronizer (310) passing a request signal (410) issued by the asynchronous processor (10) to the synchronous peripheral (21), the combining circuit (311) passing a reply signal (411) to the asynchronous processor (10).
Optionally, the synchronizer (310) comprises a plurality of flip-flops connected in series, the flip-flops are controlled by a local clock signal (511) issued by the synchronization peripheral (21), and the combination circuit (311) comprises an and gate.
Optionally, the push channel interface circuit (32) comprises a combination circuit (320) and a synchronizer (321), wherein the combination circuit (320) implements a delay function, and the synchronizer (321) transfers the asynchronous data signal (422) sent by the asynchronous processor (10) to the synchronous peripheral (22).
Optionally, the combination circuit (320) is a buffer, the response signal (431) is sent to the asynchronous processor (10) after the combination circuit (320) buffers the request signal (421), and the synchronizer (321) comprises a plurality of serially connected flip-flops controlled by a local clock signal (521) from the synchronous peripheral (22).
Optionally, the pull channel interface circuit (33) comprises a combination circuit (330), and in the combination circuit (330), the request signal (430) output by the asynchronous processor (10) and the selection signal (530) and the data ready signal (531) output by the synchronous peripheral (23) cooperate to generate a response signal (431) to be output to the asynchronous processor (10).
Optionally, wherein the combining circuit (330) comprises a buffer, an inverter, a Delay Element (DEL), a nor gate and a selector, the asynchronous processor (10) sends the request signal (430) to the 0 terminal of the selector.
Optionally, wherein the data signal (532) generated by the synchronous peripheral (23) is passed directly through the interface circuit (33) as a data input signal to the asynchronous processor (10).
Optionally, in the data channel-less asynchronous/synchronous interface circuit (31), the acknowledge signal (411) is generated by an and operation of its corresponding request signal (410) and a completion signal (512) of the synchronous peripheral (21).
Alternatively, where in the push channel asynchronous/synchronous interface circuit (32) the data signals need to be synchronized before they can be used in the synchronous peripheral (22), the reply signal can be generated simply by buffering the corresponding request signal.
Alternatively, where in the pull channel asynchronous/synchronous interface circuit (33) the data signal 532 of the pull channel can be used directly by the asynchronous processor, validity is ensured by buffering the corresponding request signal (430) or by a reply signal (431) generated by negating the inverse (334) of the valid signal (531) and the delayed (333) of the valid signal (531).
The invention also extends to a system-on-chip or network-on-chip device comprising an asynchronous/synchronous interface circuit as described in any one of the above.
The asynchronous/synchronous interface circuit of the invention can be adapted to dataless channels for synchronization purposes, in which case the request signal is often used as an enable signal for the synchronous context, while the reply signal is generated by an AND operation of the corresponding request signal AND a completion signal for the synchronous context.
Therein, the asynchronous/synchronous interface circuit of the invention can be adapted to either push channels or pull channels, in which case the asynchronous environment or the synchronous environment respectively initiates the communication of data. For push channels, the data signals need to be synchronized before the data is used in the synchronization circuit, and the reply signal can simply be buffered with its corresponding request signal. On the other hand, an asynchronous processor can directly use the data signal of the pull channel, while its validity will be guaranteed by the reply signal, which is obtained by buffering its corresponding request signal or by the valid signal generated by the synchronous environment and its delay signal NOR.
Drawings
For a better understanding of the invention, reference will now be made to specific exemplary embodiments thereof based on the following drawings. It should be noted, however, that the present invention is applicable to all equivalent embodiments and is not limited by the following drawings.
FIG. 1 is a hybrid circuit architecture of an asynchronous processor, synchronous peripheral circuits and their interface circuits;
FIG. 2 is a block diagram of an implementation of an asynchronous/synchronous interface circuit for a data channel-less system according to an embodiment of the present invention;
FIG. 3 is an implementation of an asynchronous/synchronous interface circuit for a push channel according to an embodiment of the present invention;
FIG. 4 is an implementation of an asynchronous/synchronous interface circuit for a pull channel according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating the operation of the asynchronous/synchronous interface circuit of FIG. 4 according to one embodiment of the present invention.
Detailed Description
Embodiments of the invention are described in detail below. These examples provide a complete and complete embodiment, and are intended to fully convey the scope of the invention. It is to be understood that any embodiment of the invention herein may be embodied by one or more components of a claim.
"example" as used herein means "an example, instance, or illustration," and any embodiment described herein as "an example" is not necessarily to be construed as preferred or advantageous over other embodiments.
The invention relates to the field of interfaces between different types of circuits, and in particular to the field of asynchronous/synchronous hybrid circuits. The method can be used in the scene that the asynchronism is main and the synchronization is auxiliary. For example, if there is a timer or divider in the asynchronous host processor, because the asynchronous circuit rejects the global clock, the timer or divider needs to be implemented using a synchronous approach, and accordingly an asynchronous/synchronous interface is required.
Fig. 1 is a general architecture of asynchronous/synchronous communications, including an asynchronous processor 10, synchronous peripherals 20, and interface circuits 30, according to an embodiment of the present invention. The asynchronous circuit 10 is a main data processor and the synchronous peripheral 20 may be a functional block or an analog front-end circuit or an multi-time programmable memory, and an asynchronous/synchronous interface circuit 30 is coupled between the asynchronous circuit 10 and the synchronous circuit 20.
Typically, multiple clock domains and multiple data communication schemes are used for the synchronous peripherals, so 3 different asynchronous/ synchronous interface circuits 31, 32 and 33 are embedded between the asynchronous processor 10 and the synchronous peripherals 21, 22 and 23, respectively. Although 3 synchronous peripherals are listed here, it should be understood that any number of peripherals greater than 3 or less than 3 may be included in an electronic device or application.
In operation, the asynchronous circuit 10 controls the main data processing. A request signal is sent from the asynchronous environment 10 indicating the start of its communication with the peripheral device and an acknowledge signal is received from the synchronous environment 20 indicating the end of the asynchronous/synchronous handshake, possibly accompanied by a transfer of data.
Fig. 2 shows an embodiment of a datapath-free asynchronous/synchronous interface circuit. The interface circuit 31 comprises a synchronizer 310 and a combining circuit 311. The request signals sent from the asynchronous environment are typically enabled for synchronous operation, and the communication between the asynchronous processor 10 and the synchronous peripheral 21 is asynchronous, thus requiring the use of synchronous techniques in the interface for metastability-free communication between them.
An exemplary level synchronizer 310 can generally be implemented with two flip-flops in series, as shown in fig. 2. The two-stage synchronizer is controlled by a local clock signal 511 from the synchronous peripheral 21. the asynchronous request signal 410 sent to the first flip-flop can be converted after the two-stage synchronizer into a synchronous request signal 510 generated by the second flip-flop.
A counter or timer is preset in response to the synchronized request signal 510 and the completion signal 512 is generated after a specified delay. The reply signal 411 is generated by an AND operation of its corresponding request signal 410 AND a completion signal 512 of the synchronization operation, as indicated by block 311 of FIG. 2.
It should be noted that synchronizers implemented with multiple stages of cascaded flip-flops or complex first-in-first-out (FIFO) buffers may be used in high speed multi-clock domain systems to ensure metastability-free communication, but the synchronization request signal 410 will not stabilize until its corresponding reply signal 411 is available, so the two-stage synchronizer herein is able to effectively synchronize the request signal 410.
FIG. 3 illustrates an exemplary embodiment of a push channel asynchronous/synchronous interface circuit. The interface circuit 32 includes a combining circuit 320 and a synchronizer 321. The combination circuit 320 implements only a delay function, with the reply signal 421 being buffered by its corresponding request signal 420, thereby simply satisfying the 4-phase bundled data handshake protocol. The asynchronous processor 10 is the master initiating the push channel data transfer and the synchronizer 321 can typically be implemented using two flip-flops in series as shown in fig. 3. The two-stage synchronizer is controlled by a local clock signal 521 from the synchronous peripheral 22. the asynchronous data signal 422 sent to the first flip-flop can be converted into a synchronous data signal 520 generated by the second flip-flop after the two-stage synchronizer.
FIG. 4 illustrates an exemplary embodiment of an asynchronous/synchronous interface circuit for a pull channel. The interface circuit 33 includes a combining circuit 330. It is noted that the data signal 532 generated by the synchronous peripheral 23 passes directly through the interface circuit 33 as the data input signal 432 to the asynchronous processor 10. There are two branches to generate received signal 431 in response to select signal 530 output by sync peripheral 23. One branch has only one buffer after one selector (upper branch) and the other branch (lower branch) comprises a delay unit, an inverter in parallel with the delay unit, a nor gate, a selector and a buffer.
In the combination circuit 330, the request signal 430 and the signal 530/531 (after cooperation) output by the synchronization peripheral 23 generate the response signal 431. The combining circuit 330 will be further explained below.
Fig. 5 shows a timing diagram of an exemplary operational scenario of asynchronous/synchronous interface circuit 330 of fig. 4, the following description providing a request-acknowledge handshake based timing illustration of combinatorial circuit 330 between asynchronous processor 10 and synchronous peripheral 23.
Assuming that all gates of block 330 of FIG. 4, except for the DEL cell, have a standard delay, select signal 530 is initialized low at t0, which corresponds to the operation of the upper branch. At t1, high request signal 430 is effectively received from the preceding asynchronous processor 10. Thereafter, at t2, the output 331 of the selector goes high after a standard delay, thus causing a high acknowledge signal 431 to be output from the buffer at time t3 after a standard delay. The low-to-high transition of the reply signal 431 causes the request signal 430 to go low at time t4 after 2 standard delays (t4-t 3). Resulting in high-to-low transitions of signal 331 and reply signal 431 at times t5 and t6, respectively. So far, a complete 4-phase binding data handshake protocol is completed.
When the select signal 530 goes high at t7, this corresponds to the operation of the next branch. At t8, the low-to-high transition of request signal 430 turns on data communication. Data ready signal 531 goes high at t9 and remains 8 standard delays. Since the data ready signal 531 goes high, at t10, the output signal 334 of the inverter goes low after a standard delay and holds 8 standard delays accordingly. In the other branch, the output signal 333 of the DEL unit goes high at t11 after five standard delays of the delayed data ready signal 531. As a result, after the nor gate is operated, a pulse of 4 standard delay widths is generated and delayed by one standard delay. In the case where the select signal is low, as described above, signal 331 and reply signal 431 are each delayed by a standard delay after the selector and buffer, respectively. As soon as acknowledge signal 431 goes high, its request signal 430 goes low at t 12. Therefore, acknowledge signal 431 goes low at t13, completing a complete 4-phase bundled data handshake protocol.
Note that the function of the buffer in fig. 4 is simply to delay to satisfy the 4-phase bundled data handshake protocol of the upper branch and to boost the driving capability of the lower branch for the following asynchronous processor.
Along with the request-acknowledge based 4-phase bundled data handshake protocol described above, the data signals 532 generated by the synchronous peripheral 23 pass directly through the interface circuit 33 as data input signals to the asynchronous processor 10.
The invention has been illustrated and described in detail in the drawings and foregoing description, the illustration and description are to be considered illustrative or exemplary and not restrictive. The scope of protection of the invention is not limited to the embodiments shown. Neither is the scope of protection of the invention restricted by the reference numerals of the claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" preceding an element does not exclude a plurality of those elements.
Also, if the asynchronous processor 10 has been designed and required to be multiplexed as IP in a certain scenario, connection design and verification can be achieved in an extremely short period of time by employing the asynchronous/synchronous interface 30 according to the present embodiment.
While specific implementations of the invention have been described, it will be appreciated that the invention is not limited to these implementations. It can be applied to various electronic devices such as smart cards and radio frequency identification, and can be used for various applications such as system on chip or network on chip products.
Claims (12)
1. Asynchronous/synchronous interface circuitry for connecting an asynchronous processor (10) to a first synchronous peripheral (21), a second synchronous peripheral (22), a third synchronous peripheral (23), comprising at least one of a dataless channel asynchronous/synchronous interface circuitry (31), a push channel asynchronous/synchronous interface circuitry (32), and a pull channel asynchronous/synchronous interface circuitry (33), wherein:
a datapath-free asynchronous/synchronous interface circuit (31) that connects the asynchronous processor (10) to the first synchronous peripheral (21), wherein the asynchronous processor (10) issues a request signal as an enable to the first synchronous peripheral (21);
a push channel asynchronous/synchronous interface circuit (32) connecting the asynchronous processor (10) to the second synchronous peripheral (22), wherein the asynchronous processor (10) initiates data communication;
a pull channel asynchronous/synchronous interface circuit (33) connecting the asynchronous processor (10) to a third synchronous peripheral (23), wherein the third synchronous peripheral (23) initiates data communication.
2. Asynchronous/synchronous interface circuit according to claim 1, wherein the datapath-less asynchronous/synchronous interface circuit (31) comprises a first synchronizer (310) and a first combining circuit (311), the first synchronizer (310) passing a first request signal (410) issued by the asynchronous processor (10) to the first synchronization peripheral (21), the first combining circuit (311) passing a first acknowledgement signal (411) to the asynchronous processor (10).
3. Asynchronous/synchronous interface circuit according to claim 2, wherein the first synchronizer (310) comprises a plurality of flip-flops connected in series, the flip-flops being controlled by a first local clock signal (511) issued by the first synchronization periphery (21), the first combination circuit (311) comprising an and gate.
4. Asynchronous/synchronous interface circuit according to claim 1, wherein the push channel interface circuit (32) comprises a second combinatorial circuit (320) and a second synchronizer (321), wherein the second combinatorial circuit (320) implements a delay function, and wherein the second synchronizer (321) passes the asynchronous data signal (422) issued by the asynchronous processor (10) to the second synchronous peripheral (22).
5. Asynchronous/synchronous interface circuit according to claim 4, wherein the second combination circuit (320) is a buffer, the second combination circuit (320) buffering the second request signal (421) and sending a second reply signal (431) to the asynchronous processor (10), the second synchronizer (321) comprising a plurality of serially connected flip-flops controlled by a second local clock signal (521) issued by the second synchronous peripheral (22).
6. Asynchronous/synchronous interface circuit as claimed in claim 1, wherein the pull channel interface circuit (33) comprises a third combination circuit (330), in which third combination circuit (330) a third request signal (430) output by the asynchronous processor (10) and a selection signal (530) and a data ready signal (531) output by the third synchronous peripheral (23) co-act to generate a response signal output to the asynchronous processor (10).
7. The asynchronous/synchronous interface circuit of claim 6, wherein the third combinatorial circuit (330) comprises a buffer, an inverter, a Delay Element (DEL), a nor gate and a selector, the asynchronous processor (10) sending the third request signal (430) to the 0 terminal of the selector.
8. Asynchronous/synchronous interface circuit as claimed in claim 6, wherein the data signal (532) generated by the third synchronous peripheral (23) is passed directly through the interface circuit (33) as a data input signal for the asynchronous processor (10).
9. Asynchronous/synchronous interface circuit as claimed in claim 1 or 2, wherein in the datapath-less asynchronous/synchronous interface circuit (31) the first reply signal (411) is generated by an and operation of its corresponding first request signal (410) and a completion signal (512) of the first synchronous peripheral (21).
10. Asynchronous/synchronous interface circuit as claimed in claim 1 or 4, wherein in the push channel asynchronous/synchronous interface circuit (32) the data signal needs to be synchronized before it can be used in the second synchronous peripheral (22), the reply signal being able to be generated simply by buffering the corresponding request signal.
11. Asynchronous/synchronous interface circuit as claimed in claim 1 or 6, wherein in the pull channel asynchronous/synchronous interface circuit (33) the data signal (532) of the pull channel can be used directly by the asynchronous processor to guarantee validity by buffering the corresponding third request signal (430) or by a second reply signal (431) generated by negating the inverse (334) of the valid signal (531) and the delayed (333) signal of the valid signal (531).
12. A system-on-chip or network-on-chip device comprising an asynchronous/synchronous interface circuit as claimed in any one of claims 1 to 11.
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| CN111158923B (en) * | 2019-12-30 | 2023-05-12 | 深圳云天励飞技术有限公司 | Interface calling method and device, electronic equipment and storage medium |
| CN112929431B (en) * | 2021-02-01 | 2022-12-20 | 深圳市科漫达智能管理科技有限公司 | Message synchronous and asynchronous response conversion method and device based on micro-service framework |
| CN113190291B (en) * | 2021-05-25 | 2023-06-02 | 电子科技大学 | Configurable protocol conversion system and method based on network-on-chip data acquisition |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1514968A (en) * | 2001-02-27 | 2004-07-21 | �Ҵ���˾ | Synchronous to asynchronous to synchronous interface |
| CN1947109A (en) * | 2004-04-28 | 2007-04-11 | 皇家飞利浦电子股份有限公司 | Circuit with asynchronous/synchronous interface |
| CN102486761A (en) * | 2010-12-06 | 2012-06-06 | 中国航空工业集团公司第六三一研究所 | Conversion method of synchronous interface and asynchronous interface |
| CN105355229A (en) * | 2015-10-29 | 2016-02-24 | 同济大学 | Write circuit and read circuit of asynchronous circuit system for synchronous random-access memory |
| US9514066B1 (en) * | 2015-09-09 | 2016-12-06 | Motorola Solutions, Inc. | Reconfigurable interface and method of configuring a reconfigurable interface |
-
2017
- 2017-04-11 CN CN201710231653.4A patent/CN108694146B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1514968A (en) * | 2001-02-27 | 2004-07-21 | �Ҵ���˾ | Synchronous to asynchronous to synchronous interface |
| CN1947109A (en) * | 2004-04-28 | 2007-04-11 | 皇家飞利浦电子股份有限公司 | Circuit with asynchronous/synchronous interface |
| CN100461147C (en) * | 2004-04-28 | 2009-02-11 | 皇家飞利浦电子股份有限公司 | Circuit with asynchronous/synchronous interface |
| CN102486761A (en) * | 2010-12-06 | 2012-06-06 | 中国航空工业集团公司第六三一研究所 | Conversion method of synchronous interface and asynchronous interface |
| US9514066B1 (en) * | 2015-09-09 | 2016-12-06 | Motorola Solutions, Inc. | Reconfigurable interface and method of configuring a reconfigurable interface |
| CN105355229A (en) * | 2015-10-29 | 2016-02-24 | 同济大学 | Write circuit and read circuit of asynchronous circuit system for synchronous random-access memory |
Non-Patent Citations (2)
| Title |
|---|
| 同步异步通信转换的CPLD／FPGA设计;田小芳等;《微型电脑应用》;20051231;第21卷(第10期);全文 * |
| 基于FPGA的全局异步局部同步四相单轨握手协议实现;张景伟等;《电子技术应用》;20121231;第38卷(第4期);全文 * |
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