KR100376319B1 - Apparatus for scrambling for 4 channel STM-1 and 1 channel STM-4 - Google Patents

Abstract

The present invention is to provide a scrambling device that can be used as a four-channel STM-1 and one channel STM-4, the present invention is an STM-1 pattern forming unit for forming a four-channel STM-1 pattern and ; An STM-4 pattern forming unit forming an STM-4 pattern of one channel; A selection unit which receives the scrambling patterns of the STM-1 and STM-4 pattern forming units and selects and outputs one pattern according to a transmission mode; A negative logic element that outputs scrambled data by performing a negative logic sum operation on the scrambling pattern selected by the selector and the parallel data inputted, and thus, a 4-channel STM-1 signal and a 1-channel STM signal among the tributary signals of the 2.5G SDH system. The scrambling of the -4 signal is enabled so that the corresponding ASIC can be used in both STM-1 / STM-4 units.

Description

Apparatus for scrambling for 4 channel STM-1 and 1 channel STM-4}

The present invention relates to a 2.5G SDH (Synchronous Digital Hierarchy) system, and in particular, a four-channel STM-1 (Synchronous Transport Module level 1, synchronous transport) in a tributary signal (Tributary Signal) of the 2.5G SDH system Module 1) Enables scrambling of the signal and one-channel Synchronous Transport Module level 4 (STM-4) signal, so that the applicable specific integrated circuit (ASIC) allows the STM-1 / STM-4 unit to It relates to a four-channel STM-1 and a one-channel STM-4 dual scrambling device suitable for use in both.

SDH-based transmission is a method of transmitting a 53-byte ATM (Asynchronous Transfer Mode) cell in a frame of a synchronous transmission system. For example, a SONET (Synchronous Optical Network) is transmitted to a transmission system. It is to use. In SDH-based transmission, STM-1 has a transmission rate of 155.52 Mbps and STM-4 has a transmission rate of 622.08 Mbps.

In general, for STM-1 / 4 of one channel, each scrambler can be implemented as follows by referring to the Recommendation of 6.5 Scrambled Item of G.707 of International Telecommunications Union, Telecommunication Sector (ITU-T). Can be.

That is, STM-N (N = 1, 4, 16, 64) signals should have an appropriate bit pattern of "1" or "0" using a scrambler in the NNI (Network Network Interface). The scrambler sequence is repeated 127 patterns. This pattern generates a scrambled data pattern by performing a negative logic operation on the input data. The resulting polynomial is "1 + X ⁶ + X ⁷ ".

1 is a block diagram of a conventional scrambling apparatus of STM-1 / 4 of one channel.

As shown therein, the first to seventh flip-flops (1 to 7) for delaying and outputting the input clock according to the frame pulse; A first negative logic element 8 for performing a negative logic sum operation on the outputs of the sixth flip-flop 6 and the seventh flip-flop 7, and inputting the output to the first flip-flop 1 to output a scrambling pattern. )Wow; The scrambling pattern output from the seventh flip-flop 7 and the second negative logic element 9 output the scrambled data by performing a negative logic sum operation on the input data.

The operation of the conventional apparatus configured as described above is as follows.

First, 127 sequences created in the scrambler are listed.

11111110 00000100 00011000 01010001 11100100 01011001 11010100 11111010

00011100 01001001 10110101 10111101 10001101 00101110 11100110 0101010

This 127 sequence repeats the same sequence until the scrambler is initialized. A scrambled data is generated by performing a negative logic sum operation on the input data and the second negative logic element 9 using the data pattern of the 127 sequence. The bit rate of the data is determined according to the processing capacity of the signal. In general, data processing is performed serially.

FIG. 2 is a block diagram illustrating the scrambling example of FIG. 1.

Therefore, the scrambler 127 sequence is sequentially negated on the serial data input "d1 / d2 / d3 / d4 / d5 / ……", and the scrambled data output "d1 ?? 1 / d2 ?? 1 / d3?" ? 1 / …… / d7 ?? 1 / d8 ?? 0 / d9 ?? 0 / d10 ?? 0 / …… ”are generated sequentially.

However, the conventional technology has a disadvantage in that the size of hardware increases, power consumption and heat problems occur because the data is processed serially, and the STM-1 and STM-4 cannot be used in combination.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is to provide scrambling of a 4-channel STM-1 signal and a 1-channel STM-4 signal among the tributary signals of a 2.5G SDH system. It is possible to provide a four-channel STM-1 and one-channel STM-4 combined scrambling device so that the ASIC can be used in both STM-1 / STM-4 units.

In order to achieve the above object, the four-channel STM-1 and one-channel STM-4 dual scrambling apparatus according to the present invention,

An STM-1 pattern forming unit forming a 4-channel STM-1 pattern; An STM-4 pattern forming unit forming an STM-4 pattern of one channel; A selection unit which receives the scrambling patterns of the STM-1 and STM-4 pattern forming units and selects and outputs one pattern according to a transmission mode; The technical configuration is characterized in that it consists of a negative logic element that outputs scrambled data by performing a negative logic sum operation on the scrambling pattern selected by the selection unit and the input parallel data.

1 is a block diagram of a conventional STM-1 / 4 scrambling apparatus,

FIG. 2 is a block diagram showing the scrambling example of FIG.

Figure 3 is a block diagram of a four-channel STM-1 and one channel STM-4 combined scrambling apparatus according to an embodiment of the present invention,

FIG. 4 is a block diagram showing an example in which FIG. 3 is applied to STM-1.

FIG. 5 is a block diagram showing an example in which FIG. 3 is applied to STM-4.

Explanation of symbols on the main parts of the drawings

10: STM-1 / 4 scrambler 11 ~ 14: 4-channel STM-1 pattern forming part

15: 1 channel STM-4 pattern forming unit 16 ~ 19: Selecting unit

20 ~ 23: negative logic element

Hereinafter, an embodiment according to the technical concept of the STM-1 and STM-4 combined scrambling apparatus of one channel of the present invention as described above will be described.

Figure 3 is a block diagram of a four-channel STM-1 and one channel STM-4 combined scrambling apparatus according to the present invention.

As shown therein, the STM-1 pattern forming units 11 to 14 form a four-channel STM-1 pattern; An STM-4 pattern forming unit 15 forming an STM-4 pattern of one channel; A selection unit (16 to 19) that receives the scrambling patterns of the STM-1 and STM-4 pattern forming units (11 to 15) and selects and outputs one pattern according to a transmission mode; And a negative logic element 20 to 23 for outputting scrambled data by performing a negative logic sum operation on the scrambling pattern selected by the selector 16 to 19 and the input parallel data.

Operation of the four-channel STM-1 and one-channel STM-4 combined scrambling apparatus according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, we need to construct a circuit that negates and compares the 127 sequence data pattern with the input data using serial data streams of 155 Mbps (STM-1) and 622 Mbps (STM-4). Since it must be able to accept both -1 and STM-4 signals, generate the STM-1 data pattern and the STM-4 data pattern, respectively, and output the corresponding data pattern by input logic and negative logic sum depending on the transmission mode. do.

At this time, the output data patterns of the pattern forming units 11 to 15 are negated and arithmetic with parallel input data of 19 Mbps, and the data is 155 Mbps through 8: 1 multiplexing in the case of STM-1, and 8: in the case of STM-4. After the 1 multiplexing, the pattern is generated in consideration of the data of 622Mbps through 4: 1 multiplexing.

Therefore, when the frame pulse, which is a signal indicating the start position of the STM-1 frame, becomes logic1, the output value of the pattern forming units 11 to 15 is reset to the initial value, and then the pattern synchronized with the clock is obtained using a 19 MHz clock. Create

4 is a block diagram showing an example in which FIG. 3 is applied to STM-1.

That is, when the ASIC (Applicable Specific Integrated Circuit) to be used is the STM-1 mode, the data patterns from the first to fourth STM-1 pattern forming units 11 to 14 accommodating four channels are first to fourth. It selects from the selection part 16-19. Then, the first to fourth negative logic elements 20 to 23 perform an NOR operation on the STM-1 scramble pattern and parallel 19 Mbps input data. The 8: 1 multiplexer 31 outputs scrambled data sequentially according to the STM-1 data.

FIG. 5 is a block diagram showing an example in which FIG. 3 is applied to STM-4.

Thus, when the ASIC to be used is the STM-4 mode, the first to fourth selectors 16 to 19 select data patterns from the STM-4 pattern forming unit 15 accommodating one channel. Then, the first to fourth negative logic elements 20 to 23 perform an NOR operation on the STM-4 scramble pattern and the input parallel data of 19Mbps. The first to fourth 8: 1 multiplexers 32 to 35 and the 4: 1 multiplexer 36 output scrambled data sequentially according to the STM-4 data.

As such, the present invention enables scrambling of the 4-channel STM-1 signal and the 1-channel STM-4 signal among the tributary signals of the 2.5G SDH system so that the corresponding ASIC can be used in both STM-1 / STM-4 units. .

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the four-channel STM-1 and one-channel STM-4 dual scrambling apparatus according to the present invention enables the use of the scrambler for both the four-channel STM-1 and one-channel STM-4 signals. Depending on the mode, the -1 and 1-channel STM-4 dual ASICs enable scrambling of 4-channel STM-1 signals and scrambling of 1-channel STM-4 signals. This allows the ASIC to compress four existing 1-channel STM-1 ASICs into a single chip, which can also be used as an STM-4 combination to reduce the volume of integrated circuits and reduce power consumption. Phosphorus effect will occur.

Claims (1)

An STM-1 pattern forming unit forming a 4-channel STM-1 pattern; An STM-4 pattern forming unit forming an STM-4 pattern of one channel; A selection unit which receives the scrambling patterns of the STM-1 and STM-4 pattern forming units and selects and outputs one pattern according to a transmission mode; And a negative logic sum element configured to output a scrambled data by performing a negative logic sum operation on the scrambling pattern selected by the selecting unit and the parallel data input.