JPH086664A - Computer and its clock switching method - Google Patents

Abstract

PURPOSE:To switch a clock signal without previously providing plural clocks and stopping a device. CONSTITUTION:A synchronizing signal is sent and received through a synchronizing signal line 14 and then the clock signal synchronizing means of an external clock unit 12 synchronizes the clock signal that its own clock outputs with the clock signal outputted by a clock 10. Then a changeover switch 15 is switched so as to supply the clock signal from the external clock unit 12 to a bus A8 and a bus B9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer capable of exchanging clocks and its clock switching method.

[0002]

2. Description of the Related Art As a computer having fault tolerance,
There is a fault tolerant computer. In this fault tolerant computer, some or all of the constituent parts such as the CPU, the memory, the input / output part, the bus, etc. are provided in a plurality and redundant. With such a configuration, even if a failure occurs in a part of the constituent parts, the processing is replaced by another redundant part so that the entire device does not need to be stopped. Further, the repair and replacement of the defective portion can be performed without stopping the device, and the device can be continuously operated for 24 hours.

[0003]

However, even in a fault tolerant computer, the clock that supplies a clock signal as a reference for operation to each part cannot normally be redundant because it cannot be redundant if it fails. Only prepared. Further, in this fault tolerant computer, the cycle of the clock signal for its operation is changed. For this change, it is possible to supply a plurality of types of clock signals in advance.
You should have multiple clocks.

If a plurality of clocks are not prepared in advance, the device will be stopped when the clocks are exchanged for changing the clock signal. However, there is a limit in preparing a plurality of clocks in advance to cope with a change in a large number of clock signals, and it is expensive to arrange a large number of clocks in each of a plurality of devices. There was a problem.

The present invention has been made in order to solve the above problems, and it is possible to switch clock signals without stopping the apparatus without preparing a plurality of clocks in advance. The purpose is to do.

[0006]

A computer of the present invention includes a connector for receiving a clock signal supplied from a second clock provided separately from a first clock provided in advance in the computer, and this connector. A synchronizing means for synchronizing the clock signal from the second clock and the clock signal supplied from the first clock, and the clock signal supplied from the first clock and the second clock via a connector And a changeover switch for supplying the clock signal supplied from the computer to the bus of the computer.

According to the computer clock switching method of the present invention, a clock signal supplied from a second clock and a first clock provided separately from the first clock provided in the computer are supplied from the first clock. The clock signal from the first clock and the clock signal from the second clock obtained from outside the computer are switched and supplied to the bus of the computer in synchronization with the clock signal from the computer.

In addition, when the computer is using the clock signal supplied from the second clock, the first clock is exchanged with the third clock and the clock signal supplied from the second clock is exchanged. It is characterized in that the clock signal supplied from the third clock is synchronized with the clock signal supplied from the third clock, and the clock signal supplied from the second clock is switched to the clock signal supplied from the third clock and supplied to the bus.
The clock signal supplied from the third clock has a frequency different from that of the clock signal supplied from the first clock.

[0009]

The clock signal supplied by the second clock is the first
If it synchronizes with the clock signal supplied by the clock, the operation of the computer will not be disturbed regardless of which of the clock signals is supplied. If the clock signal supplied by the third clock is synchronized with the clock signal supplied by the second clock, the operation of the computer will not be hindered by switching the supplied clock signal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a schematic configuration of a fault tolerant computer according to an embodiment of the present invention.
In the figure, 1 is a computer, 2 is a main CPU,
3 is a sub CPU for making the main CPU 2 redundant, 4 is a main memory A, 5 is a main memory B for making the main memory A4 redundant, 6 is a main I / O, and 7 is a main I / O 6 for making it redundant. Sub I / O, 8 is a bus A, 9 is a bus B for making the bus A8 redundant, 10 is a clock for supplying a reference clock signal, and 11 is a connector for receiving a clock signal from the outside.

Further, 12 is an external clock unit for supplying a clock signal to the computer via the connector 11, 13a is a clock supply line for supplying a clock signal from the clock 10 to the buses A8 and B9, and 13b is from the external clock unit 12. Bus A via connector 11
8, a clock supply line for supplying a clock signal to the bus B9, 14 a synchronization signal line for synchronizing the clock 10 and the external clock unit 12, 15 a clock signal from the clock 10 and a clock from the external clock unit 12 It is a changeover switch for changing over to a signal. The external clock unit 12 includes a clock signal synchronizing means, and synchronizes its own clock with the clock 10 or synchronizes the clock 10 with its own clock via the synchronizing signal line 14.

In the structure described above, the external clock unit 12 is not normally connected to the connector 11. However, when the external clock unit 12 is connected to the connector 1
When connected to 1, the clock signal synchronizing means of the external clock unit 12 synchronizes the clock signal output by its own clock with the clock signal output by the clock 10 by transmitting and receiving the synchronization signal via the synchronization signal line 14.

After that, if the changeover switch 15 is switched to supply the clock signal from the external clock unit 12 to the buses A8 and B9, the clock signal is supplied without interruption, so that the computer 1 is stopped. There is nothing to do. And even if the clock 10 is removed, the computer 1 does not stop,
The clock 10 can be replaced by one that emits clock signals of different frequencies. After this exchange, this time, the clock signal synchronizing means of the external clock unit 12 synchronizes the clock signals output by the different clocks with the clock signals output by itself.

Then, by switching the changeover switch 15 so as to supply the clock signals from the clocks of different frequencies to the buses A8 and B9, the built-in clock 10 can be exchanged without stopping the computer 1. You can That is, as described above, the frequency of the clock signal to be supplied can be switched without stopping the computer 1. It is to be noted that not only when the built-in clock 10 is replaced with a clock having a different frequency but also when the clock 10 is replaced with a new one due to aging, it is the same as described above.
It can be replaced without stopping.

[0015]

As described above, according to the present invention, it is possible to exchange a clock for supplying a desired clock signal when needed, without stopping the computer. Therefore, clock signals having a plurality of frequencies can be used without preparing a plurality of clocks in advance. Also, for example, the clock changes over time, so it must be replaced at a certain time, but the computer does not have to be stopped at the time of this replacement.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a schematic configuration of a fault tolerant computer according to an embodiment of the invention.

[Explanation of symbols]

1 ... Computer, 2 ... Main CPU, 3 ... Sub CP
U, 4 ... Main memory A, 5 ... Main memory B, 6 ... Main I /
O, 7 ... Sub I / O, 8 ... Bus A, 9 ... Bus B, 10 ...
Clock, 11 ... Connector, 12 ... External clock unit, 13a, 13b ... Clock supply line, 14 ... Synchronous signal line, 15 ... Changeover switch.

Claims (4)

[Claims] 1. A computer for performing information processing and the like, and a connector for receiving a clock signal supplied from a second clock provided separately from a first clock provided in advance in the computer; Synchronization means for synchronizing the clock signal received from the second clock and the clock signal supplied from the first clock, and the clock signal supplied from the first clock and the second clock A computer provided with a changeover switch for switching between a clock signal supplied through the connector and supplying to a bus of the computer. 2. A computer for performing information processing and the like, wherein a clock signal supplied from a second clock provided separately from a first clock provided in advance in the computer and a clock signal supplied from the first clock. The clock signal from the first clock and the clock signal from the second clock obtained from outside the computer are switched and supplied to the bus of the computer. Computer clock switching method. 3. The computer clock switching method according to claim 2, wherein the first clock is exchanged with a third clock when the computer is using a clock signal supplied from the second clock. A clock signal supplied from the second clock and a clock signal supplied from the third clock are synchronized, and the clock signal supplied from the second clock is supplied from the third clock. And a clock switching method for a computer, characterized in that the clock is supplied to the bus. 4. The computer clock switching method according to claim 3, wherein the clock signal supplied from the third clock has a frequency different from that of the clock signal supplied from the first clock. How to switch the computer clock.