JPH04302016A - Reference signal generating circuit - Google Patents

Reference signal generating circuit

Info

Publication number
JPH04302016A
JPH04302016A JP3106338A JP10633891A JPH04302016A JP H04302016 A JPH04302016 A JP H04302016A JP 3106338 A JP3106338 A JP 3106338A JP 10633891 A JP10633891 A JP 10633891A JP H04302016 A JPH04302016 A JP H04302016A
Authority
JP
Japan
Prior art keywords
reference signal
output
phase
signal generator
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3106338A
Other languages
Japanese (ja)
Inventor
Tsugio Hori
次男 堀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3106338A priority Critical patent/JPH04302016A/en
Publication of JPH04302016A publication Critical patent/JPH04302016A/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To eliminate the rapid change of a phase at the time of switching a duplexed reference signal CONSTITUTION:One of output signals of two reference signal generators 11 and 12, is used as a reference, a phase difference between the two signals is detected, and the detected phase difference is adjusted by a delay circuit 14, so that the phase of the two reference signals can be made equal.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、基準信号発生回路の発
振出力の位相制御手段に関する。本発明は移動通信無線
装置に利用する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to means for controlling the phase of the oscillation output of a reference signal generating circuit. INDUSTRIAL APPLICATION This invention is utilized for a mobile communication radio|wireless apparatus.

【0002】0002

【従来の技術】装置内で使用するクロックのもとになる
信号を生成する基準信号発生回路は従来から二重化され
、一方の基準信号発生回路に障害が発生した場合でも装
置が動作不能にならないように構成されている。図2は
、従来の基準信号発生回路の一例を示す。図に示すよう
に、従来例では信号発生源として第一の基準信号発生器
21と第二の基準信号発生器22をもち、第一と第二そ
れぞれの基準信号発生器21、22の出力を入力とする
出力選択回路23から構成され、制御信号24により出
力選択回路23で第一の基準信号発生器21の出力また
は第二の基準信号発生器22の出力の一方を選択して基
準信号として出力していた。
2. Description of the Related Art Conventionally, reference signal generation circuits that generate signals that are the basis of clocks used in devices have been duplicated, so that even if one of the reference signal generation circuits fails, the device will not become inoperable. It is composed of FIG. 2 shows an example of a conventional reference signal generation circuit. As shown in the figure, the conventional example has a first reference signal generator 21 and a second reference signal generator 22 as signal generation sources, and the outputs of the first and second reference signal generators 21 and 22 are used as signal generation sources. The output selection circuit 23 selects either the output of the first reference signal generator 21 or the output of the second reference signal generator 22 as a reference signal in response to a control signal 24. It was outputting.

【0003】0003

【発明が解決しようとする課題】このような従来の基準
信号発生回路では、第一の基準信号発生器21の出力信
号と第二の基準信号発生器22の出力信号の位相が異な
るので、出力選択回路23で第一の基準信号発生器21
の出力信号と第二の基準信号発生器22の出力信号を切
替えたときに出力選択回路23の出力信号の位相が急に
変わり、この出力信号を使用している回路では少しの間
様々な異常動作を起こす場合が生ずる (例えば、シン
セサイザが少しの間アンロック状態になる)欠点があっ
た。
In such a conventional reference signal generation circuit, the output signal of the first reference signal generator 21 and the output signal of the second reference signal generator 22 are different in phase. The first reference signal generator 21 in the selection circuit 23
When switching between the output signal of the second reference signal generator 22 and the output signal of the second reference signal generator 22, the phase of the output signal of the output selection circuit 23 suddenly changes, causing various abnormalities in the circuit using this output signal for a short time. There was a drawback that there were cases where the synthesizer would be activated (for example, the synthesizer would be in an unlocked state for a short period of time).

【0004】本発明は、このような欠点を除去するもの
で、出力の切り換え時の位相急変を防止する手段をもつ
基準信号発生回路を提供することを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to eliminate such drawbacks and to provide a reference signal generating circuit having means for preventing sudden changes in phase when switching outputs.

【0005】[0005]

【課題を解決するための手段】本発明は、第一の基準信
号発生器と、第二の基準信号発生器と、上記第一の基準
信号発生器の第一の出力信号または上記第二の基準信号
発生器の第一の出力信号に係わる信号のいずれか一方を
制御信号に応じて選択する出力選択回路とを備えた基準
信号発生回路において、上記第一の基準信号発生器の第
二の出力信号と上記第二の基準信号発生器の第二の出力
信号との位相差を検出する位相検出回路と、この位相検
出回路からの位相制御信号に応じて上記第二の基準信号
発生器の第一の出力信号の位相を変化させ、上記第二の
基準信号発生器の第一の出力信号に係わる信号として上
記出力選択回路に与える遅延回路とを備えたことを特徴
とする。
[Means for Solving the Problems] The present invention includes a first reference signal generator, a second reference signal generator, and a first output signal of the first reference signal generator or the second output signal. and an output selection circuit that selects one of the signals related to the first output signal of the reference signal generator according to a control signal, wherein the second output signal of the first reference signal generator is a phase detection circuit for detecting a phase difference between the output signal and a second output signal of the second reference signal generator; and a phase detection circuit for detecting a phase difference between the output signal and a second output signal of the second reference signal generator; The present invention is characterized by comprising a delay circuit that changes the phase of the first output signal and supplies it to the output selection circuit as a signal related to the first output signal of the second reference signal generator.

【0006】[0006]

【作用】二つの基準信号発生器の出力信号のうち一方の
出力信号の位相を基準として二つの信号間の位相差を検
出し、検出された位相差分を遅延回路で調整する。これ
より二つの基準信号の位相を等しくし、切り換え時の位
相急変を防ぐ。
[Operation] The phase difference between the two signals is detected using the phase of one of the output signals of the two reference signal generators as a reference, and the detected phase difference is adjusted by the delay circuit. This makes the phases of the two reference signals equal and prevents sudden changes in phase during switching.

【0007】[0007]

【実施例】以下、本発明の一実施例について図面を参照
して説明する。図1はこの実施例の構成図である。この
実施例は、図1に示すように、基準信号発生器11と、
基準信号発生器12と、基準信号発生器11の第一の出
力信号または基準信号発生器12の第一の出力信号に係
わる信号のいずれか一方を制御信号に応じて選択する出
力選択回路15とを備え、さらに、本発明の特徴とする
手段として、基準信号発生器11の第二の出力信号と基
準信号発生器12の第二の出力信号との位相差を検出す
る位相検出回路13と、この位相検出回路13からの位
相制御信号に応じて基準信号発生器12の第一の出力信
号の位相を変化させ、基準信号発生器12の第一の出力
信号に係わる信号として出力選択回路15に与える遅延
回路14とを備える。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of this embodiment. As shown in FIG. 1, this embodiment includes a reference signal generator 11,
a reference signal generator 12; and an output selection circuit 15 that selects either the first output signal of the reference signal generator 11 or a signal related to the first output signal of the reference signal generator 12 according to a control signal. Further, as means characteristic of the present invention, a phase detection circuit 13 for detecting a phase difference between the second output signal of the reference signal generator 11 and the second output signal of the reference signal generator 12; The phase of the first output signal of the reference signal generator 12 is changed according to the phase control signal from the phase detection circuit 13, and the signal is sent to the output selection circuit 15 as a signal related to the first output signal of the reference signal generator 12. and a delay circuit 14 that provides a delay circuit.

【0008】次に、この実施例の動作を説明する。基準
信号発生器11および基準信号発生器12は位相の異な
る基準信号を発生する。各基準信号発生器11、12の
第一の出力信号は位相検出回路13に入力される。基準
信号発生器11、12の第1の出力信号を入力とする位
相検出回路13では、基準信号発生器11の出力信号の
位相を基準として基準信号発生器11の出力信号と基準
信号発生器12の出力信号との位相差を検出し、その位
相差に応じた制御信号を発生して遅延回路14に入力す
る。遅延回路14では、基準信号発生器12の第二の出
力信号を入力として位相検出回路13からの制御信号に
応じて入力信号の位相を変化させ、基準信号発生器11
の出力信号の位相と等しくなるように制御する。基準信
号発生器11の出力信号と同じ位相をもつ遅延回路14
の出力信号は出力選択回路15へ入力される。出力選択
回路15では、基準信号発生器11の第二の出力信号と
遅延回路14の出力信号を入力とし、制御信号によりい
ずれか一方が選択されて基準信号として出力される。
Next, the operation of this embodiment will be explained. Reference signal generator 11 and reference signal generator 12 generate reference signals having different phases. A first output signal of each reference signal generator 11, 12 is input to a phase detection circuit 13. A phase detection circuit 13 that receives the first output signals of the reference signal generators 11 and 12 uses the phase of the output signal of the reference signal generator 11 as a reference to detect the output signal of the reference signal generator 11 and the reference signal generator 12. Detects the phase difference with the output signal of the output signal, generates a control signal corresponding to the phase difference, and inputs the control signal to the delay circuit 14. The delay circuit 14 inputs the second output signal of the reference signal generator 12 and changes the phase of the input signal according to the control signal from the phase detection circuit 13.
control so that the phase is equal to the phase of the output signal. A delay circuit 14 having the same phase as the output signal of the reference signal generator 11
The output signal is input to the output selection circuit 15. The output selection circuit 15 receives the second output signal of the reference signal generator 11 and the output signal of the delay circuit 14, and selects one of them by a control signal and outputs the selected signal as a reference signal.

【0009】[0009]

【発明の効果】本発明は位相の異なる二つの基準信号発
生器の出力の位相差を位相検出回路により検出し、遅延
回路で一方の基準信号発生器の位相を他の基準信号と同
位相にするので、出力選択回路へ入力される二つの入力
信号を切り替えても出力信号の位相は変化せず、切替時
に起こる基準信号の急激な位相変化により起こる異常動
作(例えばシンセサイザーがアンロック状態となる)の
発生を防ぐことができる効果がある。
[Effects of the Invention] The present invention uses a phase detection circuit to detect the phase difference between the outputs of two reference signal generators having different phases, and uses a delay circuit to adjust the phase of one reference signal generator to the same phase as the other reference signal. Therefore, even if the two input signals input to the output selection circuit are switched, the phase of the output signal does not change, and abnormal operation (for example, the synthesizer becomes unlocked) due to the sudden phase change of the reference signal that occurs at the time of switching. ) has the effect of preventing the occurrence of

【図面の簡単な説明】[Brief explanation of drawings]

【図1】  本発明実施例の構成を示すブロック構成図
FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention.

【図2】  従来例の構成を示すブロック構成図。FIG. 2 is a block configuration diagram showing the configuration of a conventional example.

【符号の説明】[Explanation of symbols]

11    基準信号発生器 12    基準信号発生器 13    位相検出回路 14    遅延回路 15    出力選択回路 16    制御信号入力端子 17    基準信号出力端子 21    基準信号発生器 22    基準信号発生器 23    出力選択回路 24    制御信号入力端子 25    基準信号出力端子 11. Reference signal generator 12 Reference signal generator 13 Phase detection circuit 14 Delay circuit 15 Output selection circuit 16 Control signal input terminal 17 Reference signal output terminal 21 Reference signal generator 22 Reference signal generator 23 Output selection circuit 24 Control signal input terminal 25 Reference signal output terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  第一の基準信号発生器と、第二の基準
信号発生器と、上記第一の基準信号発生器の第一の出力
信号または上記第二の基準信号発生器の第一の出力信号
に係わる信号のいずれか一方を制御信号に応じて選択す
る出力選択回路とを備えた基準信号発生回路において、
上記第一の基準信号発生器の第二の出力信号と上記第二
の基準信号発生器の第二の出力信号との位相差を検出す
る位相検出回路と、この位相検出回路からの位相制御信
号に応じて上記第二の基準信号発生器の第一の出力信号
の位相を変化させ、上記第二の基準信号発生器の第一の
出力信号に係わる信号として上記出力選択回路に与える
遅延回路とを備えたことを特徴とする基準信号発生回路
1. A first reference signal generator, a second reference signal generator, and a first output signal of the first reference signal generator or a first output signal of the second reference signal generator. A reference signal generation circuit comprising an output selection circuit that selects one of the signals related to the output signal according to a control signal,
a phase detection circuit that detects a phase difference between a second output signal of the first reference signal generator and a second output signal of the second reference signal generator; and a phase control signal from the phase detection circuit. a delay circuit that changes the phase of the first output signal of the second reference signal generator in accordance with and supplies it to the output selection circuit as a signal related to the first output signal of the second reference signal generator; A reference signal generation circuit comprising:
JP3106338A 1991-03-28 1991-03-28 Reference signal generating circuit Pending JPH04302016A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3106338A JPH04302016A (en) 1991-03-28 1991-03-28 Reference signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3106338A JPH04302016A (en) 1991-03-28 1991-03-28 Reference signal generating circuit

Publications (1)

Publication Number Publication Date
JPH04302016A true JPH04302016A (en) 1992-10-26

Family

ID=14431069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3106338A Pending JPH04302016A (en) 1991-03-28 1991-03-28 Reference signal generating circuit

Country Status (1)

Country Link
JP (1) JPH04302016A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH086664A (en) * 1994-06-15 1996-01-12 Nec Corp Computer and its clock switching method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH086664A (en) * 1994-06-15 1996-01-12 Nec Corp Computer and its clock switching method

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