JP2004023470A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit whereby frequency deviation is eliminated in a produced signal while stabilizing its operation when a reference signal is switched. <P>SOLUTION: The PLL circuit includes: a phase comparator 1; an integrator circuit 2; a voltage-controlled oscillator 3; a frequency divider circuit 4; a selection circuit 7 for selecting either of two received reference signals 5, 6; and a phase difference elimination circuit 8 having a function of canceling a phase difference between the two reference signals, and the phase difference elimination circuit 8 includes: a signal input detection circuit 9 for monitoring the two received reference signals 5, 6 to detect whether or not the two received reference signals 5, 6 exist; a phase difference presence detection circuit 10 for detecting the presence / absence of the phase difference between the two received reference signals 5, 6; and a delay circuit 11 for delaying either of the two received reference signals 5, 6. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a PLL (Phase Locked Loop) circuit used in an electrical device requiring a signal of a desired frequency such as a communication device.
[0002]
[Prior art]
FIG. 3 is a block diagram showing a conventional PLL circuit (phase locked loop circuit). In FIG. 3, 1 is a phase comparator, 2 is an integrator (low-pass filter), and 3 is a voltage controlled oscillator. And 4 is a frequency dividing circuit. The basic circuit of the PLL circuit includes a phase comparator 1, an integrating circuit 2, a voltage controlled oscillator 3, and a frequency dividing circuit 4. Reference numerals 5 and 6 denote reference signals input to the PLL circuit, reference numeral 20 denotes a selection signal, and reference numeral 7 denotes a reference signal selector for selecting one of the reference signal 5 and the reference signal 6 based on the selection signal 20.
[0003]
Next, the operation will be described.
The reference signal (either the reference signal 5 or the reference signal 6) output from the reference signal selector 7 and the frequency-divided signal output from the frequency divider 4 are input to the phase comparator 1, and the phase difference between the two is calculated. A pulse signal is output based on the signal. The pulse signal output from the phase comparator 1 is input to the integration circuit 2 and is output from the integration circuit 2 as a certain voltage value. The voltage value output from the integration circuit 2 is input to a voltage controlled oscillator 3, which generates a signal (hereinafter, referred to as an “output signal”) with a change in frequency proportional to a change in voltage. .
[0004]
This output signal is a desired signal in the device. The output signal is input to the frequency dividing circuit 4, where the output signal is frequency-divided so as to be close to the frequency of the reference signal, and output from the frequency dividing circuit 4 as a frequency-divided signal. The frequency-divided signal output from the frequency divider 4 is input to the phase comparator 1 together with the reference signal. This is the basic operation of the PLL circuit, and it is characterized in that there are two systems of reference signals in a redundant configuration (duplexing), and one of them can be selected (either the reference signal 5 or the reference signal 6).
[0005]
[Problems to be solved by the invention]
Since the conventional PLL circuit is configured as described above, when the reference signal is switched, if the phase difference exists between the two reference signals, the operation of the PLL circuit instantaneously becomes unstable. In some cases, the frequency of the generated signal may be deviated, and the reference signal is a reference for basic operations such as timing generation in many electronic devices. There is a problem that this affects the entire apparatus, and more specifically, erroneous recognition (error) of digital data handled by the apparatus occurs instantaneously. In addition, since a device that requires duplication of the reference signal is fundamentally required to have stability and is configured as such, unstable operation greatly influences such an instantaneous error. There was a problem that the specification had to be specified so as to allow the above.
[0006]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and it is intended that, when a reference signal is switched, the generated signal does not have a frequency shift while the operation remains stable. An object is to obtain a PLL circuit.
[0007]
[Means for Solving the Problems]
A PLL circuit according to the present invention includes a phase comparator, an integrating circuit, a voltage controlled oscillator, a frequency dividing circuit, and a selecting circuit for selecting two input reference signals. A phase difference canceling circuit having a function of canceling the phase difference is further provided.
[0008]
In a PLL circuit according to the present invention, a phase difference canceling circuit has a signal input detection circuit that monitors two input reference signals to detect whether or not two reference signals are present. It works when exists.
[0009]
In the PLL circuit according to the present invention, the phase difference canceling circuit operates in response to a detection signal indicating the presence of two reference signals from two input reference signal supply sources.
[0010]
In the PLL circuit according to the present invention, the phase difference canceling circuit further includes a phase difference existence detecting circuit for detecting the presence or absence of a phase difference between the two reference signals, and a delay circuit for delaying one of the two reference signals. It is.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described.
Embodiment 1 FIG.
FIG. 1 is a configuration diagram showing a PLL circuit according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 8 denotes a phase difference canceling circuit. 9 is a signal input detection circuit, 10 is a phase difference existence detection circuit, and 11 is a delay circuit. The phase difference elimination circuit 8 includes a signal input detection circuit 9, a phase difference presence detection circuit 10, and a delay circuit 11. The components denoted by the same reference numerals as those in FIG. 3 are the same as the components denoted by the reference numerals in FIG.
[0012]
Next, the operation will be described.
The operation of the basic circuit (1, 2, 3, 4) of the PLL circuit and the existence and switching of the two reference signals (5, 6) are the same as those of the conventional PLL circuit shown in FIG. The difference from the conventional PLL circuit is that a phase difference canceling circuit 8 is added.
[0013]
Before selecting a reference signal to be input to the PLL circuit, a phase difference between the two reference signals (5, 6) is eliminated. The signal input detection circuit 9 has a function of detecting whether or not both reference signals are input, and the phase difference canceling circuit 8 operates only when two reference signals (5, 6) are input. I have to.
[0014]
The phase difference presence detection circuit 10 determines whether one of the reference signals (either the reference signal 5 or the reference signal 6) is significant (the presence of a pulse) and the other is significant. . If both signals are significant at the same time, it is determined that there is no phase difference. If one of the reference signals is significant and the other is not significant, it is determined that a phase difference exists.
[0015]
If it is determined that there is a phase difference, the delay circuit 11 applies a delay process in units of time of the pulse width to one of the reference signals. The delay circuit 11 can perform (unit time × natural number) delay processing. First, a delay process of (unit time × 1) is performed, and then the operation of the phase difference determination is performed again. If it is determined that there is a further phase difference, a (unit time × 2) delay process is performed. In this manner, the phase difference determination and the delay processing are repeated, and the operation is repeated until the phase is moved by the unit time and it is determined that there is no phase difference.
[0016]
The delay circuit 11 does not set a delay time for an arbitrary natural number, but performs an operation of superimposing the delay time for each signal instructing the delay processing. Therefore, this natural number does not determine the delay time by performing a process such as binary conversion, but is simply the number of times the phase difference existence determination process and the unit time delay process are repeated. Therefore, the delay circuit 11 is relatively simple. Although the number of times the delay processing is repeated (natural number), the maximum value of the natural number is determined so that (unit time × natural number) becomes the time of the cycle of the reference signal, and the operation is defined such that the maximum value is set as the upper limit. ing.
[0017]
By the operation described above, when the phase difference between the two reference signals (5, 6) disappears, the operation of the PLL circuit does not become unstable even when the reference signals are switched, and the desired generated signal (output signal) is not generated. Since the frequency does not shift, the operation of the device does not become unstable, and no instantaneous error occurs.
[0018]
As described above, the PLL circuit according to the first embodiment includes a phase comparator (1), an integrating circuit (2), a voltage controlled oscillator (3), and a frequency dividing circuit (4). A selection circuit (7) for selecting one of the two reference signals (5, 6), and further comprising a phase difference canceling circuit (8) having a function of canceling a phase difference between the two reference signals (5, 6). It is.
[0019]
In the PLL circuit according to the first embodiment, the phase difference canceling circuit (8) monitors two input reference signals (5, 6) and determines whether two reference signals (5, 6) exist. , And operates when two reference signals (5, 6) are present.
[0020]
In the PLL circuit according to the first embodiment, a phase difference elimination circuit (8) includes a phase difference existence detection circuit (10) for detecting the presence or absence of a phase difference between two reference signals (5, 6), and two reference signals. And a delay circuit (11) for delaying one of the signals (5, 6).
[0021]
As described above, according to the first embodiment, since the phase difference between the two input reference signals is eliminated, there is a possibility that the frequency shift of the generated signal may occur when the reference signals are switched. The effect of preventing occurrence of an error is obtained.
[0022]
As described above, according to the first embodiment, since two input reference signals are monitored, it is possible to obtain in advance whether it is possible to switch the reference signals.
[0023]
As described above, according to the first embodiment, since the phase difference between the two reference signals input using the delay circuit is eliminated, the effect of simplifying the circuit configuration is obtained.
[0024]
Embodiment 2 FIG.
FIG. 2 is a configuration diagram showing a PLL circuit according to a second embodiment of the present invention. In FIG. 2, reference numeral 21 denotes a detection signal. The components denoted by the same reference numerals as those in FIG. 1 are the same as the components denoted by the reference numerals in FIG.
[0025]
Next, the operation will be described.
In the second embodiment, the signal input detection circuit 9 for detecting whether both of the reference signals are input is used in the first embodiment, whereas the reference signal from two reference signal supply sources is used. A detection signal 21 indicating whether a signal is present is input to the phase difference presence detection circuit 10.
[0026]
In the first embodiment, the signal input detection circuit 9 monitors the reference signal itself flowing in the PLL circuit unit. On the other hand, in the second embodiment, when there is a signal indicating the presence of the reference signal from the reference signal supply source for the purpose of referencing when selecting one of the two reference signals, for example, The signal is used as the detection signal 21 to replace the signal input detection circuit 9. When two reference signals are present, the phase difference canceling circuit operates. Other operations are the same as in the first embodiment.
[0027]
As described above, the PLL circuit according to the second embodiment includes a phase comparator (1), an integrating circuit (2), a voltage controlled oscillator (3), and a frequency dividing circuit (4). A selection circuit (7) for selecting one of the two reference signals (5, 6), and further comprising a phase difference canceling circuit (8) having a function of canceling a phase difference between the two reference signals (5, 6). It is.
[0028]
In the PLL circuit according to the second embodiment, the phase difference canceling circuit (8) detects the presence of two reference signals (5, 6) from the supply sources of the two input reference signals (5, 6). It operates according to the signal (21).
[0029]
In the PLL circuit according to the second embodiment, a phase difference elimination circuit (8) includes a phase difference existence detection circuit (10) for detecting the presence or absence of a phase difference between two reference signals (5, 6), and two reference signals. And a delay circuit (11) for delaying one of the signals (5, 6).
[0030]
As described above, according to the second embodiment, since the phase difference between the two input reference signals is eliminated, there is a possibility that the frequency shift of the generated signal may occur when the reference signals are switched. The effect of preventing occurrence of an error is obtained.
[0031]
As described above, according to the second embodiment, the operation is performed in response to the detection signals indicating the presence of the two reference signals from the two input sources of the reference signals. An effect is obtained that the signal need not be directly monitored.
[0032]
As described above, according to the second embodiment, since the phase difference between the two reference signals input using the delay circuit is eliminated, the effect that the circuit configuration can be simplified can be obtained.
[0033]
【The invention's effect】
As described above, according to the present invention, since the phase difference between the two input reference signals is eliminated, the occurrence of an error due to the frequency shift of the generated signal which may occur when the reference signals are switched is generated. Has the effect of preventing.
[0034]
According to the present invention, two input reference signals are monitored, so that it is possible to know in advance whether switching of the reference signals is possible.
[0035]
According to the present invention, it is configured to operate in response to the detection signal indicating the presence of the two reference signals from the input sources of the two input reference signals, so that it is not necessary to directly monitor the two reference signals. effective.
[0036]
According to the present invention, since the phase difference between the two reference signals input using the delay circuit is eliminated, the circuit configuration can be simplified.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a PLL circuit according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram showing a PLL circuit according to a second embodiment of the present invention.
FIG. 3 is a configuration diagram showing a conventional PLL circuit.
[Explanation of symbols]
1 phase comparator, 2 integrator, 3 voltage controlled oscillator, 4 divider, 5, 6 reference signal, 7 reference signal selector, 8 phase difference elimination circuit, 9 signal input detection circuit, 10 phase difference presence detection circuit, 11 delay circuit, 20 selection signal, 21 detection signal.

Claims (4)

In a PLL circuit including a phase comparator, an integrating circuit, a voltage controlled oscillator, a frequency dividing circuit, and a selecting circuit for selecting two input reference signals,
A PLL circuit further comprising a phase difference canceling circuit having a function of canceling a phase difference between the two reference signals. The phase difference canceling circuit has a signal input detection circuit that monitors two input reference signals to detect whether the two reference signals are present, and operates when the two reference signals are present. The PLL circuit according to claim 1, wherein 2. The PLL circuit according to claim 1, wherein the phase difference canceling circuit operates in response to a detection signal indicating the presence of the two reference signals from two input reference signal supply sources. The phase difference cancellation circuit
A phase difference presence detection circuit for detecting the presence or absence of a phase difference between the two reference signals,
4. The PLL circuit according to claim 2, further comprising a delay circuit for delaying one of the two reference signals.

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