JPH08102665A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE: To prevent the generation of a phase jump and to attain smooth and stable switching by providing this phase synchronizing circuit with a frequency divider for obtaining an output signal matched with the phase of a reference signal, an input detection means and a switching means. CONSTITUTION: The OFF of an input signal A is detected by a detection part 104. Namely when the input signal A is defined as a signal to be fixed at 'H' at the time of being turned off, the input signal A is judged as a normal state when its logic is 'L' on the rise position of a mask signal or judged as an off state in the case of 'H'. When the input signal A is turned off, the output from a selection part 106 is switched from an input mask signal A' to a self- advancing signal B. In this case, the signal B is generated based upon the rise of the signal A', and since the phase of rise coincides with each other in both the signals A', B up to immediately before switching, a reference signal Dk phase jump is not generated in any output from the selection part 106. At the rise of the mask signal immediately after the rise of the input signal A on the H part of the mask signal, the logic of a SEL signal is switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is used in the field of telecommunications.
The present invention relates to a device that switches between two reference signals of an LL circuit. In particular, the present invention relates to the case where the original clock N times as large as the PLL circuit reference signal exists in only one system.

[0002]

2. Description of the Related Art FIG. 19 shows a conventional PLL circuit disclosed in, for example, Japanese Patent Laid-Open No. 3-27620. In the figure, 1 is an oscillator for generating the original clock of the signal A, 2 is an oscillator for generating the original clock of the signal B, and 3 is 1 from the signals A and B.
A selector for selecting two signals and outputting a signal C; 4 a detector for giving an instruction to the selector 3; 5 a frequency divider for dividing the signal C selected by the selector 3 by N to obtain a reference signal D; Reference numerals 6 and 11 are switches, 7 is a phase comparator for comparing the phases of the reference signal D and the comparison signal E, 8 is a loop filter, 9 is a voltage controlled oscillator, and 10 is an output signal of the voltage controlled oscillator 9. A frequency divider for obtaining the signal E, 12 is a control unit for resetting 5, 10.

Next, the operation of the conventional technique will be described. In the conventional circuit, the switches 6 and 11 are opened immediately before the signal is switched to bring the output of the phase comparator 7 into a high impedance state. The loop filter 8 holds the input voltage of the voltage controlled oscillator 9, and the system is switched by the selection unit 3 in this state. After the switching, the frequency dividers 5 and 10 are reset to match the phases of the reference signal D and the comparison signal E, and then the switches 6 and 11 are closed. For that purpose, both systems need N times the original clock of the reference signal. When the original clock of N times the signal exists in only one system, the two frequency dividers are reset only when switching to the system in which the original clock exists, and the phases of the reference signal D and the comparison signal E are matched. be able to.

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the LL circuit reference signal switching circuit, there is a problem that the frequency of the PLL circuit output signal becomes unstable because a phase jump occurs in the reference signal D when switching to a system in which there is no N times the original clock of the reference signal. It was Also, it was premised that the signals were normally input until the signals were switched.

The present invention has been made in order to solve the above-mentioned problems. A circuit for immediately detecting a signal disconnection and switching the signal, and an original reference signal for the PLL circuit are provided. An object of the present invention is to obtain a phase-locked circuit that prevents a phase jump of a reference signal and outputs a stable output even when switching to a system in which a swing clock does not exist. Further, it is an object of the present invention to obtain a phase locked loop circuit which can perform the synchronization more quickly and stably.

[0006]

A phase-locked loop circuit according to the present invention divides a reference clock by N and generates a free-running signal B in phase with an input signal A which is one reference input. And an input detecting means for detecting a disconnection of the input signal A, detecting that the recovery of the input signal A is in phase with the free-running signal B, and issuing a switching signal, and the switching signal A switching means for switching and outputting the input signal A and the free-running signal B to be used as an input for phase comparison of the phase locked loop, and a phase control means for forming a closed loop for controlling the voltage controlled oscillator by the phase comparison input are provided.

Another phase-locked loop circuit of the present invention divides a reference clock by N to generate a free-running signal B, and outputs a mask signal from the reference clock, and an input signal A.
Input detecting means for detecting a disconnection of the input signal and outputting a switching signal, a reset circuit for receiving the input signal A and the switching signal and outputting a reset signal to the frequency divider, the input signal A and the switching signal by the switching signal. A switching means for switching and outputting the free-running signal B to be used as an input for phase comparison of the phase locked loop, and a phase control means for forming a closed loop for controlling the voltage controlled oscillator by the phase comparison input are provided.

Further, the frequency divider is configured to output a mask signal by variably setting a predetermined mask width.

Furthermore, an instruction means for monitoring the recovery of the input signal A and outputting an instruction signal for a certain period is provided, and the frequency divider has a structure in which the frequency division ratio can be varied. I changed the ratio.

Further, a monitoring instruction means for monitoring the input signal A and the free-running signal B is provided, and the reset timing of the reset circuit is changed by the instruction output of the monitoring instruction means.

Furthermore, a reset limiting circuit for limiting the reset output is provided to limit the number of resets as necessary.

Furthermore, a phase difference reset limiting circuit for limiting the reset output by the phase difference of the bit clock of the demodulator is provided to limit the number of resets as necessary.

[0013]

In the phase locked loop circuit according to the present invention, the input signal A is normally selected by the switching means to be the input of the phase control means, but the phase of the free-running signal B is matched with the input signal A. Even when the input signal A is disconnected, the free-running signal B is switched in phase with the input signal A, and when the input signal A is recovered, it is switched in phase with the input signal A, so that the frequency and phase of the output signal of the voltage controlled oscillator are not changed .

In another phase locked loop circuit of the present invention, the input signal A is synchronously monitored by a mask generated by a reference clock,
Normally, this input signal A is switched and selected to be input to the phase control means, but when switching to the free-running signal B due to disconnection of the input signal A, the switching timing of the free-running signal B is selected by resetting. Also, at the time of restoration, the input signal A and the mask signal are synchronized and switched and selected.

Furthermore, the mask signal width changes.

Furthermore, the frequency division ratio for generating the free-running signal B at the time of restoration is changed, and the time until completion of switching is shortened.

Furthermore, due to the phase difference between the two signals to be monitored, the frequency division ratio for generating the free-running signal B at the time of restoration is changed in the direction in which the switching completion time is shortened, and the switching completion time is shortened.

Furthermore, the switching timing at the time of restoration is limited if necessary, and the switching time is controlled.

Further, the switching timing at the time of restoration is limited according to the phase difference of the bit clock of the demodulator, and the switching time is controlled.

[0020]

【Example】

Example 1. FIG. 1 shows the configuration of a phase locked loop circuit which is an embodiment of the present invention. Reference numeral 101 is an oscillator that supplies an original clock of N times the free-running signal B, and 102 is a counter unit that divides the original clock by N to obtain the free-running signal B. 103
In the mask section, an input mask signal A ′ is generated from the input signal A by a mask signal described later. A detection unit 104 detects a disconnection of the input signal. Reference numeral 105 is a reset circuit, and 106 is a selector for selecting the input mask signal A ′ and the free-running signal B.
Is a PLL circuit. The PLL circuit 200 has, as a detailed configuration, a low-pass filter of the phase comparator 202 of 201,
It is composed of a closed loop composed of a voltage controlled oscillator 203 and an N frequency divider 204. FIG. 2 is a diagram for explaining the relationship between the input mask signal A ′, the free-running signal B and the counter unit (frequency divider), FIG. 3 is a diagram for showing the relationship between the counter unit and the mask signal output from the mask unit, and FIG. It is a figure explaining operation | movement of the mask circuit at the time.

Next, the operation of the phase locked loop circuit having the above configuration will be described. First, in a normal state, that is, when the input signal A is correctly input, as shown in FIG. 2, the reset portion detects the rising edge of the input mask signal A ′, and at that timing, shifts from FIG. 2A to FIG. The counter unit 102 as indicated by the arrow
Has been reset. Furthermore, resetting is necessary only during normal operation, and the SEL signal to be described later is output under the AND condition when "H". The input mask signal A ′ is a signal obtained by processing the input signal A in the mask section described later. Since the rising edge is aligned with the input signal A, the free-running signal B is in phase synchronization with the input signal A. That is, what is important is that the phase of the input signal A and the phase of the free-running signal B are aligned when switching is performed. When the input mask signal A ′ does not rise (when the input signal A is off), the counter value is self-reset by self-resetting. The generation of the mask signal to be sent to the mask section is performed by decoding the counter value as shown in FIG. That is, for example, the counter is "H" only from N-4 to N4.
Is output. The width of the mask is set to be larger than the amount of jitter of the input signal A and as narrow as possible.

Further, in the normal state, as shown in FIG. 4, the mask section 103 generates an input mask signal A ′ which is valid only in the section where the rising edge of the input signal A is “H”, and the selection section 106 is provided. Output. The processed input mask signal A'is self-reset to "L" so that the duty ratio becomes 50%. If it is no longer valid, the output of the input mask signal A'is fixed at "L" thereafter. Switching of signals in the selection unit 106 is performed by selecting (hereinafter, SEL
When the signal is "H", the input mask signal A'is changed to "
When L ", the phase comparator 2 uses the free-running signal B as the reference signal D.
Output to 01. In the PLL circuit including the loop filter (LPF) 202, the voltage controlled oscillator (VCO) 203, and the frequency divider 204, the output signal (comparison signal E) of the frequency divider 204 has the same rising edge as the reference signal D. With such a circuit configuration, it is possible to prevent a phase jump even if the sync signal A is disconnected at any timing.

Next, the switching operation at the time of abnormality will be described. FIG. 5 corresponds to FIG. 4 and is a switching signal when the input signal is disconnected, FIGS. 6 and 7 are switching operations when the input clock is disconnected, and FIG. 8 is a diagram in which the input clock is restored and the free-running signal B to the input signal A are recovered.
It is a figure explaining the switching operation to. The detection unit 104 detects the disconnection of the input signal. That is, if the input signal A is a signal that is fixed to H when disconnected, it is determined to be normal if the logic of the input signal A is "L" at the rising position of the mask signal, and disconnected if it is "H". As shown in FIG. 5, the detection result is “H” if it is normal as a SEL signal, but if a disconnection is detected, it is set to “L” in synchronization with the rising edge of the mask signal and output to the selection unit 106. Of course SE
The logic of the L signal may be reversed. When the input signal A is disconnected, the output of the selection unit 106 is switched from the input mask signal A ′ to the free-running signal B. FIG. 6 shows the case where the disconnection occurs in the section where the input signal A is “H”. Input signal A'is "L"
The figure shows the case where a disconnection occurs in the section. In this case, the free-running signal B is generated with reference to the rising edge of the input mask signal A ′, and the phases of the rising edges match immediately before the switching. Therefore, as shown in FIG. No phase jump is seen.

When the input signal A is restored from the disconnection, the selection unit 106
A state in which the output of the above is switched from the free-running signal B to the input mask signal A ′ will be described with reference to FIG. When the sync signal is restored, the SEL signal does not switch to "H" until the input signal A rises at the "H" portion of the mask signal, and the mask signal immediately after the input signal A rises at the mask signal "H" portion. The logic of the SEL signal is first switched at the rising edge of. When the input signal A recovers from the disconnection state, the rising edges of the free-running signal B and the input signal A may not match, but as shown in the figure, the selection unit 106 waits until the phases match. When switching from the free-running signal B to the input mask signal A ', the phases of the two signals are aligned,
Therefore, the phase jump of the PLL reference signal D does not occur.
The input signal A gradually shifts to the mask signal “H” and the input signal A and the free-running signal B are input.
Is not completely frequency synchronized. Thus
The time "T" shown in FIG. 8 until the synchronization is achieved is the time required to actually switch the signal in the selection unit after the synchronization signal is restored.

Example 2. FIG. 9 shows the configuration of the phase locked loop circuit according to another embodiment of the present invention. In the present embodiment, the width of the mask signal shown in FIG. 1 is variable, a setting unit 107 is provided, and the width of the value of the counter for generating the mask signal is set from there. This will increase the flexibility of the circuit. The mask signal is generated by decoding the counter value as shown in FIG. The width of the mask is larger than the jitter amount of the input signal A, and it is necessary to set the value as narrow as possible.
The decode value is variable so that the width of the mask signal can be set based on the measured value of the jitter amount. The configuration of the PLL circuit 200 of FIG. 9 is the same as that of the PLL circuit of FIG.

Example 3. FIG. 10 shows the configuration of a phase locked loop circuit according to another embodiment of the present invention. In this embodiment, an instruction unit 108 for changing the frequency division ratio of the counter unit 102 is added to the circuit of FIG. The instruction unit 108 detects the operation start of the input signal A, and further, the counter 1 is operated under the condition that the SEL signal is “L”.
02, the frequency division ratio is instructed to be changed to N-1. That is, it is detected that the system is waiting for the return, and the period of the free-running signal B is consciously shortened during this period. Thus, when the SEL signal is L, that is, when the input signal A is restored in the self-running state,
The frequency division ratio of the counter section is set to N-1 until it enters the "H" portion of the rising mask signal of the input signal A. As shown in FIG. 11, the rising mask signal “H” of the input signal A is “H”.
When entering the part of, the division ratio of the counter part is returned to N (Fig. 1
(Lower point of 1), when the synchronization state is reached, the counter section is reset based on the rising edge of the input mask signal A ′. With the above configuration, when the input signal A is restored from the interruption, the time "T" shown in FIG. 8 can be shortened, that is, the phase of the free-running signal B can be aligned with the input signal A earlier.

Example 4. FIG. 12 shows the configuration of the phase locked loop circuit according to another embodiment of the present invention. In this embodiment, 109 monitoring units are provided in addition to the circuit of FIG. The operation using the monitoring unit 109 is as follows. When the SEL signal is L, that is, when the input signal A is restored in the self-running state, the monitoring unit 109 monitors the rising position of the input signal A with respect to the self-running signal B. When the phase is advanced as shown in FIG. 13, the frequency division ratio of the reset section is set to N-1, and when the phase is delayed as shown in FIG. 14, it is set to N + 1.
As a result, the phase of the free-running signal B can be aligned with the input signal A faster.

Example 5. In the present embodiment, prior to switching to the input signal A at the time of restoration, the average change speed of the free-running signal B is moderated, and the free-running signal is gradually changed to match the input signal A. . FIG. 15 is a configuration diagram of the phase-locked loop circuit of the present embodiment. In addition to the circuit of FIG. 1, a limiting unit 110 is provided. The operation using the restriction unit 110 is as follows. When the SEL signal is L (self-running state) and the input signal A is restored, the limiting unit 110 restores the counter unit 102.
It limits the number of resets to. That is, the reset is performed once every M times. As a result, the period of the free-running signal B changes gently on average, and the oscillation phase of the PLL circuit at the subsequent stage changes gently in response to this. It is possible to prevent the sync signal from being switched where the phase of the input signal A which has been restored eventually matches the phase, and to prevent the phase of the free-running signal B from abruptly changing.

Example 6. In this embodiment, an example in which the reset limit number M of the above embodiment is made variable will be described. FIG. 16 shows a block diagram of the phase locked loop circuit of the present embodiment. In the figure, 1
A setting unit 11 is an element added to the configuration diagram of FIG. In this configuration, the reset limit number M times in the above embodiment is made variable, setting is possible from the setting unit 111, and the flexibility of the circuit is increased. As a result, the speed with which the phase of the free-running signal B changes can be set arbitrarily. Alternatively, the setting unit 111 may be controlled from the outside and the reset limitation may be applied from the outside.

Example 7. In this embodiment, as another example of the reset restriction, an example will be described in which a prohibition unit that prohibits the reset of the counter unit by receiving the phase difference information of the bit clock of the demodulator is described. By doing so, the self-running state is returned to the synchronization state as soon as possible without causing any trouble in wireless communication. This circuit is effective in wireless communication,
The reset is allowed when the phase correction amount of the recovered clock of the demodulator is sufficiently small during communication with the opposite device.

FIG. 17 shows a block diagram of this embodiment. The configuration shown in the figure includes a prohibition unit 112 that prohibits the reset of the counter unit from the phase difference of the bit clock of the demodulator, instead of the reset limiting circuit 110 of FIG. The input BTR information is information on the phase difference between the bit clocks of the parent device and the child device, which are not shown in the figure, and when the difference is 0, 0 is input as the BTR information. Clock reproduction is performed in order to demodulate received data in wireless communication, but if the phase difference between the reproduced clock and the reference clock is large, correct demodulation cannot be performed.
If the phase of the free-running signal B changes abruptly, this phase difference may increase. Therefore, when this phase difference is large (for example, ± 15 degrees or more), the frequency division ratio of the counter unit 102 should not be changed. The prohibition unit 112 prohibits reset. As a result, the phases of the input signal A and the free-running signal B can be aligned most quickly without adversely affecting the wireless communication.

Example 8. In the present embodiment, the circuit for averaging the phase difference between the bit clocks of the demodulator is used in the above-mentioned embodiment so that the free-running state is returned to the synchronization state as quickly as possible without causing any trouble in the wireless communication. . In this way, by the circuit that calculates the average value of the phase correction amount of the recovered clock for multiple times, it is possible to return from the free-running state to the synchronization state as soon as possible without causing a trouble to the communication radio more accurately. did. FIG. 1 is a configuration diagram of this embodiment.
8 shows. The configuration shown in the figure includes, in addition to the configuration shown in FIG. 17, a calculation unit 113 that averages the phase difference of the bit clocks of the demodulator. The operation of this configuration is the same as that of the above-described embodiment.
The phase difference of the bit clock of the demodulator is counted multiple times and averaged, and resetting is prohibited depending on the magnitude of the average value. Thus, the timing of resetting the counter unit 102 becomes more reliable. That is, the phases of the two signals are matched more accurately with a speed that does not adversely affect the entire apparatus.

[0033]

As described above, according to the present invention, the N frequency divider for obtaining the output signal in phase with the reference signal A, the input detecting means and the switching means are provided, so that the reference signal is disconnected or restored. In the case of switching at the time of, there is an effect that a phase jump is prevented and smooth and stable switching can be performed.

Further, since the N frequency divider indicating the mask timing, the input detecting means, the reset circuit for phase synchronization, and the switching means for switching in accordance with the mask timing are provided, the reference signal A is disconnected or In the case of switching at the time of restoration, there is an effect that phase jump can be prevented and smooth and stable switching can be performed.

Furthermore, since the width of the mask signal can be externally set, the circuit flexibility can be increased.

Furthermore, since the circuit configuration is such that the frequency division ratio of the counter portion is changed when the input signal A is restored from disconnection, the phase of the free-running signal B can be quickly aligned with the input signal A.

Furthermore, since the frequency division ratio value (N-1 / N + 1) of the counter section is selected according to the rising position of the input signal A with respect to the free-running signal B when the input signal A is restored from disconnection. The phase of the free-running signal B is advanced earlier
There is an effect that can be aligned.

Furthermore, since the reset applied to the counter portion when the input signal A is restored from disconnection is prohibited as necessary, there is an effect that the phases of the two signals can be matched at an appropriate speed.

Furthermore, since the reset is allowed when the phase difference between the bit clocks of the demodulator is checked and the amount of phase correction of the reproduced clock is sufficiently small, the speed is such that the entire apparatus is not adversely affected. Has the effect of matching the phases of the two signals.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase locked loop circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the counter of the phase locked loop circuit according to the first embodiment.

FIG. 3 is a diagram illustrating mask signal generation of the counter of FIG.

FIG. 4 is a diagram illustrating the operation of the mask unit in FIG.

5 is a diagram illustrating an operation of the input detection unit of FIG.

FIG. 6 is a diagram illustrating a switching operation of the phase locked loop circuit of FIG. 1 to a free-running signal B.

FIG. 7 is a diagram illustrating a switching operation of the phase locked loop circuit of FIG. 1 to a free-running signal B.

FIG. 8 is a diagram illustrating an operation of switching to the input signal of the phase locked loop circuit of FIG. 1.

FIG. 9 is a diagram showing a configuration of a phase locked loop circuit according to a second embodiment.

FIG. 10 is a diagram showing a configuration of a phase locked loop circuit according to a third embodiment.

FIG. 11 is a diagram illustrating the operation of the phase locked loop circuit according to the third embodiment.

FIG. 12 is a diagram showing a configuration of a phase locked loop circuit according to a fourth embodiment.

FIG. 13 is a diagram for explaining the operation of the phase locked loop circuit according to the fourth embodiment.

FIG. 14 is a diagram for explaining the operation of the phase locked loop circuit according to the fourth embodiment.

FIG. 15 is a diagram showing a configuration of a phase locked loop circuit according to a fifth embodiment.

FIG. 16 is a diagram showing a configuration of a phase locked loop circuit according to a sixth embodiment.

FIG. 17 is a diagram showing a configuration of a phase locked loop circuit according to a seventh embodiment.

FIG. 18 is a diagram showing a configuration of a phase locked loop circuit according to an eighth embodiment.

FIG. 19 is a block diagram showing a configuration of a conventional phase locked loop circuit.

[Explanation of symbols]

101 N-fold original clock oscillator of free-running signal, 102
Counter section, 103 mask section, 104 input detection section,
105 reset circuit, 106 selection unit, 107 mask width setting, 108 instruction unit, 109 monitoring unit, 110
Limiting unit, 111 reset limit number setting unit, 112 prohibiting unit, 113 calculating unit, 200 PLL circuit, 201
Phase comparator, 202 low pass filter, 203 voltage controlled oscillator, 204 phase controlled frequency divider.

Claims (7)

[Claims] 1. A frequency divider for dividing a reference clock by N and generating a free-running signal B in phase with an input signal A which is one of the reference inputs, and a disconnection of the input signal A is detected, Also, input detection means for detecting the phase of the recovery of the input signal A and the phase of the free-running signal B to output a switching signal, and the input signal A, the free-running signal B and the switching output by the switching signal. A phase synchronization circuit comprising switching means for inputting the phase comparison of the phase synchronization circuit and phase control means forming a closed loop for controlling the voltage controlled oscillator by the phase comparison input. 2. A frequency divider that divides a reference clock by N to generate a free-running signal B, outputs a mask signal from the reference clock, and detects disconnection of the input signal A, and also detects the input signal A. Input detection means for outputting a switching signal by detecting the recovery of the signal and the coincidence in the mask signal with the free-running signal B, and reset for outputting the reset signal to the frequency divider in response to the input signal A and the switching signal. A circuit, a switching means for switching and outputting the input signal A and the free-running signal B by the switching signal to be an input for phase comparison of a phase locked loop, and a closed loop for controlling a voltage controlled oscillator by the phase comparison input. A phase synchronization circuit having a phase control means for controlling the phase. 3. The phase locked loop circuit according to claim 2, wherein the frequency divider is configured to variably set a predetermined mask width to output a mask signal. 4. Furthermore, the recovery of the input signal A is monitored,
2. An instruction means for instructing and outputting for a predetermined period of time is provided, a frequency divider is also configured to be variable in frequency division ratio, and the frequency division ratio is changed by the instruction output of the instructing means. The phase synchronization circuit described. 5. Further, a monitor instruction means for monitoring the input signal A and the free-running signal B is provided, and the reset timing of the reset circuit is changed by the instruction output of the monitor instruction means. The phase locked loop circuit according to claim 2. 6. The phase locked loop circuit according to claim 5, further comprising a reset limiting circuit for limiting a reset output to limit the number of resets as necessary. 7. The phase synchronization according to claim 5, further comprising a phase difference reset limiting circuit for limiting the reset output according to the phase difference of the bit clock, and limiting the number of resets as necessary. circuit.