JP4921811B2 - Phase-locked loop circuit and control method used in the phase-locked loop circuit - Google Patents

Description

  The present invention relates to a phase-locked loop circuit that is used in, for example, a broadcasting station for digital broadcasting and phase-synchronizes an external clock signal and an internal clock signal, and a control method used in the phase-locked loop circuit.

  In recent years, digital broadcasting has been started in a terrestrial broadcasting system. In such a digital broadcast system, for example, the construction of an STL (Studio to Transmitter Link) broadcast network that connects a performance place (studio) and a transmission place by microwaves is an issue. In addition, construction of a TTL (Transmitter to Transmitter Link) broadcasting network that connects a transmitting station and a relay station by a microwave is also an issue.

By the way, in the transmitting station or the relay station, a highly stable reference frequency is obtained, and a PLL (Phase Locked Loop) is applied to the control input of the voltage controlled oscillator (VCO) using this reference frequency as a reference, thereby obtaining a highly accurate signal. It is considered to use a PLL circuit that generates a processing frequency signal (for example, Patent Document 1).
JP 2001-274678 A.

  By the way, in the PLL circuit described above, when a disconnection or abnormality occurs in the input reference signal, the reference clock becomes abnormal, and thus the phase between the counter value generated from the reference clock and the counter value generated from the internal clock generated from the VCO. Shifts. In this case, it takes a long time for the reference clock and the internal clock to be phase-synchronized, which may hinder the operation of the apparatus. For this reason, there has been a strong demand for an effective measure that can cope with the interruption or abnormality of the input reference signal.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a phase locked loop circuit capable of coping with an abnormality even when an abnormality occurs in a reference clock, and a control method used in the phase locked loop circuit.

In order to achieve the above object, the present invention is configured as follows.
(1) A phase comparator that compares a reference clock signal generated from an input external clock signal and having a first signal level and a second signal level and an internal clock signal generated from an oscillator and having a first signal level and a second signal level. In the phase-locked loop circuit for controlling the oscillation frequency of the oscillator based on the phase comparison result and phase-synchronizing the reference clock signal and the internal clock signal, the reference clock signal is 1 / m (m is A first frequency dividing means for dividing the internal clock signal to 1 / n (where n is a natural number) and a second frequency divider. A second frequency dividing means for generating a frequency signal and supplying it to the phase comparator; a holding means for temporarily holding a control signal input to the oscillator; and an output of the first and second frequency dividing means; In this comparison result Is obtained as a control means for inputting a control signal to the oscillator from the holding means Zui.

  According to the configuration of (1), the reference clock signal is divided by 1 / m to generate the first divided signal, and the internal clock signal is divided by 1 / n to obtain the second divided signal. Before the control signal corresponding to the phase comparison result between the first divided signal and the second divided signal is supplied to the oscillator, the control signal is held in the holding unit. The control signal is read from the holding unit and supplied to the oscillator only when the phase shift between the first frequency-divided signal and the second frequency-divided signal is within the allowable range from the phase comparison result again.

  Therefore, even if an abnormality occurs in the reference external clock signal, the phase difference between the external clock signal and the internal clock signal can be held within an allowable range within a short time and in a simple procedure. It becomes possible to always operate the phase locked loop circuit stably.

  (2) Further, a window generation for generating a window signal in which the period of the second signal level is a period corresponding to approximately 2n clock length or more and n / 2 or less from the second frequency-divided signal and supplies the window signal to the phase comparator Means for changing the first signal level from the first signal level to the second signal level or the change point from the second signal level to the first signal level is the second signal level of the window signal. It is determined whether or not it is within the period, and if it is determined that the predetermined number of times is not entered, the first frequency dividing means is reset so that the changing point enters the second signal level period of the window signal. It is characterized by controlling.

  According to the configuration of (2), by generating a window signal necessary for detecting an abnormality of the external clock signal from the second divided signal and comparing the first divided signal and the window signal, It is determined whether or not the changing point of the first frequency-divided signal from the first signal level to the second signal level falls within the second signal level period of the window signal. Then, the first frequency divider is reset so that the change point of the first frequency-divided signal falls within the second signal level period of the window signal when the predetermined number of times has not been entered.

  Therefore, even if an abnormality occurs in the reference external clock signal, the phase difference between the external clock signal and the internal clock signal can be held within one clock within a short time, thereby enabling the phase locked loop circuit to be It becomes possible to always operate stably.

(3) It further comprises input switching means for selectively inputting the reference clock signal and the spare reference clock signal for the reference clock signal to the first frequency dividing means, and the control means changes the first frequency divided signal. When it is determined that the point does not fall within the second signal level period of the window signal, the input switching means is controlled to input the spare reference clock signal to the first frequency dividing means according to a predetermined condition. It is characterized by doing. Note that the number of times that the changing point of the first frequency-divided signal has entered the second signal level period of the window signal is used to determine the predetermined condition.
According to the configuration of (3), after the suspension of the supply of the control signal to the oscillator is canceled, when an abnormality occurs in the reference clock signal, it is possible to cope with the abnormality of the external clock signal by switching to the standby reference clock signal. can do.

  As described above in detail, according to the present invention, it is possible to provide a phase-locked loop circuit capable of coping with the abnormality even when an abnormality occurs in the reference clock, and a control method used in the phase-locked loop circuit. .

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a configuration of a phase locked loop circuit as a first embodiment of the present invention. This phase-locked loop circuit is used, for example, in a broadcasting device that processes a program information signal of digital broadcasting.

  The external clock signal is input to the PLD circuit 11A and phase-compared with the internal clock signal output from the voltage controlled crystal oscillator 12. A control signal corresponding to the phase comparison result is supplied to the loop filter 14. Then, it is converted into a control voltage of the voltage controlled crystal oscillator 12 by the loop filter 14 and temporarily held in the sample hold circuit 15. The control voltage output from the sample hold circuit 15 is supplied to the voltage controlled crystal oscillator 12.

  Further, the PLD circuit 11A includes counters 111 and 112, a phase comparison unit 113, a control unit 114, and an input switch 115.

  That is, the external clock signal is input to the counter 111 and counted by 1 / m (m is a natural number), thereby generating a first rectangular wave signal having a high level and a low level. The internal clock signal is input to the counter 112 and counted by 1 / n (n is a natural number), thereby generating a second rectangular wave signal different from the first rectangular wave signal. These first and second rectangular wave signals are supplied to the phase comparison unit 113 and the control unit 114.

The control unit 114 compares the first and second rectangular wave signals, and from (1 / m ) to (1 / m ) of the first rectangular wave signal (1 / m counter value) as shown in FIG. ) +1 is confirmed by confirming that the changing point is between (1 / n) and (1 / n) +1 of the second rectangular wave signal (1 / n counter value). It is determined whether or not is locked. Here, if the change point falls between (1 / n) and (1 / n) +1 of the second rectangular wave signal, the control voltage held in the sample hold circuit 15 is read out and the voltage The sample hold circuit 15 is controlled so that the control voltage held in the sample hold circuit 15 is held as it is unless it is input, and the counters 111 and 112 are controlled. To do.

Here, when the control unit 114 performs the counter control, the phase comparison unit 113 uses the first rectangular wave signal ( (1 / m) counter value) and the second rectangular wave signal ( (1 / n) counter value). When a certain difference is detected, the second rectangular wave signal ( (1 / n) counter value) is changed to the first rectangular wave signal ( (1 / m) counter value) after a predetermined time has elapsed. The counters 111 and 112 are corrected and controlled so that the phases match.

When the control unit 114 controls the sample and hold circuit 15, the phase comparison unit 113 uses the first rectangular wave signal ( (1 / m) counter value) and the second rectangular wave signal ( (1 / n)). When a certain difference from the counter value is detected, the sample hold circuit 15 is controlled to hold the current state. After a certain time has elapsed, the counters 111 and 112 are set so that the second rectangular wave signal ( (1 / n) counter value) is in phase with the first rectangular wave signal ( (1 / m) counter value). Simultaneously with the correction control, the sample hold circuit 15 is returned from the held state to the normal state.

  An input switch 115 is connected to the input terminal of the counter 111. The input switch 115 derives one of the n external clock signals S1 to Sn to the counter 111. The input switch 115 is controlled to be switched by the control unit 114.

As described above, in the first embodiment, the external clock signal is counted (1 / m) by the counter 111 to generate the first rectangular wave signal, and the internal clock signal is generated by the counter 112 (1 / n) Count and generate a second rectangular wave signal, and supply the control signal corresponding to the phase comparison result between the first and second rectangular wave signals to the voltage controlled crystal oscillator 12 before the control signal Is held in the sample hold circuit 15. Then, the control voltage is supplied from the sample hold circuit 15 to the voltage controlled crystal oscillator 12 only when the phase shift between the first rectangular wave signal and the second rectangular wave signal is within the allowable range in the control unit 114. I am doing so.

  Therefore, even if an abnormality occurs in the reference external clock signal, the phase difference between the external clock signal and the internal clock signal can be held within an allowable range within a short time and in a simple procedure. It becomes possible to always operate the phase locked loop circuit stably.

(Second Embodiment)
FIG. 3 is a block diagram showing a configuration of a phase-locked loop circuit as a second embodiment of the present invention.

  The external clock signal is input to the PLD circuit 11B and phase-compared with the internal clock signal output from the voltage controlled crystal oscillator 12. A control signal corresponding to the phase comparison result is supplied to the sample hold circuit 15 via the switch 13. The control voltage of the voltage controlled crystal oscillator 12 held in the sample and hold circuit 15 is supplied to the voltage controlled crystal oscillator 12. The switch 13 is ON / OFF controlled by the PLD circuit 11B. Thus, the control voltage supplied to the voltage controlled crystal oscillator 12 is obtained by integrating the low level and the high level of the external clock signal cut out by the window generated from the internal clock signal. The integration process is performed by a charge pump.

FIG. 4 is a block diagram showing a specific configuration of the PLD circuit 11B.
The PLD circuit 11B includes counters 111 and 112-2, a phase comparison unit 113, and an abnormality determination control unit 114-2. That is, the external clock signal is input to the counter 111 and counted, thereby generating a rectangular wave signal having a high signal level and a low signal level. The internal clock signal is input to the counter 112-2 and counted, thereby generating a window signal indicating a high level around one clock (counter value 0 to 2) of the rising edge of the rectangular wave signal. These rectangular wave signal and window signal are supplied to the phase comparison unit 113 and the abnormality determination control unit 114-2.

  The phase comparator 113 compares the phases of both input signals to detect a phase difference and outputs this phase difference as a control signal. The abnormality determination control unit 114-2 determines whether or not the rising edge of the rectangular wave signal is within the high level period of the window signal by comparing the rectangular wave signal and the window signal. When it is determined that the signal does not enter, the counter 111 is controlled so that the rising edge of the rectangular wave signal falls within the high level period of the window signal, and the on / off of the switch 13 is controlled.

Next, the operation in the above configuration will be described.
First, an internal clock signal of (512/63) MHz is generated from an external clock signal of 10 MHz as shown in FIG. In this case, 10 MHz is divided by 315, (512/63) MHz is divided by 256, and a counter 111 having the same period is prepared. Then, as shown in FIG. 5A, a counter 112-2 is prepared that generates a window signal that is opened only during a period in which the counter value of the internal clock signal is 0-2. The PLL is realized by comparing the rising phase of the rectangular wave signal only during the high level period of the window signal.

  As shown in FIG. 6, when an abnormality occurs in the external clock signal, the rising edge of the rectangular wave signal cannot be detected during the high level period of the window signal. At this time, with reference to the high level period of the window signal, the external reference clock counter 111 is corrected so that the rising edge of the rectangular wave signal is at the center of the high level period of the window signal, and on / off of the switch 13 is controlled. To do.

  Thereby, the counter phase difference of the external reference clock can be adjusted within one clock of the external reference clock.

  As described above, in the second embodiment, the counter 111 generates a rectangular wave signal synchronized with the internal clock signal from the external clock signal, and the counter 112-2 detects abnormality of the external clock signal from the internal clock signal. A window signal necessary for detection is generated, and the abnormality determination control unit 114-2 determines whether or not the rising edge of the rectangular wave signal is within the high level period of the window signal. The counter 111 is controlled so that the rising edge of the rectangular wave signal falls within the high level period of the window signal, and on / off of the switch 13 is controlled.

  Therefore, even if an abnormality occurs in the reference external clock signal, the phase difference between the external clock signal and the internal clock signal can be held within one clock within a short time, thereby enabling the phase locked loop circuit to be It can always be operated stably.

(Third embodiment)
FIG. 7 is a block diagram showing a configuration of a phase-locked loop circuit as a third embodiment of the present invention.
That is, two external clock signals S1 and S2 are input to the PLD circuit 11C.

  FIG. 8 is a block diagram showing a specific configuration of the PLD circuit 11C. In FIG. 8, the same parts as those in FIG.

An input switch 115 is connected to the input terminal of the counter 111. The input switch 115 derives one of the two external clock signals S1 and S2 to the counter 111.
Each output of the counters 111 and 112-2 is supplied to the phase comparison unit 113 and also supplied to the abnormality determination unit 116. The abnormality determination unit 116 determines whether the rising edge of the rectangular wave signal is within the high level period of the window signal by comparing the rectangular wave signal with the window signal. This determination result is supplied to the switch control unit 117 and the switching control unit 118.

  Based on the determination result, the switch control unit 117 determines whether the number of times that the rising edge of the rectangular wave signal has entered the high level period of the window signal is N (N is a natural number) or more in T seconds, and N times Only when this is the case, the switch 13 is controlled to be turned on.

  The switching control unit 118 controls the counter 111 so that the rising edge of the rectangular wave signal falls within the high level period of the window signal and determines that the switch 13 is turned on when it is determined not to enter from the determination result. When the rising edge of the rectangular wave signal does not fall within the high level period of the window signal, for example, the input switcher switches from the state in which the external clock signal S1 is input to the counter 111 to the state in which the external clock signal S2 is input to the counter 111. 115 is switched.

Next, the processing operation of the above configuration will be described below.
FIG. 9 is a flowchart illustrating a series of processing operations of the abnormality determination unit 116, the switch control unit 117, and the switching control unit 118.

  First, it is assumed that a timer (not shown) of the switch control unit 117 is activated at the time of activation, and the external clock signal S1 is input to the counter 111.

  Based on the determination result from the abnormality determination unit 116, the switch control unit 117 determines whether the rising edge of the rectangular wave signal is within the high level period of the window signal (step ST8a), and the high level period of the window signal If it is within (Yes), +1 is counted, and it is determined whether or not the counter value is N times (step ST8b), and the processing of step ST8a and step ST8b is repeatedly executed until N times. .

  Here, when it has become N times (Yes), the switch control unit 117 determines whether or not the timer has reached T seconds (step ST8c), and when it is within T seconds (No), the switch 13 is turned on. The abnormality detection mask is released by switching to the ON state (step ST8d).

  Subsequently, the switching control unit 118 determines whether or not the rising edge of the rectangular wave signal is within the high level period of the window signal based on the determination result from the abnormality determination unit 116 (step ST8e). If it is not within the high level period (No), the counter 111 is corrected so that the rising edge of the rectangular wave signal enters the high level period of the window signal (step ST8f), and the rising edge of the rectangular wave signal is again the window signal. It is determined whether or not it is within the high level period (step ST8g).

  When the window signal is not within the high level period (No), the switching control unit 118 controls the input switch 115 to input the external clock signal S2 to the counter 111, and corrects the counter 111. After that (step ST8h), the process proceeds to step ST8e.

  Further, in step ST8c, if T seconds are exceeded (Yes), the switch control unit 117 determines whether or not the abnormality detection mask has been released (step ST8i), and the abnormality detection mask is released. If it has been completed (Yes), the process proceeds to the normal startup operation continuation process, that is, the process of Steps ST8e to ST8h (Step ST8j). If the abnormality detection mask has not been released (No), the known startup abnormality switching process is performed. Transition (step ST8k).

  As described above, in the third embodiment, in the switch control unit 117, the number of times that the rising of the rectangular wave signal enters the high level period of the window signal within T seconds is N times or more, that is, the external clock signal S1 is The switch 13 is maintained in the off state until it is confirmed to be normal.

  Therefore, prior to the phase comparison process between the external clock signal S1 and the internal clock signal, it is possible to confirm whether or not the external clock signal S1 is abnormal, and thus there is a risk that the abnormality of the external clock signal S1 will spread to the entire circuit. Can be prevented.

  In the third embodiment, when the switch 13 is switched on by the switch control unit 117 and an abnormality occurs in the external clock signal S1, the switching control unit 118 outputs the external clock signal S2. Since the input switch 115 is controlled to be input to the counter 111, it is possible to cope with an abnormality in the external clock signal S1.

(Other embodiments)
The present invention is not limited to the above embodiments. For example, in the second embodiment, when the number of times that the rising edge of the rectangular wave signal does not enter the high level period of the window signal is N or more with the switch 13 turned on, the switch 13 is turned off. You may make it set to.

  In the third embodiment, when the number of times the rising of the rectangular wave signal has entered the high level period of the window signal is N times or more, the switch 13 is set to the on state, and then the external clock The signals S1 and S2 are switched. When the number of times that the rising edge of the rectangular wave signal does not enter the high level period of the window signal at the time of activation is a plurality of times, it is determined that the external clock signal is abnormal, The external clock signal may be switched.

  In the third embodiment, the abnormality determination unit 116, the switch control unit 117, and the switching control unit 118 have been described as hardware configurations. However, the abnormality determination unit 116, the switch control unit 117, and the switching control unit 118 are combined into one unit. You may make it implement | achieve with a microcomputer.

  Further, in the second embodiment, in order to obtain a control voltage to be supplied to the voltage controlled crystal oscillator 12, the low level and high level integration processing of the external clock signal cut out by the window generated from the internal clock signal is charged. Although the example performed by the pump has been described, it may be performed by a filter other than the charge pump.

  Furthermore, although each said embodiment is a case where it applies to a broadcast apparatus, it is not limited to this, Of course, it can apply also about the correction | amendment of phase synchronization in the electronic circuit of another digital communication system. It is.

1 is a block diagram showing a configuration of a phase-locked loop circuit as a first embodiment of the present invention. The timing waveform figure of the 1st and 2nd rectangular wave signal produced | generated by each counter of the PLD circuit in the said 1st Embodiment. The block diagram which shows the structure of the phase-locked loop circuit as 2nd Embodiment of this invention. FIG. 4 is a block diagram showing a specific configuration of the PLD circuit shown in FIG. 3. FIG. 9 is a timing waveform diagram of a rectangular wave signal and a window signal generated by each counter of the PLD circuit in the second embodiment. The figure shown in order to demonstrate a mode when abnormality generate | occur | produces in the external clock signal in the said 2nd Embodiment. The block diagram which shows the structure of the phase-locked loop circuit as 3rd Embodiment of this invention. FIG. 8 is a block diagram showing a specific configuration of the PLD circuit shown in FIG. 7. The flowchart which shows the control procedure and control content of the phase locked loop circuit in the said 3rd Embodiment.

Explanation of symbols

  11A, 11B, 11C ... PLD circuit, 12 ... voltage controlled crystal oscillator, 13 ... switch, 14 ... loop filter, 15 ... sample hold circuit, 111,112,112-2 ... counter, 113 ... phase comparator, 114 ... control , 114-2... Abnormality determination control unit, 115... Input switch, 116... Abnormality determination unit, 117.

Claims (8)

The reference clock signal generated from the input external clock signal and having the first signal level and the second signal level and the internal clock signal generated from the oscillator and having the first signal level and the second signal level are phase-shifted by the phase comparator. In the phase-locked loop circuit for controlling the oscillation frequency of the oscillator based on the phase comparison result and synchronizing the phase of the reference clock signal and the internal clock signal,
The reference clock signal 1 / m (m is a natural number) and frequency dividing means you supplied to the phase comparator to generate a dividing division signal,
A window signal in which the internal clock signal is divided by 1 / n (n is a natural number) and the period of the second signal level is a period corresponding to any one of approximately 2 clock lengths or more and n / 2 or less. Window generating means for generating and supplying to the phase comparator;
Holding means for temporarily holding a control signal input to the oscillator;
Control means for comparing the output of the frequency dividing means and the output of the window generating means, and inputting a control signal from the holding means to the oscillator based on the comparison result;
And an input switching means for inputting selectively before Symbol dividing unit and a spare reference clock signal with respect to the reference clock signal and the reference clock signal,
The control means is configured such that the changing point of the divided signal from the first signal level to the second signal level or the changing point from the second signal level to the first signal level is within the second signal level period of the window signal. If it is determined whether or not to enter, if it is determined that it does not enter more than a predetermined number of times, the frequency dividing means is reset and the change point is controlled to fall within the second signal level period of the window signal, After controlling the frequency dividing means, the changing point of the divided signal from the first signal level to the second signal level or the changing point from the second signal level to the first signal level is the second signal of the window signal. if not within level period, according to a predetermined condition, the phase locked loop circuit, characterized by switch controlling the input switching means to enter a reference clock signal for the preliminary prior Symbol dividing unit Wherein said control means includes a feature to perform the control of the first signal level and the oscillator by a control signal proportional to the second signal level of the time before Symbol divided signal in said second signal level period of said window signal The phase-locked loop circuit according to claim 1. The control means according to claim 1, characterized by using the number in the determination of a predetermined condition, the change point of the previous SL-divided signal did not enter consecutively in the second signal level period of said window signal The phase-locked loop circuit described.   2. The phase-locked loop circuit according to claim 1, wherein the phase-locked loop circuit is used in a digital broadcast program processing apparatus that processes a digital broadcast program information signal and is used in the processing of the digital broadcast program processing apparatus.   2. The phase synchronization according to claim 1, wherein the control means is obtained by integrating a first signal level and a second signal level of the divided signal obtained by cutting out a control signal input to the oscillator by the window signal. Loop circuit. Wherein said control means includes a phase locked loop circuit according to claim 5, characterized in that the first signal level and a second signal-level integration before Symbol divided signal cut out in the previous Kiu guiding signal filter. Wherein said control means includes a phase locked loop circuit of claim 5, wherein performing the first integration signal level and a second signal level before Symbol divided signal cut out in the previous Kiu guiding signals in the charge pump. The reference clock signal generated from the input external clock signal and having the first signal level and the second signal level and the internal clock signal generated from the oscillator and having the first signal level and the second signal level are phase-shifted by the phase comparator. In the control method used in the phase-locked loop circuit for controlling the oscillation frequency of the oscillator based on the phase comparison result to synchronize the phase of the reference clock signal and the internal clock signal,
1 / m of the reference clock signal by frequency dividing means (m is a natural number) is supplied to the phase comparator to generate a dividing division signal,
1 / n of the internal clock signal by window producing formation means (n is a natural number) by dividing the equivalent to the period of the second signal level is one of approximately 2 or more clock length and n / 2 or less Generate a window signal to be a period and supply it to the phase comparator,
A control signal input to the oscillator is temporarily held in a holding unit,
Input to selectively pre Symbol dividing unit and a spare reference clock signal with respect to the reference clock signal and the reference clock signal at input switching means,
Pre Symbol divided signal and compare the ratio of said window signal, the control signal from the holding unit on the basis of the comparison result input to said oscillator, from the first signal level before Symbol divided signal to the second signal level It is determined whether or not the changing point or the changing point from the second signal level to the first signal level is within the second signal level period of the window signal. as change point to reset the pre-Symbol dividing unit is controlled to fall within the second signal level period of the window signal, after controlling the division means, first signal level of the frequency division signal When the change point from the second signal level to the second signal level or the change point from the second signal level to the first signal level does not fall within the second signal level period of the window signal , the spare signal is changed according to a predetermined condition. Standard Tsu control method for use in a phase locked loop circuit being characterized in that so as to switch control the input switching means to enter before Symbol dividing means click signal.

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