JP2010130638A - Clock hitless switching apparatus and its operation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide clock hitless switching apparatus and an operation method capable of making a phase difference at system switching coincident at high precision. <P>SOLUTION: A clock hitless switching apparatus 100 compares a frequency division signal 110 of a standby system with an output frequency division signal 120 higher by integer times of the clock thereof to determine a phase difference value 126, and at system switching, a phase difference frequency division counter value 124 of the standby system is shifted by a phase difference value 126, thereby allowing a phase of an output frequency division signal 120 after switching to be coincident with a phase before switching at high precision. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a transmission apparatus that transmits and receives an information signal such as a video signal via a communication line such as the Internet, and more particularly to a clock uninterruptible switching apparatus that switches two clocks in redundant transmission without instantaneous interruption and an operation method thereof. Is.

  2. Description of the Related Art Conventionally, in an information signal transmission apparatus such as a video signal for a high-definition television, a method of selecting either one by switching between two active and standby input clocks is generally used for redundant transmission. It is done. In such a transmission apparatus, when the clock is switched from the active system to the standby system, switching without interruption is required to improve reliability. At this time, it is important to match the phases of both clocks.

Patent Document 1 discloses an example in which the working clock side resets the standby clock divider to match the clock phases of the working system and the standby system. Patent Document 2 discloses an example in which the working system and the standby system are synchronized. An example is disclosed in which a delay circuit that gives a plurality of phase delays to either one of the systems and a clock phase with the smallest phase difference is selected to match the clock phases of the active system and the standby system.
JP-A-8-223085 Japanese Patent Laid-Open No. 10-240375

  In the conventional clock switching device, when there is a phase difference between the clocks of the active system and the standby system, even if the phases are adjusted by resetting the standby clock divider with the active system clock, at least the clock 1 A phase difference of less than one cycle remains. If a large number of phase delay circuits are prepared, it is possible to increase the accuracy of phase alignment, but there is a limit in terms of hardware configuration and cost, and eventually a phase difference remains.

In any case, voltage crystal oscillator (VCXO: Voltage Controlled)
There was a problem that the output clock from the Crystal Oscillator was disturbed.

  An object of the present invention is to provide a clock uninterruptible switching device and method that can eliminate the above-described drawbacks of the prior art and can match the phase difference at the time of system switching with high accuracy.

  According to the present invention, in order to solve the above-described problem, a clock non-interruptible switching device that switches between two clocks in redundant transmission without instantaneous interruption is a clock supply unit that outputs two clocks having a phase difference. The first frequency dividing counter means for outputting the first frequency dividing counter value from the two clocks, respectively, and the first frequency dividing counter value is divided by 1 / N (where N is a natural number). ), First counter decoding means for outputting a divided signal, selection means for selecting one of the divided signals from the two divided signals, the selected divided signal, and feedback from the output. A phase comparison unit that compares the phase of the output frequency division signal and outputs a phase difference corresponding voltage corresponding to the phase difference, a filtering unit that filters the phase difference corresponding voltage and outputs a control voltage, and a control voltage Clock generating means that controls the wave number and outputs a frequency control clock that is α times the input clock (where α is a natural number), and a clock that divides this frequency control clock by 1 / α and outputs the output clock Output means, second frequency dividing counter means for outputting a second frequency dividing counter value from the frequency control clock, and frequency dividing the second frequency dividing counter value to 1 / (N × α), The frequency control clock is used to temporarily store the signal and output the second counter decoding means to output, the phase difference between one of the two first frequency division counter values and the second frequency division counter value. Phase difference detection means for detecting a phase difference value with a frequency accuracy of α times, and a phase matching means for adding and subtracting the temporarily stored output frequency division signal with the phase difference value when the system is switched to match the phases. Including It is characterized in.

  In addition, the operation method of the clock non-interruptible switching for switching the two clocks in the redundant transmission without instantaneous interruption is a clock supply process for outputting two clocks having a phase difference, and the first clock from each of the two clocks. A first frequency division counter step for outputting a frequency division counter value, a first frequency division signal value for dividing the first frequency division counter value by 1 / N (where N is a natural number), and a first frequency division signal for outputting a frequency division signal. The counter decoding step, the selection step of selecting one of the two divided signals, and the phase of the selected divided signal and the output divided signal fed back from the output are compared. A phase comparison step for outputting a phase difference-corresponding voltage corresponding to the phase difference, a filtering step for filtering the phase difference-corresponding voltage and outputting a control voltage, and controlling the frequency using the control voltage, A clock generation step that outputs a frequency control clock that is α times the clock (where α is a natural number), a clock output step that divides the frequency control clock by 1 / α and outputs an output clock, and a frequency control clock A second output frequency division counter process for outputting the second frequency division counter value, the second frequency division counter value is divided by 1 / (N × α), and the output frequency division signal is temporarily stored. At the same time, the phase difference between the second counter decoding step to be output and one of the two first frequency division counter values and the second frequency division counter value is obtained with a frequency accuracy of α times using the frequency control clock. A phase difference detecting step for detecting the phase difference value, and a phase matching step for adding and subtracting the output frequency-divided signal temporarily stored at the time of system switching to match the phase. To do.

  Next, with reference to the accompanying drawings, an embodiment of a clock uninterruptible switching device according to the present invention will be described in detail.

  FIG. 1 shows a configuration of a clock non-interruptible switching device 100 in an output signal from an HD-SDI (High Definition Serial Digital Interface) processing unit of a high definition television (HDTV).

  In this embodiment, when switching between the active clock (system 0 clock) having a phase difference and the standby clock (system 1 clock) output from the redundant HD-SDI processing unit, the output clock from the VCXO This shows how to perform disruptive switching with minimal disruption.

  The clock supply unit 12 outputs two clocks having a phase difference, a 0-system clock 102 and a 1-system clock 104, and sends them to the frequency dividing counters 14 and 18, respectively.

  The frequency division counters 14 and 18 are counters for frequency-dividing the 0-system clock 102 and the 1-system clock 104 sent from the clock supply unit 12. The frequency-dividing counter values 122 and 124 are respectively represented by counter decoders (DEC: Decoder). ) Sent to 16 and 20, and sent to the phase difference detection circuit 36.

  The counter decoders 16 and 20 respectively divide the 0-system clock and the 1-system clock from the frequency-divided counter values 122 and 124 sent from the frequency-dividing counters 14 and 18 to 1 / N (N: a desired natural value), The 0-system frequency division signal 106 and the 1-system frequency division signal 108 are sent to the selector 22.

  The selector 22 selects either the 0-system divided signal 106 or the 1-system divided signal 108 sent from the counter decoders 16 and 20, and sends the selected divided signal 110 to the phase comparison circuit 24. Further, when system switching occurs, a selection signal 128 is received from the outside.

  The phase comparison circuit 24 uses the frequency division signal 110 sent from the selector 22 as a reference, compares the phase with the output frequency division signal 120 sent from the output counter decoder 34 as a subordinate, and compares the phase difference corresponding voltage 111 corresponding to the phase difference. Is sent to the filter circuit 26.

  The filter circuit 26 filters the phase difference corresponding voltage 111 sent from the phase comparison circuit 24 to obtain a VCXO control voltage 112 and sends it to the voltage controlled crystal oscillator (VCXO) 28.

  The VCXO 28 controls the frequency by the VCXO control voltage 112 sent from the filter circuit 26 and outputs a frequency control clock 114 having a frequency accuracy that is α times (a desired natural number times) the input clock and is 1 / α minutes. Send to circuit 30. Further, the frequency control clock 114 is sent to the VCXO frequency division counter 32 and the phase difference detection circuit 36.

  The 1 / α divider circuit 30 divides the frequency control clock 114 sent from the VCXO 28 by α times the frequency accuracy by 1 / α, and finally outputs the output clock 116 having the same clock frequency as the selected divided signal 110. Is output.

  The VCXO division counter 32 is a counter for dividing the frequency control clock 114 sent from the VCXO 28, and sends the VCXO division counter value 118 to the output counter decoder 34 and the phase difference detection circuit 36.

  The output counter decoder 34 divides the VCXO division counter value 118 sent from the VCXO division counter 32 into 1 / (N × α), and sends it to the phase comparison circuit 24 as an output division signal 120.

  In addition, when the switching of the system is generated from the outside by the selection signal 128, the output counter decoder 34 stores the output frequency dividing signal 120 (decoded value) before the switching is generated, and the phase difference value sent from the phase difference detection circuit 36. Addition / subtraction is performed at 126, and an output frequency-divided signal 120 whose phase matches the frequency-divided signal after switching is generated.

  The phase difference detection circuit 36 includes one of the frequency division counter value 122 sent from the frequency division counter 14 or the frequency division counter value 124 sent from the frequency division counter 18, and the VCXO frequency division counter value sent from the VCXO frequency division counter 32. The phase difference from 118 is detected as a phase difference value 126 having a frequency accuracy of α times using the frequency control clock 114 sent from the VCXO 28 and sent to the output counter decoder 34.

  Next, an operation method of the clock uninterruptible switching device 100 in the present embodiment will be described.

  First, the operation when the clock system switching has not occurred will be described.

  A 0-system clock 102 and a 1-system clock 104 having a phase difference are output from the clock supply unit 12, the 0-system clock 102 is input to the frequency dividing counter 14, and a frequency dividing counter value 122 is output. This frequency division counter value 122 is decoded by the counter decoder 16 and divided by 1 / N to become a frequency division signal 106. Similarly, the 1-system clock 104 is input to the frequency dividing counter 18 and a counter value 124 is output. The counter value 124 is decoded by the counter decoder 20 and divided to 1 / N to become a frequency divided signal 108.

  These frequency-divided signals 106 and 108 are sent to the selector 22, one of which is selected as the frequency-divided signal 110 and sent to the phase comparison circuit 24.

  The phase comparison circuit 24 uses the selected divided signal 110 as the reference side, and uses the output divided signal 120 divided based on the frequency control clock output from the VCXO 28 as the subordinate side, so that the phases of both are the same. The phase difference corresponding voltage 111 corresponding to the phase difference is output and sent to the filter circuit 26 and the VCXO control voltage 112 is sent to the VCXO 28.

  The VCXO 28 is set in advance to output a clock that is α times the input clock (a desired natural number), and the frequency control clock 114 having a frequency accuracy that is α times that of the clock supplied from the clock supply unit 12. Is output.

  The frequency control clock 114 having a frequency accuracy of α times is input to the VCXO frequency dividing counter 32, and the VCXO frequency dividing counter value 118 is output and sent to the output counter decoder.

  The output counter decoder 34 divides the VCXO frequency division counter value 118 sent to 1 / (N × α) to become an output frequency division signal 120.

  The output frequency division signal 120 is sent to the phase comparison circuit 24 as a subordinate side, and phase comparison is performed with the frequency division signal 110 on the reference side sent from the selector 22.

  In this way, the frequency control clock 114 is frequency-divided, and the finally selected output clock 116 is output from the 1 / α frequency dividing circuit 30.

  Next, a case where the clock is switched will be described. The system selected here is called the active system, and the system not selected is called the standby system.

  In the phase difference detection circuit 36, the counter value of the standby system among the two frequency division counters sent from the two clocks, that is, the 1 system when the 0 system clock is the active system and the 1 system clock is the standby system When the 1-system clock is the working system and the 0-system clock is the standby system, the 0-system division counter value 122 is compared with the VCXO division counter value 118.

  Here, when switching from the active system to the standby system occurs due to the selection signal 128 from the outside, the output counter decoder 34 adds the phase difference detection circuit 36 to the frequency-dividing counter 124 (decoded value) before the occurrence of switching stored in advance. By adding / subtracting the phase difference value 126 from the output, the output frequency division signal 120 whose phase matches the frequency division signal of the standby system after switching is created.

  Since the phase difference value 126 is obtained from the clock 114 having a frequency accuracy of α times, it is possible to match the phases with higher accuracy as the multiple becomes larger.

  Further, as shown in FIG. 2, when the 0 system clock is the active system and the 1 system clock is the standby system, the 1 system frequency dividing counter 18 is reset by the reset signal 130 from the 0 system counter decoder 16. If the 1-system clock is the active system and the 0-system clock is the standby system, the 0-system frequency division counter 14 is reset by the reset signal 132 from the 1-system counter decoder 20 in advance. The phase difference between the divided counter values 122 and 124 and the phase difference between the divided signals 106 and 108 of both systems may be used within one cycle of the supplied clock.

  The above operation will be specifically described with reference to the time chart of FIG. Here, α is 4, that is, the VCXO clock is four times the frequency of the supplied clock, the 0 system clock is the working system clock, and the 1 system clock is the spare clock.

  In a state before the clock is switched, the rising of the active frequency dividing signal 106 when the active frequency dividing counter 122 decodes “0” and the VCXO frequency dividing counter value 118 is “0” to “3”. The rising edge of the VCXO output frequency dividing signal 120 when the signal is decoded coincides with that of the active clock 102 and the phase of the VCXO clock 114 coincides.

  Next, the standby frequency dividing counter 124 counted by the standby clock 104 whose phase does not match the working clock has a phase difference with the VCXO frequency dividing counter 118, and the phase difference value 126 is obtained. Specifically, as in the case of the active system frequency dividing counter 122, when the standby system frequency dividing counter 124 decodes “0”, the standby system frequency dividing signal 108 rises, and the VCXO frequency dividing counter 118 sets “0”. The phase difference value 126 from the rising edge of the VCXO output divided signal 120 when “3” to “3” is decoded is “6” with the accuracy of the VCXO clock 114.

  When the clock switching is performed, the VCXO output frequency division signal 120 is shifted by 6 clocks, which is the phase difference value 126, using the VCXO clock 114 in the output counter decoder 34, whereby “6” to “6” of the VCXO frequency division counter 118. 9 ".

  As a result, the phase of the standby frequency division signal 108 can be made to match the phase before the switching with the accuracy within one cycle of the VCXO clock 114 and the VCXO frequency division signal after the clock switching.

  In this embodiment, an HDTV signal is shown as an example, but SDTV (Standard Definition Television) can be applied regardless of the frequency domain. In addition, it is clear that the phase accuracy improves as the magnification of the VCXO with respect to the supplied clock increases, but the present invention can be applied if it is twice or more.

  Thus, according to the present invention, when switching between two clocks having a phase difference in the clock uninterruptible switching device, the clock frequency on the dependent side of the phase comparison circuit is set to be an integer multiple higher than the supplied clock. The standby frequency division counter value is compared with the subordinate frequency division counter to obtain the phase difference value. When a system switchover occurs, the decode value of the subordinate frequency division counter is shifted by the phase difference value. By making the phase of the frequency-divided signal after switching coincide with each other with high accuracy, it is possible to prevent clock disturbance occurring at the time of switching.

  Further, since processing can be performed by simple phase comparison, the scale of the circuit can be reduced without increasing the amount of hardware for increasing accuracy.

It is a block which shows the structure of the clock uninterruptible switching apparatus by the Example of this invention. It is a figure of description of the clock uninterruptible switching device by other Example of this invention. It is a time chart explaining operation | movement of the clock uninterruptible switching device by the Example of this invention.

Explanation of symbols

100 clock uninterruptible switching device
12 Clock supply section
14,18 Divider counter
16,20 counter decoder
22 Selector
24 Phase comparison circuit
26 Filter circuit
28 Voltage controlled crystal oscillator (VCXO)
30 1 / α divider circuit
32 VCXO divider counter
34 Output counter decoder
36 Phase difference detection circuit

Claims (4)

In a clock uninterruptible switching device that switches two systems of clocks in redundant transmission without instantaneous disconnection, the device includes:
Clock supply means for outputting two systems of clocks having a phase difference;
First frequency division counter means for outputting a first frequency division counter value from each of the two clocks;
First counter decoding means for dividing each of the first frequency division counter values by 1 / N (where N is a natural number) and outputting a frequency division signal;
Selecting means for selecting one of the divided signals from the two divided signals;
Phase comparison means for comparing the phase of the selected frequency-divided signal and the output frequency-divided signal fed back from the output, and outputting a phase difference corresponding voltage corresponding to the phase difference;
Filtering means for filtering the phase difference corresponding voltage and outputting a control voltage;
Clock generation means for controlling the frequency with the control voltage and outputting a frequency control clock that is α times (where α is a natural number) times the input clock;
A clock output means for dividing the frequency control clock by 1 / α and outputting an output clock;
Second frequency division counter means for outputting a second frequency division counter value from the frequency control clock;
A second counter decoding means for dividing the second frequency division counter value by 1 / (N × α), temporarily storing an output frequency division signal, and outputting it;
A phase in which a phase difference between one of the first frequency division counter values of the two systems and the second frequency division counter value is detected as a phase difference value with the frequency accuracy of α times using the frequency control clock. Difference detection means;
A clock non-interruptible switching device comprising phase matching means for adding and subtracting the temporarily stored output frequency-divided signal with the phase difference value when the system is switched.   2. The clock uninterruptible switching device according to claim 1, wherein when dividing the clocks of the two systems, the first frequency division counter means of the other clock is reset from one clock. Switching device.   3. The clock uninterruptible switching device according to claim 2, wherein the reset causes the phase difference between the first frequency division counter values of the two systems to be within one cycle of the supplied clock in advance. Instantaneous interruption switching device. In an operation method of clock non-instantaneous switching for switching two clocks in redundant transmission without instantaneous interruption, the method includes:
A clock supply step of outputting two clocks having a phase difference;
A first frequency division counter step of outputting a first frequency division counter value from each of the two clocks;
A first counter decoding step of dividing each of the first frequency division counter values by 1 / N (where N is a natural number) and outputting a frequency division signal;
A selection step of selecting one of the divided signals from the two divided signals;
A phase comparison step of comparing the phase of the selected frequency-divided signal and the output frequency-divided signal fed back from the output, and outputting a phase difference corresponding voltage corresponding to the phase difference;
A filtering step of filtering the phase difference corresponding voltage and outputting a control voltage;
A clock generation step of controlling the frequency with the control voltage and outputting a frequency control clock that is α (where α is a natural number) times the input clock;
A clock output step of dividing the frequency control clock by 1 / α and outputting an output clock;
A second frequency division counter step of outputting a second frequency division counter value from the frequency control clock;
A second counter decoding step of dividing the second frequency division counter value by 1 / (N × α), temporarily storing the output frequency division signal, and outputting it;
A phase in which a phase difference between one of the first frequency division counter values of the two systems and the second frequency division counter value is detected as a phase difference value with the frequency accuracy of α times using the frequency control clock. A difference detection step;
And a phase matching step of adding and subtracting the output frequency-divided signal temporarily stored with the phase difference value to match the phase when switching of the system occurs.

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