JP3346520B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
Particularly, the present invention relates to a method for stabilizing coefficient setting at an overlap point in a PLL circuit having a coefficient multiplier.

[0002]

2. Description of the Related Art In order to expand the lock frequency range, a conventional PLL circuit compares the phase of an input reference signal with the phase of a comparison signal from a 1 / N frequency divider 5 as shown in FIG. A phase comparison unit 1 for outputting a detection signal, an LPF (loop filter) 2 for integrating the phase difference detection signal to remove a high frequency component and output a VCO control voltage, and a signal of a frequency corresponding to the VCO control voltage A VCO (voltage controlled oscillator) 3 to be generated, a coefficient multiplier 4 for multiplying a signal from the VCO 3 by a predetermined variable coefficient to output a clock signal, and a clock signal from the coefficient multiplier 4 for 1 / N The 1 / N frequency divider 5 for outputting a comparison signal, and an unlock detection circuit 6 for detecting unlock and an unlock direction from the reference signal and the comparison signal; Lock detection It was composed of a coefficient control unit 9 for setting the coefficient of the coefficient multiplier based on the item. However, in this configuration, as shown in FIG. 12, the locked VCO control voltage for the input reference signal (Href) of the same frequency is
Plural (two in FIG. 13) curves (Qn
And Qn + 1), and exist as VCO control voltage (Vl) and VCO control voltage (Vh), and they are locked regardless of which coefficient is set.

However, the VCO control voltage differs from (Vl) or (Vh) between the case of locking with the coefficient (Qn) and the case of locking with the coefficient (Qn + 1). As shown in FIG. 14, the phase difference of the comparison signal is locked in the former case where the comparison signal advances from the reference signal, and in the latter case the comparison signal locks after the reference signal. When the video signal is sampled with clock signals having different phases as described above, sampling positions are shifted as shown in FIG. 15, so that different data is sampled, and this sampled data is returned to the original video signal and displayed. When you try
There is a problem in that, when locking is performed with different coefficients, such as blurring, blurring, and sharpness, videos having different video qualities are reproduced.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and when there is a possibility of locking with a different coefficient as described above, a PLL circuit for selecting and setting one of the predetermined coefficients. It is intended to provide.

[0005]

In order to solve the above-mentioned problems, the present invention compares a phase of an input reference signal with a phase of a comparison signal from a 1 / N divider and outputs a phase difference detection signal. A LPF (loop filter) that integrates the phase difference detection signal to remove a high-frequency component and outputs a VCO control voltage; and a VCO (voltage controlled oscillator) that generates a signal having a frequency corresponding to the VCO control voltage. , A coefficient multiplier for multiplying a signal from the VCO by a predetermined variable coefficient to output a clock signal, and a clock signal from the coefficient multiplier being 1 / N
The 1 / N frequency divider for dividing and outputting a comparison signal, an unlock detection circuit for detecting unlock and an unlock direction from the reference signal and the comparison signal, and unlock detection from the unlock detection circuit In a PLL circuit configured with a coefficient control unit that sets a coefficient of the coefficient multiplier based on a signal, a plurality of VCO control voltages locked when the coefficient is changed are compared to determine a control direction of the coefficient to determine a direction. A control direction discriminating unit that outputs a signal, the unlock detection signal, and an up-down control circuit that controls switching between up and down of a coefficient according to the direction discrimination signal,
The coefficient control section is controlled by an up / down control signal from the up / down control circuit to determine a coefficient of the coefficient multiplier.

[0006]

As described above, according to the PLL circuit of the present invention, the unlock state is detected from the reference signal and the comparison signal, the coefficient is varied in the locking direction from the unlock detection signal, and the locking is performed. Further, it is checked whether the coefficient is locked by one coefficient above or below by increasing or decreasing the coefficient. If there are two or more lock states, the difference between the VCO control voltage data and the predetermined reference voltage data is calculated. The coefficient to be locked is selected and set in a direction where the difference is small, that is, the one closer to the reference voltage data. When the difference between the VCO control voltage data and the reference voltage data is the same, the smaller coefficient is used. (Or the larger one) is fixedly selected and set.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a PLL circuit according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention. In the figure, reference numeral 1 denotes a phase comparison unit which compares a phase of an input reference signal (Href) with a phase of a comparison signal (Hvari) from the 1 / N frequency divider 5 and outputs a phase difference detection signal (Spd). . 2 is LPF
(Loop filter), the phase difference detection signal (Spd)
Is integrated to remove high frequency components, and VCO control voltage (Vc)
Is output. Reference numeral 3 denotes a VCO (Voltage Controlled Oscillator) which generates a signal having a frequency corresponding to the VCO control voltage. A coefficient multiplier 4 multiplies the signal from the VCO 3 by a variable coefficient (Q) to output a clock signal (Sck). Reference numeral 5 denotes the 1 / N divider, which divides the clock signal by 1 / N and outputs a comparison signal (Hvari).

Reference numeral 6 denotes an unlock detecting circuit which receives the reference signal (Href) and the comparison signal (Hvari), and when a phase shift of a predetermined value or more continues for a predetermined number of times, the unlock signal is determined and the unlock signal is determined. (Sul) and an unlock direction signal (Suld) indicating whether the phase shift is shifted to a high frequency or a low frequency. Reference numeral 7 denotes a control direction discriminating unit, which is a VC from the LPF.
The O control voltage is compared with a predetermined reference voltage (Vs) for each field, and if the comparison result before and after is different, a control direction discrimination signal in the direction of the coefficient set in the field closer to the reference voltage is output. If the comparison results are the same, a control direction discrimination signal (Scd) for the direction with the smaller coefficient is output. Reference numeral 8 denotes an up / down control circuit which receives an unlock signal (Sul) and an unlock direction signal (Suld) from the unlock detection circuit 6 and a control direction determination signal (Scd) from the control direction determination unit 7. , And outputs an up-down control signal (Scu / d) for controlling whether to increase or decrease from the current coefficient. Reference numeral 9 denotes a coefficient control unit, which controls the up-down control signal (Scu / d).
The coefficient (Q) is set by the following formula, and is input to the coefficient multiplier 4.

FIG. 2 is a detailed circuit block diagram showing one embodiment of the coefficient control section 9. In the figure, reference numeral 91 denotes an up / down counter, which receives an up / down control signal (Scu / d) from the up / down control circuit 8 and an up / down signal (Su / d) and an up / down enable signal (Seu / d) to be described later. Based on this, the field edge signal (Sveg) is counted up or down, and count data (Dc) is output. Reference numeral 92 denotes a ROM that constitutes a look-up table.
The coefficient data (Dq) shown in (b) is stored, and the count data (Dc) is input to the ROM address, and the corresponding coefficient data (Dq) is output. still,
In the present embodiment, the look-up table 92 is configured by a ROM, but is configured by a nonvolatile RAM and provided with a data input unit.
Needless to say, by enabling variable input of data from the outside, it is possible to expand the clock frequency range to be output and the input frequency range. 9
3 is a setting data format conversion unit,
The coefficient data (Dq) is converted into an input data format (for example, serial data) of the coefficient multiplier 4 to output a coefficient (Q).

FIG. 3 is a detailed circuit block diagram showing an embodiment of the up-down control circuit. In the figure, reference numeral 81 denotes a first D latch which latches an unlock signal (Sul) from the unlock detection circuit 6 as an enable signal and an unlock direction signal (Suld) as data as a field edge signal (Sveg). And the inverted output terminal (-
Q) outputs a direction inversion signal (-Suldr). Reference numeral 82 denotes a selector, which outputs the unlock direction signal (Su
ld) and a direction inversion signal (-Suld) are input, and selected by the control direction discrimination signal (Scd) from the control direction discrimination unit 7 to output an up / down signal (Su / d). 83 is a second D latch, which is an unlock signal (Su
l) as data, a field edge signal (Sveg)
And outputs an unlock latch signal (Slur). Reference numeral 84 denotes a first OR circuit which takes a logical sum of the unlock signal (Sul) and the unlock latch signal (Slur) to obtain an unlock timing signal (Sult).
Is output. A second OR circuit 85 performs a logical OR operation of the unlock timing signal (Sult) and the control direction determination signal (Scd) from the control direction determination unit 7 to generate an up / down enable signal (Seu / d). Output.

FIG. 4 is a detailed circuit block diagram showing an embodiment of the control direction judging section 7. In the figure, reference numeral 70 denotes an A / D converter, which converts the VCO control voltage (Vc) from the LPF 2 into a digital signal and outputs VCO control voltage data (Dv
c) is output. Reference numeral 71 denotes a deviation value calculation unit,
The absolute value of the difference between the O control voltage data (Dvc) and the reference data (Dvs) is calculated for each field, and each deviation value data (Dvc-s) is calculated. A first register 711 stores the VCO control voltage data (Dvc) at the rise of the field delay signal (Svd). Reference numeral 712 denotes a second register, which is one field before the VCO control voltage data (Dv) stored in the first register.
c-1) is stored at the rise of the field delay signal (Svd). 713, a reference data storage unit;
The approximate center value of the VCO control voltage variable range constituted by OM is stored as reference data (Dvs). In this embodiment, the reference data storage unit 713 is constituted by a ROM. However, a nonvolatile RAM may be used, and a data input unit may be provided so that data can be variably input from the outside. A first subtractor 714a is a VCO control voltage data (Dvc) and reference data (Dv) stored in the first register 711.
s) is calculated, and the deviation value data (Dvc-
s) is output. A second subtractor 714b calculates an absolute value of a difference between the VCO control voltage data (Dvc─1) stored in the second register 712 and the reference data (Dvs), and calculates deviation value data (Dvc-1). −s).

In FIG. 4B, a subtractor 714 calculates the absolute value of the difference between the VCO control voltage data (Dvc) from the A / D converter 70 and the reference data (Dvs). , And deviation value data (Dvc-s). A first register 711a stores and outputs the deviation value data (Dvc-s) at the rise of the field delay signal (Svd). A second register 712a stores and outputs the deviation value data (Dvc-1-s) one field before stored in the first register 711a at the rise of the field delay signal (Svd). Numeral 72 is a direction discriminating section, which is used for the deviation value data (D
vc-s) and the deviation value data (Dvc-
1-s), and outputs a control direction discrimination signal (Scd) for discriminating the up or down direction of the coefficient from the comparison result. Reference numeral 73 denotes a field signal generation unit which detects an edge of an input vertical synchronization signal (Vsync) and outputs a field edge signal (Sveg), and a field edge signal (S).
veg) for a predetermined time and a field delay signal (Sv
and d) outputting a frame delay circuit 732.

FIG. 5 is a detailed block diagram showing an embodiment of the direction discriminating section 72. In the figure, reference numeral 721 denotes a first comparison unit, which is the difference value data (Dvc-s) from the difference value calculation unit 71 and the difference value data (Dv-
c-1-s), the deviation value data (Dvc-1-s) one field before is replaced by the current deviation value data (Dvc-s).
A different value signal (Sn) when different from s) and an equal value signal (Seq) when same are output. Reference numeral 722 denotes a different value direction discriminating unit which detects a rising edge of the different value signal (Sn) and outputs a different value edge signal (Segn). 7
Reference numeral 23 denotes an equivalent direction discriminating section which outputs an equivalent edge signal (Segeq) from the equivalent signal (Seq) and the count data (Dc) from the up / down counter 91. Reference numeral 724 denotes a control direction discrimination signal synthesizing unit, which outputs an unlock timing signal (Su
lt) from the fall of the field edge signal (Sve)
Until g), the direction discrimination signal (Scd) in which the H level is latched by the logical sum output of the different value edge signal (Segn) and the same value edge signal (Segeq) is output.

FIG. 6 is a detailed circuit block diagram showing an embodiment of the direction discriminating section 72. FIG. 6A shows details of the different value direction discriminating section 722 and the control direction discriminating signal synthesizing section 724. 6- (b) shows the details of the equivalent direction discrimination section 723. In FIG. 6A, reference numeral 7221 denotes a first rising edge detection circuit which detects a rising edge of the different value signal (Sn) from the first comparator 721 and outputs a different value edge signal (Segn). are doing. Reference numeral 7241 denotes a third OR circuit, which is the same-value edge signal (Seg) from the same-value direction discrimination unit 723 as the different-value edge signal (Segn).
eq) is output as a determination clock signal (Sdck). Reference numeral 7242 denotes a falling edge detection circuit which detects the falling edge of the unlock timing signal (Sult) from the up / down control circuit. Reference numeral 7243 denotes a first H latch circuit, which is reset by a falling edge signal (Segd) from the falling edge detection circuit 7242, and
Using the inverted output of 43 as an enable signal, the H level is latched by a field edge signal (Sveg) and a changeable signal (Sech) is output. 7244 is the second H
The latch circuit resets with a field delay signal (Svd), and sets a high level with a discrimination clock signal (Sdck) from the third OR circuit 7241 during a change enable signal (Sech) from the first H latch circuit 7243. The level is latched and a direction discrimination signal (Scd) is output.

In FIG. 6B, reference numeral 7231 denotes a third register which sequentially stores and outputs count data (Dc) from the up / down counter 91 of the coefficient control unit 9 as a field delay signal (Svd). ing. Reference numeral 7232 denotes a fourth register which sequentially stores count data (Dc-1) one field before stored in the third register as a field delay signal (Svd) and outputs the count data. 72
Reference numeral 33 denotes a second comparison unit which compares the count data (Dc) with the count data (Dc-1) one field before to compare the count data (Dc-
If 1) is greater than the count data (Dc), a comparison signal (Scc) which is set to H level is output. Reference numeral 7234 denotes a first AND circuit which outputs the logical product of the comparison signal (Scc) from the second comparison unit 7233 and the equivalent signal (Seq) from the first comparison unit 721. Reference numeral 7235 denotes a second rising edge detection circuit,
234, and outputs an equivalent edge signal (Segeq) to detect the rising edge of the signal from the third OR circuit 72.
41 has been entered.

FIG. 7 is a block diagram showing one embodiment of the unlock detecting circuit 6. As shown in FIG. In the figure, reference numeral 61a denotes a first edge detection circuit which detects a rising edge of an input reference signal (Href) and outputs an edge signal (Seghr). Reference numeral 61b denotes a second edge detection circuit which detects a rising edge of the comparison signal (Hvari) from the 1 / N frequency divider 5 and outputs an edge signal (Segv). Reference numeral 62 denotes a counter, which is reset by an edge signal (Segv) from the second edge detection circuit 61b,
The output clock signal (Sck) is counted. An a-value decoder 63a decodes the a-value of the data from the counter 62 and outputs a decoded signal (Sa). 63b is a b-value decoder, and the counter 6
2 to decode the b value of the data and decode signal (S
b) is output. 64 is an SR flip-flop,
The decode signal (Sa) is input to an S terminal, the decode signal (Sb) is input to an R terminal, and a gate pulse (Pg) is output from an inverting (-Q) terminal.

Reference numeral 65 denotes a third D latch which latches the gate pulse (Pg) as data using an edge signal (Seg) from the first edge detection circuit 61a, and outputs an H level signal from the Q terminal when the phase is locked. , A lock change signal (Slch) of L level at the time of unlocking, and an unlock change signal (Sulch) of L level at the time of phase lock and H level at the time of unlock from the -Q terminal. 66a
Is a second AND circuit which takes the logical product of the edge signal (Seg) and the unlock change signal (Sulch) and outputs an unlock edge signal (Segul). 66
b is a third AND circuit, and the edge signal (Seg)
AND signal of the lock change signal (Slch) and outputs a lock edge signal (Segl). A first integration counter 67a counts an unlock edge signal (Segul) of a logical product output from the second AND circuit 66a. A second integration counter 67b counts a lock edge signal (Segl) of a logical product output from the third AND circuit 66b. A first X value decoder 68a decodes a predetermined number (for example, 5) of the output from the first integration counter 67a and outputs a first decoded signal (Sxs). A second X value decoder 68b decodes a predetermined number (for example, 5) of the output from the first integration counter 67b and outputs a second decoded signal (Sxr).

A first inverter 69a inverts the first decode signal (Sxs) to reset the second integration counter 67b. A second inverter 69b inverts the second decode signal (Sxr) to reset the first integration counter 67a. 60a
Is an SR flip-flop, which inputs the first decode signal (Sxs) to the S terminal, inputs the second decode signal (Sxr) to the R terminal, and outputs an unlock detection signal (Sul) from the Q terminal. are doing. 60b is the fourth D
The latch uses the most significant bit output signal (MSB) of the data from the counter 62 as data, and outputs the unlocked edge signal (Se) of the logical product output of the second AND circuit 66a.
gul) and unlock direction detection signal (Sul
d) is output.

The operation of the above configuration will now be described. Now, an operation when the input reference signal (Href) is changed to a higher frequency fh than the current state in the locked state will be described. First, the operation of the unlock detection circuit 6 will be described with reference to the block diagram shown in FIG. 7 and the timing chart shown in FIG. The clock signal (Sck) is counted from the rising edge (Seghr) of the comparison signal (Hvari) from the 1 / N divider 5 and decoded by counting.
Value decode signal (Sa) and b value decode signal (Sb)
The gate pulse (Pg) obtained from the reference signal (Hre)
The lock change signal (Slch) latched and output by the rising edge signal (Seghr) of f) changes from the H level in the locked state to the L level in the unlocked state due to a change in the reference signal. In the AND circuit 66a, an unlock change signal (Sulch) and a reference signal (Href)
The edge signal (Segul) at the time of unlocking is obtained from the logical product with the edge signal (Seghr), and when this is counted X times by the integrating counter 67a, it is determined that the lock is released, and the SR flip-flop 60a is set. And outputs an H-level unlock signal (Sul), and the AND circuit 66b determines the lock edge from the logical product of the lock change signal (Slch) and the edge signal (Seghr) of the reference signal (Href). Get the signal (Segl)
When this is counted X times by the integration counter 67b, it is determined that the lock has been achieved, the SR flip-flop 60a is reset, and an L level unlock signal (Sul) is output and input to the up / down control circuit 8. Also, the most significant bit output signal of the data from the counter 62 (MS
B) is latched by an edge signal (Segul) at the time of unlocking, so that an unlock direction signal (Suld in the present example, which has been unlocked in a direction lower in frequency than the reference signal and thus at H level). ) Is output to the up-down control circuit 8.

Next, the operation of the up / down control circuit 8 will be described with reference to the block diagram of FIG. 3 and the timing chart of FIG. As described above, when the unlock detection unit 6 detects that the reference signal has changed to a high frequency to be unlocked, the unlock signal (Sul) at the H level and the unlock direction signal (Suld) at the H level are detected. Is input to the up-down control circuit 8. The H-level unlock direction signal (Suld) is input to the U / D control terminal of the up / down counter 91 of the coefficient control unit 9 via the selector 82, and is controlled to count up. Also, H
The level unlock signal (Sul) is synthesized with the unlock latch signal (Slur) latched for one field period by the first OR circuit 84 and becomes an unlock timing signal (Sult) obtained by extending the H level for one field period. The signal is input to the enable terminal of the up / down counter 91 via the second OR circuit 85 to enable the up / down operation, and the count is forcibly advanced even in the next unlocked field. Second OR circuit 85
Since the other input is still at the L level in this process, the output of the first OR circuit 84 is directly input to the up / down counter 91. In this process, the selector also uses A
Side is selected.

Next, the operation of the control direction discriminating means 7 will be described with reference to the block diagrams shown in FIGS. 4, 5 and 6 and the timing chart shown in FIG. As shown in FIG. 4A, the VCO control voltage (Vc) from the LPF 2 is set to A /
The VCO control voltage data (Dvc) converted to a digital signal by the D conversion unit 70 is input to the first register 711,
The VCO control voltage data (Dvc) is detected by the field edge detector 731 at the falling edge of the input vertical synchronizing signal, and stored at the timing of the field delay signal (Svd) delayed by the field delay circuit 732 for a predetermined period. VCO control voltage data (Dvc) one field before
-1) is stored in the second register 712. From the VCO control voltage data (Dvc) to be stored and the VCO control voltage data (Dvc-1) one field before, predetermined reference data (Dvs) to be stored in the reference data storage unit 713.
td) is converted to the first subtractor 714a or the second subtractor 71.
4b, the difference value data (Dvc) of the absolute value of the difference and the difference value data (Dv
c-1) is calculated and input to the direction determination unit 72. In the case of the embodiment of FIG. 4B, the subtracted data is stored in the register, and the output result is the same.
As shown in FIG. 5, the first comparing unit 72 of the direction determining unit 72
In step 1, the magnitude of the deviation value data (Dvc) and the deviation value data (Dvc-1) one field before are compared.
If the deviation value data before the field is large, it is set to L level, and if it is small, it is set to H level.
The difference value data (Dvc) input to the different value direction discriminating unit 722 and the current value of the deviation value
vc-1), the H-level equivalent signal (Se)
q) is output to the equivalent direction discriminating unit 723.
The different value direction discrimination unit 722 detects the rising of the different value signal (Sn), that is, the field where the current deviation value data (Dvc) is larger than the deviation value data (Dvc-1) of one frame before, and detects the first field. Rising edge detection circuit 7
In step 221, the rising edge is detected, and the different value edge signal (Segn) is output to the third
Is input to the OR circuit 7241. In the case of the example of FIG. 10, the current deviation value data (Dvc) = β is larger than the deviation value data (Dvc-1) of one field before = α (α <
β), the different value signal (Sn) becomes H level, and the rising edge is detected to detect the different value edge signal (Se).
gn). On the other hand, the equivalent direction discriminating section 723 sequentially stores the count data (Dc) from the up / down counter 91 for two fields with the field delay signal (Svd), compares the sizes thereof, and compares the count data (Dc) of the current field. ) Is greater than the count data (Dc-1) one field before, outputs a comparison signal (Scc) that outputs an H level, detects a rise of an AND signal with the equivalent signal (Seq), and outputs a control direction discrimination signal. The signal is input to the third OR circuit 7241 of the synthesis unit 724.
In the example of FIG. 10, since the equivalent signal (Seq) is at the L level, the logical product signal does not rise and the equivalent edge signal (Segeq) remains at the L level.

The control direction discrimination signal synthesizing section 724 shown in FIG.
Then, the falling edge detection circuit 7242 detects that the unlock timing signal (Sult) extended by one field period from the first OR circuit 84 falls, that is, that the up / down counter 91 is disabled.
The first H latch circuit 7243 generates a falling edge signal (Seg) of the unlock timing signal (Sult).
d) is reset, the -Q output is set to the H level, and the variable signal (Sech), which is set to the L level by the next field edge signal (Sveg), is set to the second enable signal.
, And the second H latch circuit 7244 supplies a rising edge signal (Segn) of the different value signal (Sn) and a signal (Scc) equivalent to the comparison signal (Scc).
eq) and the rising edge signal (Seg
q) as a clock signal (Sdck), latches the H level, and outputs a direction discrimination signal (Scd) which keeps the H level until the next delay field signal is input, and outputs the direction determination signal (Scd) of the up-down control circuit 8. The coefficient is input to the OR circuit 85 of the second circuit and used as an up / down enable signal (Seu / d) of the up / down counter 91 of the coefficient control unit 9. For example, in the case of the example of FIG. 10, the unlock timing signal (Su
If the current deviation value data (Dvc) after one field is larger than the deviation value data (Dvc-1) when the state changes from the unlocked state to the locked state after the fall of lt), The rising edge signal (Segn) of the signal (Sn) is used as a clock signal (Sdck) to output a direction discrimination signal (Scd) which is at the H level for a period until the next delay field signal (Svd). Up / down enable signal (Seu /
d) is input to the enable terminal of the up / down counter 91 to enable the count operation, and the direction discrimination signal (Scd) is also switched by the selector 82 to select the inverted signal and to be sent to the U / D control terminal of the counter 91. By inputting an L level up / down signal (Su / d), a down count is performed to return to the count one field before.

The timing chart of FIG. 11 shows a case where the deviation value data (Dvc) of the current field is the same as the deviation value data (Dvc-1) of one field before, and the operation of this example will be described below. In the case of the example of FIG.
In 2, the different value signal (Sn) of the output of the first comparing section 721 becomes L level, the different value edge signal (Segn) is not detected, and the same value signal (Seq) becomes H level. In the equivalent direction discriminating unit 723, the count data (Dc) of the current field is changed to the count data (Dc) one field before.
-1), the comparison signal (Sc) that outputs an H level when it is larger than
c), and detects the rise of the logical product signal with the H-level equivalent signal (Seq), and detects the equivalent edge signal (Seg).
q) is output to the third OR circuit 7241 of the control direction discrimination signal synthesizing unit 724, and the clock signal (Sdck)
And outputs a direction discrimination signal (Scd) which is kept at the H level for a period until the next delay field signal (Svd).
Is input to an enable terminal of an up / down counter 91 as an up / down enable signal (Seu / d) through an OR circuit 85 to enable the count operation, and the direction determination signal (Scd) is also inverted by switching the selector 82. A signal is selected, and an L level up / down signal (Su / d) is input to the U / D control terminal of the counter 91 to count down and return to the count one field before.

Next, the operation of the coefficient control section 9 for controlling the coefficient multiplier 4 will be described with reference to the block diagram of FIG. 2 and the timing chart of FIG. When an H-level up / down enable signal (Seu / d) is input to the enable terminal of the up / down counter 91, the field edge is determined according to the state of the up / down signal (Su / d) input to the U / D control terminal. The signal (Sveg) is counted. For example, when the up / down signal (Su / d) of the U / D control terminal is at the H level, the count is up, and when it is at the L level, the count is down. The count data of the up / down counter 91 is obtained by referring to a look-up table that stores data shown in FIG. 9 in advance, obtaining corresponding coefficient data, converting the coefficient data into an input format of the coefficient multiplier 4, and outputting the converted data. I have.

[0025]

As described above, the PL according to the present invention is
According to the L circuit, the unlock state is detected from the reference signal and the comparison signal, the coefficient is changed in the locking direction from the unlock detection signal, the lock is performed, and the coefficient is raised or lowered to raise or lower by one. Check whether to lock with the next lower coefficient. If there are two or more lock states, VCO
The difference between the control voltage data and the predetermined reference voltage data is calculated, and the coefficient for locking is selected and set in the smaller difference, that is, closer to the reference voltage data, and the VCO control voltage data and the reference voltage are set. If the difference from the data is the same, the smaller coefficient (or the larger coefficient) is fixedly selected and set. If there is a possibility of locking with a different coefficient, one of the predetermined coefficients is used. Can be selected and set to provide a PLL circuit in which the lock phase does not fluctuate.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a PLL circuit according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a coefficient control unit according to the present invention.

FIG. 3 is a block diagram showing one embodiment of an up-down control circuit according to the present invention.

FIG. 4 is a block diagram showing an embodiment of a control direction determining means according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a direction discriminating unit according to the present invention.

FIG. 6 is a detailed circuit block diagram showing an embodiment of a direction discriminating unit according to the present invention.

FIG. 7 is a detailed circuit block diagram showing an unlock detection circuit.

FIG. 8 is a timing chart of signals of various parts of the unlock detection circuit.

FIG. 9 is a diagram showing an example of a VCO voltage versus coefficient, an output frequency characteristic, and a look-up table for explaining the operation;

FIG. 10 is a timing chart of signals of respective parts of the PLL circuit according to the present invention.

FIG. 11 is a timing chart of signals of various parts of the PLL circuit according to the present invention.

FIG. 12 is a block diagram showing a conventional PLL circuit.

FIG. 13 is a diagram illustrating an overlap point of a VCO voltage.

FIG. 14 is a diagram illustrating a phase difference due to a VCO voltage.

FIG. 15 is a diagram illustrating a difference when sampling is performed using clock signals having different phases.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 LPF 3 VCO 4 Coefficient multiplier 5 1 / N frequency divider 6 Unlock detection circuit 7 Control direction discrimination part 8 Up / down control circuit 9 Coefficient control part 61a 1st edge detection circuit 61b 2nd edge Detection circuit 62 counter 63a a-value decoder 63b b-value decoder 64 SR flip-flop 65 third D-latch 66a second AND circuit 66b third AND circuit 67a first integration counter 67b second integration counter 68a first X value decoder 68b second X value decoder 69a SR flip-flop 69b fourth D latch 71 deviation value calculator 72 direction discriminator 73 field signal generator 711 first register 712 second register 713 reference data storage 714a First subtractor 714b Second subtractor 721 First ratio Unit 722 Different value direction discriminating unit 723 Equivalent direction discriminating unit 724 Control direction discriminating signal synthesizing unit 731 Field edge detecting circuit 732 Field delay circuit 7221 First rising edge detecting circuit 7231 Third register 7232 Fourth register 7233 Second Comparison section 7234 First AND circuit 7235 Second rising edge circuit 7241 Third OR circuit 7242 Falling edge detection circuit 7243 First H latch circuit 7244 Second H latch circuit

Claims (12)

(57) [Claims] 1. A phase comparator for comparing the phases of an input reference signal and a comparison signal from a 1 / N divider to output a phase difference detection signal, and integrating the phase difference detection signal to reduce a high frequency component. An LPF (loop filter) for removing and outputting a VCO control voltage, a VCO (voltage controlled oscillator) for generating a signal having a frequency corresponding to the VCO control voltage, and a signal from the VCO multiplied by a predetermined variable coefficient. A coefficient multiplier for outputting a clock signal, and a clock signal from the coefficient multiplier being 1
The 1 / N frequency divider for dividing the frequency by a factor of / N and outputting a comparison signal;
An unlock detection circuit that detects unlock and an unlock direction from the reference signal and the comparison signal, and a coefficient control unit that sets a coefficient of the coefficient multiplier based on an unlock detection signal from the unlock detection circuit. PLL circuit that locks when the coefficient is varied
A control direction discriminator for comparing the O control voltage and discriminating the control direction of the coefficient to output a direction discrimination signal; A PLL circuit comprising a control circuit, wherein the coefficient control section is controlled by an up / down control signal from the up / down control circuit to determine a coefficient of the coefficient multiplier. 2. An up / down counter for counting up or down a field signal by the up / down control signal, a look-up table for outputting a coefficient based on a signal from the up / down counter, 2. A setting data format converter for converting a coefficient into an input format of the coefficient multiplier.
The PLL circuit as described in the above. 3. The look-up table has a data input unit, and is configured by a nonvolatile RAM or a RAM with a backup circuit, so that data stored from the outside is rewritten. PL
L circuit. 4. An up-down control circuit, comprising: a first D-latch for inverting and storing an unlock direction signal of the unlock detection signal; an inverted signal from the first D-latch; A selector for switching between a lock direction detection signal and outputting an up / down signal, a second D-latch for holding an unlock signal of the unlock detection signal for one field period, and an output from the second D-latch A first OR circuit for outputting a logical sum of the unlock signal and the unlock signal; and a first OR circuit for calculating an OR of a signal from the first OR circuit and a direction determination signal from the control direction determination unit and outputting an enable signal. 2. The PLL circuit according to claim 1, comprising two OR circuits. 5. An A / D converter for converting a VCO control voltage into a digital signal, a reference data storage unit for storing predetermined reference data, a control data determining unit for storing the reference data and the A / D conversion. A deviation value calculation unit that calculates a difference between the control voltage data from the device for each field, and a direction determination unit that compares the magnitudes of the plurality of deviation values for each field and determines a coefficient control direction based on the comparison result. 2. The PLL circuit according to claim 1, wherein the PLL circuit comprises: 6. The reference data storage section has a data input section, and has a nonvolatile RAM or an R with a backup circuit.
6. The PLL circuit according to claim 5, wherein the PLL circuit is constituted by an AM so that data stored from outside is rewritten. 7. The deviation value calculation unit includes a first register that stores control voltage data from the A / D converter, a second register that stores control voltage data one field before, and the reference data. It is characterized by comprising a first subtractor and a second subtractor each calculating a difference between reference data stored in a storage unit and a signal from the two registers and outputting a deviation value. The PLL circuit according to claim 5. 8. A subtractor that calculates a difference between reference data stored in the reference data storage unit and control voltage data from the A / D converter and outputs a difference value, the difference value calculating unit including: 6. The PLL circuit according to claim 5, comprising a first register storing a deviation value and a second register storing a deviation value one field before. 9. A comparator for comparing the magnitudes of two deviation values from the deviation value calculation unit, the direction discrimination unit includes: a comparison result of the comparator; A different value direction discriminating unit for discriminating a coefficient control direction when the comparison result is different, an equivalent direction discriminating unit for discriminating a coefficient control direction when the comparison result of one field before and the comparison result of the current field are the same, 6. The PL according to claim 5, wherein the control direction discriminating signal synthesizing section synthesizes a discriminating signal from the discriminating section and outputs it as a direction discriminating signal.
L circuit. 10. The different value direction discriminating section, wherein the comparison result of the two deviation values from the deviation value calculating section, the comparison signal of one field before is smaller than the comparison result of the current field, 10. The P according to claim 9 , comprising a first edge detection circuit for detecting a rising edge.
LL circuit. And a fourth register for storing count data from an up / down counter of the coefficient control unit, a fourth register for storing count data of one field before, A second comparator for comparing the sizes of the data stored in the two registers, and a comparison result of the comparison signal from the second comparator and the two deviation values from the deviation value calculation unit; An AND circuit for outputting the logical product of the comparison result before the field and the equal signal output when the comparison result in the current field is the same, and a second circuit for detecting the rising edge of the output from the AND circuit
請 to the edge detection circuit characterized by being composed of
The PLL circuit according to claim 9 . 12. A third OR circuit for outputting a logical sum of the different-value edge signal from the different-value direction discriminator and the same-value edge signal from the same-value direction discriminator. A falling edge detection circuit for detecting a falling edge of a signal from the first OR circuit of the up / down control circuit, a resetting operation using the falling edge signal, and an inversion output signal as an enable signal, and A first H level latch circuit for latching the H level; and a signal from the first H level latch circuit is used as an enable signal to latch the H level with a signal from the third OR circuit to generate a direction determination signal. Output second H
10. The level latch circuit according to claim 9, wherein:
The placing of the PLL circuit.