JP2985786B2 - Phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a phase locked loop circuit that quantizes the result of a phase comparison and performs digital processing, and more particularly to a circuit that reduces jitter and wander in a steady state.

[0002]

2. Description of the Related Art Conventionally, a phase locked loop of this type has been known as a PLL.
(Phase-locked loop), and is used to supply a stable output clock especially against fluctuations such as a break in the input clock.

For example, in Japanese Patent Application Laid-Open No. Hei 5-37369, during input clock disconnection, means for generating a signal for maintaining a phase state before input clock disconnection is detected, and detection of recovery of input clock disconnection and detection of input clock A phase-locked loop circuit that reduces the fluctuation of the output clock frequency of the voltage-controlled oscillator when the input clock is restored by cutting off the input clock by generating the reference signal input of the phase comparison circuit using means for initializing the frequency divider Have been.

Further, by quantizing the phase comparison result and digitally processing the quantized phase comparison result, a phase synchronization state is maintained when an input clock loss is detected, and the phase synchronization state is maintained. There is also a phase locked loop circuit with a simple circuit configuration for reducing fluctuations in the output clock frequency of the voltage controlled oscillator during recovery.

FIG. 4 is a block diagram showing an embodiment of a conventional phase locked loop circuit which reduces the fluctuation of the output clock frequency of the voltage controlled oscillator when the input clock is cut off by quantizing the result of the phase comparison.

The first frequency divider 1 has a second frequency divider 9 to be described later.
The input clock a is frequency-divided to have the same frequency as the output frequency-divided clock j, and the output clock b is output.

The phase comparison circuit 2 compares the phase of the clock b obtained by dividing the input clock a with the clock j obtained by dividing the output clock i of the voltage controlled oscillator 8 described later, and outputs the result of the phase comparison.

The quantization circuit 3 samples the phase comparison result c with a quantization clock p from a reference signal generation circuit 10 described later, and latches it in accordance with the timing indicated by a reference signal k from the reference signal generation circuit 10 described later. Output the value d.

The phase information holding circuit 4 converts the digital value d output from the quantization circuit 3 into a reference signal generation circuit 1 described later.
At the same time as holding the reference signal k from 0, the latest digital value is output when the input clock is steady. Also, when the input clock is cut off, the digital value is output alternately immediately before the cut-off and the digital value before a fixed time indicated by the reference signal k from the reference signal generating circuit 10 described later. Further, when the input clock is restored, an output clock b obtained by dividing the restored input clock a by the first frequency divider 1 and a clock j obtained by dividing the output clock i of the voltage controlled oscillator 8 by the second frequency divider 9 Is output to the second frequency divider 9 so that the phase comparison result c obtained by comparing the phase comparison circuit 2 with the phase comparison circuit 2 matches when the input clock a is cut off and when the input clock a is restored. I do.

The D / A conversion circuit 12 converts an input digital value e into an analog signal o indicating a control voltage of a voltage controlled oscillator 8 described later. The loop filter 7 removes unnecessary harmonic components contained in the analog signal o.

The voltage controlled oscillator 8 outputs a clock i having a frequency corresponding to the input voltage indicated by the analog value h from the loop filter 7.

The reference signal generation circuit 10 outputs a quantization clock p indicating a sampling interval and a reference signal k indicating a latch interval of a sampling result. Clock loss detection circuit 1
1 observes the input clock a to detect a clock loss,
An alarm signal n is output.

Next, the operation will be described. First, when the input clock is normal, a clock b obtained by dividing the input clock a by the first frequency divider 1 and a clock j obtained by dividing the output clock i of the voltage controlled oscillator 8 by the second frequency divider 9 are used. Phase comparison circuit 2
After the phase comparison result c of the output is sampled by the quantization clock p and latched by the reference signal k, a quantized digital value d is obtained.

The phase information holding circuit 4 holds the digital value at regular time intervals according to the reference signal k and simultaneously outputs the latest digital value e. The D / A conversion circuit 12 converts the digital value e into an analog value o, removes harmonic components by a loop filter 7, and
, The output clock i is obtained.

From the above, when the frequency of the input clock a increases, the output clock frequency of the voltage controlled oscillator 8 increases,
When the frequency of the input clock a decreases, the voltage-controlled oscillator 8
By controlling the output clock frequency to be low, a clock having a stable frequency can be obtained by following the fluctuation of the clock frequency.

Next, when the clock loss detection circuit 11 detects an input clock loss, the phase synchronization circuit loses synchronization because the phase comparison signal c using the disconnected input clock does not have information on the input clock, and the output clock is lost. Greatly fluctuates. In order to prevent this fluctuation, the digital value representing the phase information held immediately before the input clock is cut off and held in accordance with the reference signal k and representing the phase information held a predetermined time before is alternately output, and the state before the input clock is cut off. To maintain. When the input clock a is restored, the recovered input clock a is divided by the first frequency divider 1 into a clock b.
And the output clock i of the voltage controlled oscillator 8 to the second frequency divider 9
The digital value d obtained by quantizing the phase comparison result c with the clock j divided by the above is compared with the digital value obtained by quantizing the phase comparison result held immediately before the input clock is turned off. Are adjusted by the second frequency divider 9 in accordance with the signal r from the phase information holding circuit 4 so that the two digital values become equal. When the two digital values become equal, the phase comparison result by the restored input clock is obtained. The output is switched by the phase information holding circuit 4 so as to use.

By this processing, the control voltage to the voltage controlled oscillator can be prevented from suddenly changing even when the input clock is cut or restored, so that a sudden phase change of the output clock can be suppressed.

[0018]

Since the phase synchronization circuit of FIG. 4 described above requires the quantization circuit 3, the output of the quantization circuit always has a quantization error because the phase comparison result is quantized. Contains.

Therefore, the quantization error has a problem that jitter and wander occur in the output clock of the voltage controlled oscillator when the input clock is stationary.

An object of the present invention is to provide a configuration for reducing jitter and wander of an output clock of a voltage controlled oscillator when an input clock is stationary in a phase locked loop circuit for quantizing the above-mentioned phase comparison result.

[0021]

Means for Solving the Problems A phase locked loop circuit according to the present invention is a phase locked loop circuit that uses a PLL (phase locked loop) to obtain an output clock that is stable against fluctuations in the input clock. When the input clock is cut off, the output of the phase comparator is quantized with the reference signal and the signal held as a digital value is reproduced as the output signal of the original phase comparator. The voltage controlled oscillator is controlled by switching to a signal in synchronization with the reference signal.

The phase comparison result is reproduced and output from the digital value obtained by quantizing the phase comparison result. Specifically, the output signal of the phase comparison circuit is sampled by a quantization clock in a quantization circuit, and a digital value obtained by latching with a reference signal is obtained by a reproduction circuit before quantization in accordance with the quantization clock and the reference signal k. Means for reproducing the phase comparison result.

Since the phase comparison result is output without being quantized when the input clock is stationary, phase fluctuation due to a quantization error is suppressed, and jitter and wander can be reduced.

Further, since a digital value as a result of quantizing the phase comparison result is reproduced and output, a signal similar to the phase comparison result is obtained. Therefore, if the phase comparison result is switched by the selection circuit when the input clock is cut off, the synchronization of the phase synchronization circuit can be maintained. Also, when the input clock is stationary, phase fluctuations such as jitter and wander can be suppressed, and when the input clock is cut off, rapid phase fluctuations can be suppressed.

[0025]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The first frequency divider 1 divides an input clock a and outputs a divided clock b. The frequency division ratio of the first frequency divider 1 is set such that the output frequency-divided clock b and the output j of the second frequency divider described later have the same frequency.

The phase comparator 2 calculates the phase between the output frequency-divided clock b of the first frequency divider 1 and the clock j obtained by frequency-dividing the output clock i of the voltage-controlled oscillator 8 described later by the second frequency divider 9. The comparison is performed, and the phase comparison result c is output.

The quantization circuit 3 samples the phase comparison result c in accordance with the output quantization clock p of the reference signal generation circuit 10 described later, and outputs a latched digital value d in accordance with the timing indicated by the reference signal k.

The phase information holding circuit 4 holds the input digital value d in accordance with the reference signal k, outputs the latest digital value when the input clock is stationary, and holds the digital value immediately before the input clock was cut off when the input clock was cut off. The value and the digital value held for a certain period of time held according to the reference signal k are output alternately.

The reproduction circuit 5 reproduces a phase comparison result f similar to the output c of the phase comparison circuit 2 from the digital value e according to the reference signal k.

The selection circuit 6 synchronizes with a reference signal k from a reference signal generation circuit 10 to be described later in response to an alarm n from a clock disconnection detection circuit 11 to be described later. When the input clock is cut, the output f of the reproducing circuit 5 is selected and output.

The loop filter 7 removes unnecessary harmonic components from the output g of the selection circuit 6. The voltage controlled oscillator 8 outputs a clock i whose frequency is controlled by the voltage indicated by the output h of the loop filter 7.

The second frequency divider 9 divides the frequency of the output clock i of the voltage controlled oscillator 8 so that the frequency becomes the same as the output b of the first frequency divider.

The reference signal generation circuit 10 outputs a quantization clock p for sampling the output phase comparison result c of the phase comparison circuit 2 and a reference signal k indicating an interval for latching the sampling result.

Further, when the input clock is restored, the pulse signal m for adjusting the phase of the divided clock b of the input clock a to the phase of the divided clock b immediately before the interruption of the input clock is output. Further, a clock disconnection detection circuit 11 described later
And outputs a switching signal q indicating a switching timing when the selection circuit 6 is switched according to the normal state and the interruption state of the input clock a.

The clock loss detection circuit 11 detects an input clock loss and outputs an alarm n.

Next, the operation of the circuit of FIG. 1 will be described in detail with reference to the time chart of FIG.

In the first frequency divider 1, the input clock a shown in FIG. 2A is converted into a signal b having the same frequency as the output clock of the second frequency divider 9 as shown in FIG. Divided.

The output i of the voltage controlled oscillator 8 is divided by the second frequency divider 9 into a signal j having the same frequency as the output clock of the first frequency divider 1 as shown in FIG. Be circulated.

In the phase comparison circuit 2, the phase is compared by a flip-flop which is set at the rising of the signal b and reset at the rising of the signal j, and the result of the phase comparison is output as a signal c shown in FIG. The signal c is input to the selection circuit 6 and the quantization circuit 3.

In the quantization circuit 3, a signal c which is a phase comparison result based on the quantization clock p from the reference signal generation circuit 10.
Is counted, the result of the phase comparison for a certain time is held in accordance with the reference signal k shown in FIG. 2 (I), and converted to a digital value shown in FIG. 2 (D).

The phase information holding circuit 4 takes in the quantized digital value d and stores it alternately in two memories at regular time intervals according to the reference signal k, and at the same time, at the same time as the input clock a at regular time intervals according to the reference signal k. The digital value designated by the state is output as shown in FIG.

In the reproducing circuit 5, the input digital value is converted by the phase comparison circuit by the quantization clock p indicating the sampling interval from the reference signal generation circuit 10 at each timing indicated by the reference signal k from the reference signal generation circuit 10. 2
2 (F) is output and input to the selection circuit 6.

First, the operation when the input clock is stationary will be described. When the input clock is stationary, the signal c is selected by the selection circuit 6, and the signal g shown in FIG.
Therefore, the phase comparison result is directly input to the loop filter 7.

The loop filter 7 removes harmonic components contained in the signal g, integrates the waveform, and inputs the integrated signal to the voltage controlled oscillator 8 as a signal h indicating a certain voltage.

The voltage controlled oscillator 8 is controlled to increase the frequency of the output clock i when the voltage indicated by the signal h increases, and to decrease the frequency of the output clock i when the voltage decreases. As a result, the frequency of the output clock i of the voltage controlled oscillator 8 follows the frequency fluctuation of the input clock a, so that jitter and wander can be suppressed.

Next, the operation when the input clock is cut off will be described. When the input clock is lost, the detection is performed by the clock loss detection circuit 11, and the signal n is output as an alarm in FIG.
"Hi" is transmitted as shown in (K).

When this alarm is received by the phase information holding circuit 4, the selection circuit 6, and the reference signal generating circuit 10, the phase information holding circuit 4 synchronizes with the reference signal k and outputs the latest digital signal as shown in FIG. Instead of the value, the held digital value immediately before the interruption of the input clock and the digital value a predetermined time before indicated by the reference signal k are alternately output.

The reference signal generating circuit 10 outputs a switching signal q in synchronization with the reference signal k as shown in FIG. The selection circuit 6 outputs the output f of the reproduction circuit 5 instead of the output signal c of the phase comparison circuit in accordance with the switching signal q.
And outputs the signal g shown in FIG. 2 (G). Also,
When recovery from the input clock interruption is detected, the clock interruption detection circuit 11 performs detection, and “Lo” is transmitted as the signal n.

When this signal n is received by the phase information holding circuit 4, the selection circuit 6, and the reference signal generation circuit 10, the reference signal k
In synchronization with the above, the reference signal generating circuit 10 sends out a reset pulse m as shown in FIG.

The first frequency divider 1 is reset by a reset pulse m synchronized with a reference signal k, and receives an input clock a
Is output as a clock b. Therefore, the divided clock b is synchronized with the reference signal.

As shown in FIG. 2E, the phase information holding circuit 4 sends out the clock held for one reference time until the latest phase comparison information is obtained in synchronization with the reference signal k.
Thereafter, the latest phase comparison information is transmitted.

The selection circuit 6 switches selection so as to output the latest phase comparison result c from the phase comparison circuit 2 in accordance with the switching signal q, and sends out the signal g. For this reason, the phase synchronization circuit does not lose synchronization before and after the clock is cut off, and phase fluctuations such as jitter and wander can be reduced.

Further, the fact that the present embodiment can suppress jitter and wander when the input clock is in a steady state as compared with the related art will be described with reference to FIG.

FIGS. 3A, 3C and 3E show the phase comparison result output c of the phase comparison circuit 2. FIG. FIG.
(B), (D), and (F) show the digital value d latched according to the reference clock k by sampling the output of the phase comparison circuit 2 with the quantization clock p shown in FIG. This is a phase comparison result f reproduced by the reproducing circuit 5 in accordance with the reference clock k using the quantized clock p after processing by the phase information holding circuit 4.

However, since the signal f is obtained by quantizing the phase comparison result c by the quantization clock p, it is impossible to express a minute phase fluctuation of one cycle or less of the quantization clock p. Therefore, a minute phase fluctuation appears in the output clock of the phase locked loop as jitter or wander.

That is, if a small phase fluctuation of one cycle or less of the quantized clock p occurs from the state shown in FIGS. 3A and 3B, the signal c is a direct phase comparison result from the phase comparison circuit 2. As shown in FIG. 3C, a minute phase fluctuation is detected. Based on the result of this phase comparison, the voltage controlled oscillator 8
Is controlled by the voltage-controlled oscillator 8 to adjust the frequency of the output clock i in a direction to reduce the phase shift.

Therefore, the jitter and wander of the output clock i are reduced. On the other hand, since the phase comparison result of the signal f is quantized by the quantization clock p, a minute phase fluctuation cannot be detected as shown in FIG. Therefore, the control voltage of the voltage controlled oscillator 8 does not change in the phase comparison result,
The phase shift cannot be recovered. In the case of the signal f, FIG.
As shown in (1), the signal f detects a phase shift when the phase variation reaches one cycle of the quantization clock p, so that the frequency is adjusted in a direction to reduce the phase shift by controlling the voltage-controlled oscillator 8. be able to.

As described above, when the voltage controlled oscillator 8 is controlled by the signal f obtained by quantizing the result of the phase comparison, jitter and wander occur in an amount depending on the cycle of the quantization clock.

In the present embodiment, when the input clock is cut off, the signal f is selected by the selection circuit 6, but when the input clock is steady, the signal c is selected by the selection circuit 6. In this case, jitter and wander can be reduced when the input clock is stationary.

[0062]

The phase synchronization circuit of the present invention selects the output phase comparison result of the phase comparison circuit which does not include a quantization error when the input clock is steady, and quantizes and reproduces the output of the phase comparison circuit when the input clock is cut off. Since a means for switching so as to select a phase comparison result including processing is provided, there is an effect that jitter and wander can be reduced when the input clock is stationary.

Further, the phase locked loop circuit of the present invention quantizes the output phase comparison result of the phase comparison circuit and holds it at regular intervals according to a reference signal. Since there is provided a means for alternately outputting the phase comparison result immediately before the input clock is cut off from the comparison result and a predetermined time before the reference signal according to the reference signal, the phase synchronization can be maintained at the time of recovery from the input clock cutoff.

[Brief description of the drawings]

FIG. 1 is a block diagram of a phase locked loop circuit showing an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG. 1;

FIG. 3 is a time chart for explaining a quantization error suppressing effect of FIG. 1;

FIG. 4 is a block diagram of a conventional phase synchronization circuit that quantizes the result of phase comparison.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first frequency divider 2 phase comparison circuit 3 quantization circuit 4 phase information holding circuit 5 reproduction circuit 6 selection circuit 7 loop filter 8 voltage controlled oscillator 9 second frequency divider 10 reference signal generation circuit 11 clock cutoff detection circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-273648 (JP, A) JP-A-2-100518 (JP, A) JP-A-57-176845 (JP, A) JP-A-4- 306918 (JP, A) JP-A-4-265016 (JP, A) JP-A-3-44214 (JP, A) JP-A-59-4330 (JP, A) JP-A-3-90532 (JP, U) (58) Field surveyed (Int.Cl. ⁶ , DB name) H03L 7/08-7/14

Claims (5)

(57) [Claims] 1. A PLL phase synchronization circuit for obtaining a stable output clock relative to variation in the input clock used (phase locked loop) controls the voltage controlled oscillator with the output signal of the phase comparator circuit during steady of the input clock, before the on input clock loss by switching to reproduction output signal reproduced in the output signal of the phase comparator circuit outputs a source signal which has been held as a digital value by quantization of the phase comparator circuit
A phase locked loop circuit for controlling the serial voltage controlled oscillator, before
The input clock is restored when the input clock is restored.
Frequency division clock output from frequency divider to obtain frequency divided clock
The phase of the clock is adjusted to the phase immediately before the input clock is turned off.
Phase locked loop circuit characterized by have a reference signal generation circuit for outputting a pulse signal for. 2. A phase-locked loop (PLL) circuit that obtains an output clock that is stable with respect to fluctuations in an input clock using a PLL, a first frequency divider that divides an input clock to obtain a first frequency-divided clock, A phase comparator for comparing the phase of the first frequency-divided clock with the second frequency-divided clock, a quantization circuit for sampling an output of the phase comparator and outputting a digital value latched in accordance with a reference signal; A phase information holding circuit for holding a value in accordance with the reference signal, outputting the latest digital value when the input clock is stationary, and alternately outputting the held digital value for a fixed time when the input clock is cut off; A reproduction circuit for converting the digital value output from the information holding circuit into the same output format as the phase comparator in accordance with the reference signal; An output of the phase comparator at all times, a selection circuit for selecting an output of the reproduction circuit by receiving an alarm signal when the input clock is interrupted, and a loop filter for removing unnecessary harmonic components from the output of the selection circuit; A voltage-controlled oscillator whose output clock frequency is controlled by the output of the loop filter, a second frequency divider that divides the output clock and outputs the second divided clock ,
Quantized clock for sampling the output of the phase comparator
And the reference signal indicating the interval at which the sampling result is latched.
And a reference signal generating circuit for outputting the reference signal.
The generation circuit is configured to restore the input clock when the input clock is disconnected.
The phase of the first frequency-divided clock is changed immediately before the input clock is cut off.
Outputs a pulse signal to match the phase
And a phase synchronization circuit. 3. The frequency divider according to claim 2, wherein the first frequency divider and the second frequency divider select a frequency division ratio such that the frequency of each frequency-divided clock becomes the same. Phase synchronization circuit. Wherein said reference signal generating circuit receives the alarm signal at the time of disconnection of the input clock, according to claim 2, wherein the sending a switching signal indicating a switching timing to the selection circuit Phase synchronization circuit. Wherein said alarm signal, receiving said input clock signal, according to claim 1, 4 phase synchronization circuit according to the input clock signal is equal to or sent from the clock interruption detection circuit when the cross-sectional .