JP2728069B2 - Phase synchronization circuit and phase synchronization method using the phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a phase locked loop circuit of a digital signal processing system, and more particularly, to selection of a control voltage for controlling a voltage controlled oscillator.

[0002]

2. Description of the Related Art As an example of a conventional phase locked loop circuit, there is an invention of a PLL circuit described in Japanese Patent Laid-Open No. Hei 5-114857. When the phase comparator detects that the input clock and the VCO output clock are in an asynchronous state, the PLL circuit disclosed in the above publication discloses a control circuit stored in a memory circuit in advance in a synchronous state. By outputting the voltage, the fluctuation of the control voltage (hereinafter, referred to as VCO control voltage) for controlling the voltage controlled oscillator is suppressed, and the lock-up time is shortened.

FIG. 3 is a block diagram showing a conventional phase locked loop circuit, and the invention described in the above publication is rewritten to facilitate comparison with the present invention.

The phase synchronization circuit shown in FIG. 3 includes a phase comparison circuit 21, a low-pass filter (hereinafter referred to as LPF) 12, an A / D conversion circuit 13, and a memory circuit 14.
, A D / A conversion circuit 15, a selection circuit 16, a voltage controlled oscillator (hereinafter referred to as VCO) 17, and a frequency dividing circuit 2.
2 is provided.

[0005] The phase comparison circuit 21 has an asynchronous detection circuit, and inputs an input clock and a clock obtained by dividing the output clock of the VCO 17 by N by the frequency dividing circuit 22 to detect a phase difference. A VCO control voltage corresponding to the phase difference is output and input to the LPF 12. The LPF 12 removes a high-frequency component of the control voltage output from the phase comparison circuit 21,
The signal is input to the A / D conversion circuit 13 and the selection circuit 16.

The A / D conversion circuit 13 includes a phase comparison circuit 21
The control voltage of the analog value output from the LPF 12 and from which the high-frequency component has been removed by the LPF 12 is converted into a digital value, which is input to the memory circuit 14.

The memory circuit 14 has an input clock and a VCO
The phase comparison circuit 2 confirms that the output clock is in a synchronized state.
1 is detected, the A / D conversion circuit 13
The control voltage of the D-converted digital value is stored. Also,
When the phase comparison circuit 21 detects that the input clock and the VCO output clock are in an asynchronous state, it outputs a control voltage of a digital value stored in the memory circuit 14 in advance in a synchronous state, and / A conversion circuit 1
Enter 5

[0008] The D / A conversion circuit 15 converts a digital control voltage output from the memory circuit 14 into an analog value when the clock is in an asynchronous state, and inputs the analog value to the selection circuit 16.

When the clock is in a synchronous state, the selection circuit 16 outputs a control voltage output from the phase comparison circuit 21 and from which the high-frequency component has been removed by the LPF 12, and the VCO 17
To enter. When the clock is asynchronous,
The output from the memory circuit 14 and the D / A conversion circuit 15
The control voltage that has been / A converted is output and input to the VCO 17.

The oscillation frequency of the VCO 17 is controlled by a control voltage output from the selection circuit 16, and an output clock is input to the frequency dividing circuit 22. The dividing circuit 22 has a VC
The output clock of O17 is frequency-divided by N and output, and input to the phase comparison circuit 21.

[0011]

In the above-mentioned prior art, after a fault occurs in the input clock and becomes asynchronous with the VCO output clock, the fault state of the input clock is resolved and the input clock returns to the normal state. However, there is a problem that the VCO output clock remains controlled by the control voltage stored in the memory, and the VCO output clock is not synchronized with the input clock.

The reason is that when a failure occurs in the input clock and it becomes asynchronous with the VCO output clock,
Since the phase locked loop forms an open loop, the VCO output clock cannot follow the input clock. Even if the input clock returns to the normal state in this state, the phase locked loop remains open because there is no trigger to close the loop of the phase locked loop, and the input clock and the VCO output clock remain asynchronous. Because.

In view of the above, the present invention provides a method for controlling a VC when a failure occurs in an input clock and the input clock returns to a normal state after the phase locked loop circuit is once in an asynchronous state.
It is an object of the present invention to suppress the fluctuation of the oscillation frequency of the O output clock and to establish the synchronization state of the phase synchronization circuit by the input clock in a short time.

[0014]

In order to achieve the above object, a phase synchronization circuit according to the present invention comprises a phase comparison circuit, a low-pass filter, an A / D conversion circuit, a memory circuit, and a D / A converter.
A phase synchronization circuit including a conversion circuit, a selection circuit, a voltage controlled oscillator, and a frequency division circuit, including a clock failure detection circuit and a control voltage comparison circuit, wherein the phase comparison circuit includes an input clock, An output clock of the voltage controlled oscillator divided by the divider circuit is input, and a phase difference between the input clock and the divided output clock is detected.
A control voltage corresponding to the phase difference is output and input to the low-pass filter, and the clock failure detection circuit inputs the input clock and detects the state of the input clock, and the state of the input clock is normal. , A failure detection signal in the first state is output and input to the memory circuit and the selection circuit, and if the state of the input clock indicates a failure state, the second state is detected. Is output to the memory circuit and the selection circuit, and the low-pass filter receives a control voltage output from the phase comparison circuit and removes a high-frequency component of the control voltage. And outputs a first control voltage, and inputs the first control voltage to the A / D conversion circuit and the selection circuit,
The A / D conversion circuit converts the first control voltage of an analog value to a digital value and outputs a second control voltage, and outputs the second control voltage to the memory circuit and the control voltage comparison circuit. When the fault detection signal output from the clock fault detection circuit is in the first state, the memory circuit inputs the second control voltage and stores the second control voltage at predetermined time intervals. When the detection signal is in the second state, a third control voltage of a digital value currently stored in the memory circuit is output and input to the D / A conversion circuit, and the state of the input clock is temporarily disabled. When the normal state is indicated after the state, the third control voltage is output and input to the control voltage comparison circuit, and the D / A conversion circuit performs the third control of the digital value. Convert voltage to analog value A fourth control voltage output Te, fourth
Is input to the selection circuit, and the selection circuit
When the failure detection signal output from the clock failure detection circuit is in the first state, the first control voltage is selected and input to the voltage controlled oscillator, and when the failure detection signal is in the second state. In some cases, the fourth control voltage is selected and input to the voltage-controlled oscillator, and when the state of the input clock indicates a normal state after a failure state, the control voltage comparison circuit According to the result, the first or fourth control voltage is selected and input to the voltage controlled oscillator, and the control voltage comparison circuit inputs the second control voltage and the third control voltage. Comparing the second control voltage with the third control voltage to determine whether the second control voltage is equal to the third control voltage. When the second control voltage is equal to the third control voltage, the phase of the input clock is Output clock of voltage controlled oscillator Is notified to the clock failure detection circuit that the phase becomes equal to the synchronized state. When the second control voltage is not equal to the third control voltage, the circuit is controlled by the fourth control voltage. After controlling the phase of the output clock of the voltage controlled oscillator by the frequency divider circuit, the second control voltage and the third control voltage are input again and compared for equality, and the voltage control is performed. An oscillation frequency of an output clock is controlled by a first or fourth control voltage selected and output by the selection circuit,
The controlled output clock is output and input to the frequency dividing circuit, and the frequency dividing circuit divides and outputs the output clock of the voltage controlled oscillator and inputs the output clock to the phase comparison circuit.

[0015]

According to the present invention, the selection of the VCO control voltage of the phase locked loop circuit is detected by the phase comparing circuit detecting whether the input clock and the VCO output clock are in a synchronized state or in an asynchronous state. Instead, it is performed by detecting whether the input clock is in a normal state or in a failure state using a clock failure detection circuit and a control voltage comparison circuit.

Therefore, when the input clock is in a normal state, the VCO control voltage is stored in the memory circuit, and when a failure occurs in the input clock, the VCO control voltage of the stored memory circuit is output in the normal state to output the VCO. Since the control is performed, it is possible to output a stable VCO output clock equivalent to the case where the input clock is in a normal state. Thereafter, when the input clock recovers from the failure state and returns to the normal state, the VCO control voltage output from the memory circuit and the VCO control voltage output from the phase comparison circuit (according to the input clock) become equal to each other. The phase of the output clock is controlled, and when the respective control voltages become equal, the VCO control voltage output from the memory circuit is switched (by the input clock) to the VCO control voltage output from the phase comparison circuit to output the VCO. Since the phase of the clock is controlled, fluctuations in the oscillation frequency of the VCO output clock can be suppressed regardless of the state of the input clock, and a stable VCO output clock without frequency fluctuation can be output. Can be established in a short time.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a phase locked loop circuit according to one embodiment of the present invention. FIG. 2 is a flowchart illustrating a phase synchronization method according to an embodiment of the present invention.

[A] Description of Configuration First, the configuration of an embodiment of the present invention will be described with reference to FIG.

The phase synchronization circuit shown in FIG. 1 includes a phase comparison circuit 11, an LPF 12, an A / D conversion circuit 13, a memory circuit 14, a D / A conversion circuit 15, a selection circuit 16
, A VCO 17, a frequency dividing circuit 18, a clock failure detecting circuit 19, and a control voltage comparing circuit 20.

The phase comparator 11 receives the input clock and the output clock of the VCO 17 frequency-divided by the frequency divider 18 to detect a phase difference, and outputs a VCO control voltage corresponding to the phase difference. Input to LPF12.

The clock failure detection circuit 19 receives an input clock and detects its state. Then, when the input clock is in a normal state, a failure detection signal A is output. When the input clock is in a failure state,
The failure detection signal B is output. The output failure detection signals A and B are both stored in the memory circuit 14 and the selection circuit 16.
Is input to

The LPF 12 receives a control voltage output from the phase comparison circuit 11, removes high-frequency components thereof, outputs a control voltage a, and outputs an A / D conversion circuit 13 and a selection circuit 1
Enter 6

The A / D conversion circuit 13 converts the control voltage a having an analog value into a digital value, outputs a control voltage b, and inputs the control voltage b to the memory circuit 14 and the control voltage comparison circuit 20.

When the input clock is in a normal state (when the failure detection signal A is being output), the memory circuit 14 receives the control voltage b and stores it at a predetermined timing. When a failure occurs in the input clock (when the failure detection signal B is output), the latest control voltage c stored in advance in the memory circuit 14 is output and input to the D / A conversion circuit 15. . Further, when the input clock has returned to the normal state after a fault has occurred once, the control voltage c is output and input to the control voltage comparison circuit 20.

The D / A conversion circuit 15 converts the digital control voltage c output from the memory circuit 14 into an analog value, outputs a control voltage d, and inputs the control voltage d to the selection circuit 16.

The selection circuit 16 includes the clock failure detection circuit 1
The state of the input clock is determined based on the failure detection signal output from the controller 9 and the control voltage input to the VCO 17 is selected. When the input clock is in a normal state (when the failure detection signal A is output), the control voltage a is selected and input to the VCO 17. When a failure occurs in the input clock (when the failure detection signal B is output), the control voltage d is selected and input to the VCO 17.
Further, when the input clock has returned to a normal state after a fault has occurred once, the control voltage a or the control voltage d is selected according to the comparison result of the control voltage comparison circuit 20, and the VCO is selected.
Enter 17.

The control voltage comparison circuit 20 receives the control voltage b output from the A / D conversion circuit 13 and the control voltage c output from the memory circuit 14. Then, when the normal state is restored after the input clock is once in the fault state, it is compared whether or not the control voltage b is equal to the control voltage c. When the control voltage b and the control voltage c are equal,
The clock failure detection circuit 19 is notified that the phase of the input clock and the phase of the output clock of the VCO 17 have become equivalent to the synchronized state. If the control voltage b and the control voltage c are not equal, VC controlled by the control voltage d
After the phase of the output clock of O17 is controlled by the frequency dividing circuit 18, the control voltage b and the control voltage c are input again and compared.

The oscillation frequency of the output clock of the VCO 17 is controlled by the control voltage a or the control voltage d selected and output by the selection circuit 16. The controlled output clock is input to the frequency dividing circuit 18.

The frequency dividing circuit 18 controls the phase according to the information output from the control voltage comparing circuit 20 and
Is output by dividing the output clock of N by N.
To enter.

[B] Description of Operation Next, the operation of one embodiment of the present invention will be described with reference to FIGS.

An input clock to be synchronized by the phase synchronization circuit is input to the phase comparison circuit 11 and the clock failure detection circuit 19. Further, the output clock of the VCO 17 for synchronizing is divided by N by the frequency dividing circuit 18 according to the frequency of the input clock, and is input to the phase comparing circuit 11 (S2).
01).

The phase comparison circuit 11 compares the phase between the input clock and the clock divided by N, outputs a VCO control voltage corresponding to the phase difference, and inputs it to the LPF 12 (S202).

The VCO control voltage output from the phase comparison circuit 11 is passed through the LPF 12 to remove high frequency components and output as a control voltage a. Control voltage a
Is input to the A / D conversion circuit 13 and the selection circuit 16 (S203).

The clock failure detecting circuit 19 detects the state of the input clock (S204).

Then, when the input clock is in a normal state, a failure detection signal A is output (S211). Further, when the input clock is in the failure state, the failure detection signal B is output (S221). Both of the failure detection signals A and B
Input to the memory circuit 14 and the selection circuit 16.

When the clock failure detection circuit 19 determines that the input clock is in a normal state (when the failure detection signal A is being output), the control voltage a from which the high-frequency component has been removed by the LPF 12 is applied to the selection circuit. 16 and input to the VCO 17 (S212). Selection circuit 16
The oscillation frequency of the output clock of the VCO 17 is controlled using the control voltage a selected in the step S1 and input to the VCO 17, and the controlled output clock is input to the frequency dividing circuit 18 (S213). Further, in order to cope with the case where a failure occurs in the input clock, the control voltage a from which the high-frequency component has been removed by the LPF 12 is input to the A / D conversion circuit 13 and converted into a digital value to output the control voltage b. Then, the data is input to the memory circuit 14. The control voltage b of the digital value input to the memory circuit 14 is stored at a predetermined timing (S214).
After that, S201 and subsequent steps are repeated.

When the clock failure detection circuit 19 determines that the input clock is in a failure state (when the failure detection signal B is being output), the digital value stored in the memory circuit 14 is stored in the normal state. The control voltage c is output, input to the D / A conversion circuit 15, converted to an analog value, output the control voltage d, and input to the selection circuit 16 (S222). The control voltage d output from the D / A conversion circuit 15 is selected by the selection circuit 16 and input to the VCO 17 (S223). VCO1 selected by the selection circuit 16
The oscillation frequency of the output clock of the VCO 17 is controlled by using the control voltage d input to 7 and the controlled output clock is input to the frequency dividing circuit 18 (S224). At this time,
The control voltage c output from the memory circuit 14 is selected when fault information is received by the fault detection signal B output from the clock fault detection circuit 19,
Is the control voltage stored. After that, S201 and subsequent steps are repeated.

When it is determined that the input clock has recovered from the faulty state to the normal state, the control voltage b output from the A / D conversion circuit 13 and the control voltage c output from the memory circuit 14 are compared with the control voltage comparison circuit. 20 (S2
32), and whether or not they are equal is compared (S233).

When the control voltage b is not equal to the control voltage c, the VCO 17 controlled by the control voltage d
Is controlled by the frequency dividing circuit 18 (S
234). Then, S233 and subsequent steps are repeated again.

When the control voltage b is equal to the control voltage c, the control voltage b output from the A / D conversion circuit 13 becomes equal to the control voltage c output from the memory circuit 14, ie, the phase of the input clock is The clock failure detection circuit 19 is notified that the phase of the output clock of the VCO 17 has become equal to the synchronous state (S235). After that, S204 and subsequent steps are repeated based on the result of S235.

That is, if the input clock is in a normal state in S204, the clock failure detection circuit 19 outputs a failure detection signal A indicating that the input clock is in a normal state.
Is output to the memory circuit 14 and the selection circuit 16 (S211), and the selection circuit 16 selects the control voltage a output from the LPF 12 (phase comparison circuit 11) as the VCO control voltage, and outputs the control voltage to be output. The control voltage d is switched to the control voltage a and input to the VCO 17 (S21).
2).

[0042]

As described above, the present invention has the following effects.

When the input clock is in a normal state, the VCO
The control voltage is stored in the memory circuit, and when a failure occurs in the input clock, the VCO control voltage of the stored memory circuit is output when the input clock is in a normal state and the VCO is controlled, so that the input clock is equivalent to that in the normal state. Has the effect that a stable VCO output clock can be output.

Thereafter, when the input clock recovers from the fault state and returns to the normal state, the VCO control voltage output from the memory circuit and the VCO control voltage output from the phase comparison circuit (according to the input clock) become equal. The phase of the VCO output clock is controlled as described above, and when the respective control voltages become equal, the VCO control voltage output from the memory circuit is switched to the VCO control voltage output from the phase comparison circuit (by the input clock). V
By controlling the phase of the CO output clock, fluctuations in the oscillation frequency of the VCO output clock are suppressed regardless of the state of the input clock, and a VCO that is always stable and has no frequency fluctuation
This has an effect that an output clock can be output, and an effect that a synchronization state by an input clock of the phase locked loop can be established in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a phase locked loop circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a phase synchronization method according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional phase locked loop circuit;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Phase comparison circuit 12 Low-pass filter (LPF) 13 A / D conversion circuit 14 Memory circuit 15 D / A conversion circuit 16 Selection circuit 17 Voltage controlled oscillator (VCO) 18 Divider circuit 19 Clock fault detection circuit 20 Control voltage comparison circuit 21 Phase comparator circuit 22 Divider circuit

Claims (2)

(57) [Claims] A phase comparison circuit, a low-pass filter,
An A / D conversion circuit, a memory circuit, a D / A conversion circuit,
A phase synchronization circuit including a selection circuit, a voltage controlled oscillator, and a frequency dividing circuit, comprising: a clock fault detecting circuit; and a control voltage comparing circuit, wherein the phase comparing circuit divides an input clock by the frequency dividing circuit. The output clock of the divided voltage controlled oscillator is input, a phase difference between the input clock and the divided output clock is detected, and a control voltage corresponding to the phase difference is output to output the low-pass signal. Input to the filter, the clock failure detection circuit receives the input clock, detects the state of the input clock, and detects a failure in the first state when the state of the input clock indicates a normal state. A detection signal is output and input to the memory circuit and the selection circuit, and when the state of the input clock indicates a failure state, a failure detection signal in a second state is output to output the detection signal. Input to the memory circuit and the selection circuit, the low-pass filter inputs a control voltage output from the phase comparison circuit, removes a high-frequency component of the control voltage, and outputs a first control voltage; The first control voltage is set to A
/ D conversion circuit and the selection circuit, wherein the A / D conversion circuit converts the first control voltage of an analog value into a digital value and outputs a second control voltage, and outputs the second control voltage. A control voltage is input to the memory circuit and the control voltage comparison circuit, and the memory circuit outputs the second control voltage when a failure detection signal output from the clock failure detection circuit is in the first state. The memory circuit inputs and stores the data at a predetermined time interval. When the failure detection signal is in the second state, the digital circuit outputs a third control voltage of a digital value currently stored in the memory circuit to perform the D / A conversion. When the state of the input clock indicates a normal state after the state of the input clock once becomes a failure state, the third control voltage is output and input to the control voltage comparison circuit; A conversion circuit is digital Converting the third control voltage into an analog value to output a fourth control voltage, inputting the fourth control voltage to the selection circuit, wherein the selection circuit is output from the clock failure detection circuit When the failure detection signal is in the first state, the first control voltage is selected and input to the voltage controlled oscillator. When the failure detection signal is in the second state, the fourth control voltage is selected. Is selected and input to the voltage-controlled oscillator, and when the state of the input clock indicates a normal state after the state of the input clock has once changed to the fault state, the first or the second state is determined according to the comparison result of the control voltage comparison circuit. A fourth control voltage is selected and input to the voltage controlled oscillator. The control voltage comparison circuit inputs the second control voltage and the third control voltage, and outputs the second control voltage and the third control voltage. The third
And if the second control voltage is equal to the third control voltage, the phase of the input clock is synchronized with the phase of the output clock of the voltage controlled oscillator. Notifying the clock fault detection circuit that the state has become equal to the state, and when the second control voltage is not equal to the third control voltage, the voltage control controlled by the fourth control voltage is performed. After controlling the phase of the output clock of the oscillator by the frequency divider circuit, the second control voltage and the third control voltage are input again and compared for equality. The oscillation frequency of the output clock is controlled by the first or fourth control voltage selected and output by the circuit, and the controlled output clock is output and input to the frequency dividing circuit. , The voltage control Outputs the output clock of the oscillator by dividing, and wherein the input to the phase comparator circuit, a phase synchronization circuit. 2. An output clock of a voltage controlled oscillator is set to a predetermined value.
Generates a clock divided by the division ratio, and generates the divided clock.
Phase of the first analog control power
And the voltage is generated by the first analog control voltage.
Uses a phase-locked loop to control the output frequency of the pressure-controlled oscillator
In the phase synchronization method, the state of the input clock is detected, the first analog control voltage is A / D-converted, and the first digital
Control voltage is generated, and the input clock is normal.
The voltage controlled oscillation by the first analog control voltage.
Control the instrument and note the first digital control voltage.
When an input clock failure occurs, the
The second control voltage, which is the latest control voltage stored in the memory circuit,
Outputting a digital control voltage from the memory circuit;
D / A conversion of the digital control voltage into a second analog control voltage.
Voltage and control the voltage with a second analog control voltage
Controls the oscillator and restores the normal state after the input clock has failed.
When old, the first digital control voltage and the second digital control voltage
Whether the voltage is equal to the digital control voltage,
When the digital control voltage is equal to the second digital control voltage.
Controls the voltage controlled oscillator by the first analog control voltage.
Controlling a first digital control voltage and a second digital control
If the voltage is not equal to the second analog control voltage
Therefore, the first digital signal generated by controlling the voltage controlled oscillator
The digital control voltage and the second digital control voltage, and
Of the first digital control voltage and the second digital control voltage
Controls the frequency division ratio in the direction that makes it equal to the digital control voltage
And a first digital control voltage and a second digital control voltage
Until the first digital control voltage and the second digital control voltage
Comparison with digital control voltage and frequency division based on the comparison result
A phase synchronization method characterized by repeating a process of controlling a ratio .