JP2000299637A - Phase-locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To oscillate a voltage controlled oscillator(VCO) with a frequency and a phase at the time of synchronizing even when a reference frame signal is abnormal. SOLUTION: When a frame signal 22 is normal, a switch 7 is connected to the side of a low-pass filter 106 and a VCO 108 is oscillated at the frequency synchronized to the frame signal 22 by feedback control. In the state of weakening a received radio wave and making the frame signal 22 abnormal, since the voltage of an RSSI signal 21 expressing radio wave strength is lowered as well, the output signal of a comparator 10 is inverted, the switch 7 is connected to the side of a voltage storage part 12 and a switch 13 is turned off. As a result, a control voltage stored in the voltage storage part 12 at normal time is supplied to the VCO 108 and the VCO 108 continuously oscillates at the same frequency and phase as the normal time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a phase synchronization circuit which is incorporated in a communication device or the like and generates a clock signal synchronized with a reference frame signal.

[0002]

2. Description of the Related Art In digital data transmission between devices each having an independent timing generation function, a phase-locked loop is used because both devices operate synchronously. When transmitting data between two devices, generally,
The reference side is a master device (also simply referred to as a master) and the other side is a slave device (also simply referred to as a slave). It operates to synchronize the frame signal as needed. Here, the device includes not only a single device but also a circuit block and the like provided in one device.

FIG. 3 is a circuit diagram showing an example of a conventional phase locked loop circuit. In the phase locked loop 103 shown in FIG. 3, the phase comparator 105 outputs the frame signal 122 and the frequency divider 109
And outputs a signal of a voltage corresponding to the phase difference. FIGS. 4A to 4C are waveform diagrams showing the relationship between two input signals and output signals in the phase comparator 105. FIG.

FIG. 4A shows a case where the phase of the output signal 109A of the frequency divider 109 is delayed with respect to the frame signal 122. At this time, the phase comparator 105 detects the rising edge of the frame signal 122. At this timing, a pulse signal that is at a high level with respect to the reference level for a period corresponding to the phase difference is output as the output signal 105A. On the other hand, FIG.
(B) shows that the frequency divider 109
This shows a case where the phase of the output signal 109A is advanced, and at this time, the phase comparator 105 outputs a low level with respect to the reference level for a period corresponding to the phase difference at the rising timing of the output signal 109A of the divider 109. A pulse signal which becomes a level is output as an output signal 105A. FIG. 4C shows a case where the phase of the frame signal 122 matches the phase of the output signal 109A of the frequency divider 109. At this time, the phase comparator 105 outputs the reference level DC output signal. 105A is output. From the output signal of such a phase comparator 105, only a low frequency component is extracted and smoothed by a low-pass filter (LPF) 106 and input to a voltage controlled oscillator 108.

FIG. 5 is a graph showing the relationship between the control voltage and the oscillation frequency in the voltage controlled oscillator 108. In the figure,
The horizontal axis represents the control voltage, and the vertical axis represents the oscillation frequency. A straight line 108A indicates the relationship between the control voltage and the oscillation frequency, and a proportional relationship is established in which the oscillation frequency increases as the control voltage increases.

The output signal of the voltage controlled oscillator 108 is used as a clock signal in the subsequent stage, and at the same time, the frequency divider 109
And is fed back to the phase comparator 105. With such feedback control, the phase locked loop 103 is balanced and in a synchronized state in a state where the phase difference is eliminated at the input of the phase comparator 105, and the clock signal 123 synchronized with the frame signal 122 is output from the voltage controlled oscillator 108. Is output.

By the way, the phase locked loop 10 shown in FIG.
In 3, if the frame signal 122 stops for some reason, the phase comparator 105 outputs a signal that goes low every time the output signal of the frequency divider 109 rises. As a result, the voltage controlled oscillator 108 Oscillation. Therefore, when the frame signal 122 is stopped, the frequency of the clock signal 123 is significantly different from that in the case where synchronization is achieved.

Then, when the frame signal 122 returns to the normal state thereafter, the frequency difference between the two input signals of the phase comparator 105 is very large immediately after the return, and until the synchronization is established again, It takes a long time, during which time the regular clock signal 123 is not supplied to the subsequent stage, and therefore, even if the frame signal 122 becomes normal, the latter stage cannot immediately operate in its original state.

Japanese Unexamined Patent Publication No. Sho 60-194850 discloses a phase locked loop configured to solve such a problem. FIG. 6 is a block diagram showing a conventional phase synchronization circuit designed to reduce the time required for establishing synchronization after such a frame signal recovery. In the figure, phase comparator 2
05, low-pass filter 206, voltage-controlled oscillator 20
8, the frequency divider 209 includes the phase comparator 105 shown in FIG.
The low-pass filter 106, the voltage-controlled oscillator 108, and the frequency divider 109 perform basically the same functions. In the phase locked loop 203 shown in FIG. 6, a switch 207 and a voltage detection unit 214 are provided in a stage preceding the voltage controlled oscillator 208. In a state synchronized with the frame signal 222, the control voltage of the voltage controlled oscillator 208 is stable near the intermediate voltage. On the other hand, when the frame signal 222 stops, the control voltage greatly deviates from the intermediate voltage. The voltage detection unit 214 detects that synchronization has been lost by monitoring the voltage change. When detecting the loss of synchronization, the voltage detection unit 214 switches the switch 207 and supplies the voltage from the reference voltage source 212 to the voltage controlled oscillator 208 as a control voltage.

The voltage of the reference voltage source 212 is set to the above-mentioned intermediate voltage. Therefore, even if the synchronization is lost, the voltage-controlled oscillator 208 performs free-running oscillation at a frequency close to the case where the synchronization is established. The signal 223 is supplied to the subsequent stage. Further, even when the frame signal 222 returns to the normal state, the time required until the synchronization is re-established is short because the frequency difference between the two input signals of the phase comparator 205, that is, the phase difference is relatively small. Further, as described above, even when the frame signal 222 stops, the voltage-controlled oscillator 208 oscillates at a frequency close to the case where synchronization is established. Even when the signal 222 is stopped, the operation can be continued in a state close to the normal state.

[0011]

However, in such a conventional phase locked loop circuit 203, the reference frame signal 222
The frequency of the reference voltage source 212 contains an error, and the relationship between the control voltage and the oscillation frequency in the voltage controlled oscillator 208 varies among the voltage controlled oscillators 108. Even if it is set, it is difficult to match the voltage to the control voltage supplied to the voltage controlled oscillator 208 in a state where the voltage controlled oscillator 208 is oscillating synchronously in an actual device. Therefore, it is difficult to match the oscillation frequency of voltage-controlled oscillator 208 in the synchronized state with the oscillation frequency of voltage-controlled oscillator 208 in the state of free-running oscillation by the voltage from reference voltage source 212. The present invention has been made to solve such a problem, and a main object of the present invention is to cause a voltage-controlled oscillator to accurately oscillate at a frequency and a phase at the time of synchronization establishment even when a reference frame signal becomes abnormal. It is an object of the present invention to provide a phase-locked loop circuit capable of performing the above.

[0012]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention comprises a slave device for receiving a reference frame signal from a master device and transmitting / receiving a digital signal to / from the master device, And a frequency divider for dividing the clock signal generated by the voltage controlled oscillator, and generating and controlling a voltage representing a phase difference between the reference frame signal and an output signal of the frequency divider. A phase synchronization circuit configured to include a phase comparison unit that supplies the voltage as a voltage to the voltage controlled oscillator, wherein the voltage detection unit detects the control voltage supplied to the voltage controlled oscillator, and the voltage detection unit includes Voltage storage means for storing the detected control voltage; and a storage system for controlling whether the control voltage detected by the voltage detection means is stored in the voltage storage means. Means, switching means for supplying one of the control voltage output from the phase comparison means and the control voltage stored in the voltage storage means to the voltage controlled oscillator, and output from the master device. ,
Based on an identification signal indicating whether the reference frame signal is normal or not, when the reference frame signal is normal, controls the switching means and supplies the control voltage output from the phase comparison means to the voltage controlled oscillator. And controlling the storage control means to store the control voltage detected by the voltage detection means in the voltage storage means, while controlling the switching means when the reference frame signal is abnormal. Control voltage control means for supplying the control voltage stored in the voltage storage means to the voltage controlled oscillator, and controlling the storage control means to stop storing the control voltage in the voltage storage means. It is characterized by having.

In the phase locked loop circuit of the present invention, when the reference frame signal is normal, the control voltage control means controls the switching means to supply the control voltage output from the phase comparison means to the voltage controlled oscillator, and stores the control voltage. The control means is controlled to store the control voltage detected by the voltage detection means in the voltage storage means. Therefore, in this state, the voltage controlled oscillator oscillates at a frequency corresponding to the control voltage from the phase comparing means, and outputs a signal synchronized with the reference frame signal. Then, the control voltage supplied to the voltage controlled oscillator is detected by the voltage detecting means, and stored in the voltage storing means by the storage controlling means.

On the other hand, when the reference frame signal becomes abnormal, the control voltage control means controls the switching means to supply the control voltage stored in the voltage storage means to the voltage controlled oscillator, and To stop storing the control voltage in the voltage storage means. Therefore, in this state, the voltage controlled oscillator oscillates at a frequency corresponding to the control voltage stored in the voltage storage means. At this time, the control voltage stored in the voltage storage means is the voltage actually supplied from the phase comparison means to the voltage controlled oscillator in a state where synchronization is established immediately before the reference frame signal becomes abnormal. Therefore, the voltage controlled oscillator oscillates at the same frequency and the same phase as immediately before the reference frame signal becomes abnormal.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a phase locked loop according to the present invention, and FIG. 2 is a configuration diagram showing a communication system incorporating the phase locked loop of FIG.
In FIG. 1, the same elements as those in FIG. 3 are denoted by the same reference numerals. First, the communication system of FIG. 2 will be described. This communication system 300 uses a wireless local wireless link (WLL) that uses wireless communication for a part of a telephone line between a telephone network 307 and a telephone 306.
(op) system, in which the radio mobile station 302 performs radio communication with the radio base station 301 and the telephone network 307 and the telephone 30
6, a communication path is secured.

The radio mobile station 302 is roughly composed of a modulation / demodulation unit 1, a data transmission unit 2, and a line interface 305. The present embodiment relates to data transmission between the modem unit 1 and the data transmission unit 2, wherein the modem unit 1 corresponds to the master device of the present invention, and the data transmission unit 2 corresponds to the slave device of the present invention. . Digitized data such as voice is transmitted and received between the modem unit 1 and the data transmission unit 2. The modem unit 1 has a function of acquiring timing from wireless communication with the wireless base station 301. The data transmission unit 2 has a unique timing generation function for performing mutual communication with the modem unit 1.

As shown in FIG. 1, the modem unit 1 transmits data 18 (TX_DATA) such as voice to the data transmission unit 2, while transmitting data 19 (RX_DAT) such as voice.
A) is received from the data transmission unit 2. Also, the modulation / demodulation unit 1
Is the clock signal 20 (M
_CLK; the frequency is, for example, 128 KHz) and the reference frame signal 22 (M_FLM; the frequency is, for example, 8 KHz) is supplied to the data transmission unit 2. The data transmission unit 2 includes the phase synchronization circuit 3 of the present embodiment in order to synchronize its own timing with the frame signal 22 from the modulation / demodulation unit 1. The phase synchronization circuit 3 generates a clock signal 23 (CLK) synchronized with the frame signal 22 and supplies the clock signal 23 (CLK) to the subsequent timing correction unit 4. The frequency divider 15 and the frequency divider 16 in the timing correction unit 4 use a clock signal 24 (S_CLK; frequency is, for example, 8 KHz) used for data transmission in the data transmission unit 2 from a clock signal 23, and a frame signal 25 (S_FLM; Frequency is 128K, for example
Hz). The clock signal 23 output from the voltage controlled oscillator 108 is also supplied to the other processing circuits 17, and the processing circuit 17 performs a predetermined operation based on the timing of the clock signal 23.

The phase synchronization circuit 3 includes a phase comparator 105, a low-pass filter 106, a voltage controlled oscillator 108, and a frequency divider 109 (for example, frequency-divided into 1/1536) as basic components for establishing frame synchronization. I have.
Since these have already been described, the description is omitted here.

The phase-locked loop 3 further includes a reference voltage source 11, a comparator 10,
It includes a switch 7, a voltage detection unit 14, a switch 13, and a voltage storage unit 12. The reference voltage source 11 and the comparator 10 constitute control voltage control means according to the present invention. The reference voltage source 11 outputs a preset voltage, and the comparator 10 compares the output voltage of the reference voltage source 11 with the output voltage of the reference voltage source 11. , RSSI (Received) supplied from the modem unit 1
(Signal Indicator) signal 21 and outputs a high-level signal and a low-level signal indicating a magnitude relationship. Switch 7 that constitutes switching means of the present invention, and switch 1 that constitutes storage control means of the present invention
3 is controlled by the output signal of the comparator 10. The voltage detector 14 sequentially detects the control voltage of the voltage controlled oscillator 8, and supplies the detection result to the voltage storage 12 through the switch 13.

Next, the operation of the phase locked loop circuit 3 of this embodiment will be described in detail. When the radio mobile station 302 shown in FIG. 2 receives a radio wave from the radio base station 301, the modem 1 detects the intensity of the received radio wave and generates a voltage indicating the intensity of the radio wave. . The higher the voltage, the stronger the received radio wave, and the lower the voltage, the weaker the radio wave. The modulation / demodulation unit 1 outputs this voltage to the data transmission unit 2 as an RSSI signal 21. When the radio wave becomes weaker than a certain level, the modulation / demodulation unit 1 cannot perform normal demodulation.
Becomes abnormal. The voltage output by the reference voltage source 11 of the data transmission unit 2 is R just before the frame signal 22 becomes abnormal.
It is set to a value substantially equal to the voltage of the SSI signal 21.

The comparator 10 constantly compares the voltage from the reference voltage source 11 with the voltage of the RSSI signal 21.
When (the voltage of the RSSI signal 21)> (the voltage of the reference voltage source 11) holds, for example, a high-level signal is output, and the switch 7 is connected to the low-pass filter side.
The switch 13 is turned on. Therefore, in this case, the voltage controlled oscillator 108
It oscillates at a frequency based on the voltage from 06, and the voltage control oscillator 108 outputs a clock signal 23 (frequency is, for example, 12288 KHz) synchronized with the reference frame signal 22 by the feedback control similar to the related art. Then, the control voltage of the voltage controlled oscillator 108 detected by the voltage detection unit 14 is supplied to the voltage storage unit 12 through the switch 13 and stored in the voltage storage unit 12.

Here, assuming that the radio mobile station is placed in, for example, a poor radio wave environment and cannot receive radio waves of sufficient intensity at the radio mobile station, before the reference frame signal 22 is completely stopped, The voltage of the RSSI signal 21 decreases, and (voltage of the RSSI signal 21) ≦ (reference voltage source 11
Voltage) is established. At this time, the comparator 10
Outputs a low-level signal, for example, contrary to the above case, the switch 7 is connected to the voltage storage unit 12 side, and the switch 13 is set to the off state.

Therefore, in this case, the voltage controlled oscillator 108 oscillates at a frequency based on the voltage stored in the voltage storage unit 12. At this time, the control voltage stored in the voltage storage unit 12 is actually supplied from the phase comparator 105 to the voltage controlled oscillator 108 in a state where synchronization is established immediately before the reference frame signal 22 becomes abnormal. Voltage, the voltage-controlled oscillator 108
Oscillates at the same frequency and the same phase as immediately before the reference frame signal 22 becomes abnormal.

Therefore, in the present embodiment, even when the reference frame signal 22 becomes abnormal, the processing circuit 17 and the timing correction section 4 can continue operation at regular timing without interruption.

After that, when the radio wave environment around the radio mobile station is improved so that radio waves of sufficient intensity can be received, the modulation / demodulation unit 1 sets the R of a voltage exceeding the output voltage of the reference voltage source 11.
An SSI signal 21 is output, and a normal reference frame signal 22 is output. At this time, (R
Since the relationship of (voltage of the SSI signal 21)> (voltage of the reference voltage source 11) is satisfied, the switch 7 is returned to the low-pass filter side by the output signal of the comparator 10, and the switch 13 is also returned to the ON state. Therefore, the voltage controlled oscillator 108
Oscillates at a frequency based on the voltage from the low-pass filter 106, and outputs a clock signal 23 synchronized with the reference frame signal 22 in a state where the feedback control is performed.

Then, the phase synchronization circuit 3 of this embodiment
Then, when the reference frame signal becomes abnormal, the voltage controlled oscillator 108 oscillates at the same frequency and the same phase as immediately before the reference frame signal 22 becomes abnormal, as described above.
When the reference frame signal 22 returns to the original state, there is almost no difference between the phase of the output signal (clock signal 23) of the voltage controlled oscillator 108 and the phase of the reference frame signal 22, and synchronization is re-established in a short time. Can be.

[0027]

As described above, in the phase locked loop circuit of the present invention, when the reference frame signal is normal, the control voltage control means controls the switching means to control the control voltage output from the phase comparison means. The voltage is supplied to the oscillator, and the storage control means is controlled to store the control voltage detected by the voltage detection means in the voltage storage means. Therefore, in this state, the voltage controlled oscillator oscillates at a frequency corresponding to the control voltage from the phase comparing means, and outputs a signal synchronized with the reference frame signal. Then, the control voltage supplied to the voltage controlled oscillator is detected by the voltage detecting means, and stored in the voltage storing means by the storage controlling means.

On the other hand, when the reference frame signal becomes abnormal, the control voltage control means controls the switching means to supply the control voltage stored in the voltage storage means to the voltage controlled oscillator, and To stop storing the control voltage in the voltage storage means. Therefore, in this state, the voltage controlled oscillator oscillates at a frequency corresponding to the control voltage stored in the voltage storage means. At this time, the control voltage stored in the voltage storage means is the voltage actually supplied from the phase comparison means to the voltage controlled oscillator in a state where synchronization is established immediately before the reference frame signal becomes abnormal. Therefore, the voltage controlled oscillator oscillates at the same frequency and the same phase as immediately before the reference frame signal becomes abnormal.

As a result, in the phase locked loop circuit of the present invention, even when the reference frame signal is stopped, the subsequent circuit that operates using the output signal of the voltage controlled oscillator as the timing reference should continue operation at regular timing. Can be. Then, when the reference frame signal returns to the original normal state, the phase of the output signal of the voltage controlled oscillator and
There is almost no phase difference from the reference frame signal, and synchronization can be re-established in a very short time. Further, when the identification signal is a signal indicating the strength of the received radio wave, the control unit switches the control voltage before the reference frame signal is completely stopped by detecting that the received radio wave is weakened by the identification signal. be able to. In that case, even if the reference frame signal becomes abnormal, the voltage controlled oscillator continues to oscillate at the normal frequency and phase without any interruption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a phase locked loop according to the present invention.

FIG. 2 is a configuration diagram showing a communication system in which the phase synchronization circuit of FIG. 1 is incorporated.

FIG. 3 is a circuit diagram illustrating an example of a conventional phase locked loop circuit.

FIGS. 4A to 4C are waveform diagrams showing the relationship between two input signals and an output signal in a conventional phase comparator.

FIG. 5 is a graph showing a relationship between a control voltage and an oscillation frequency in a voltage controlled oscillator.

FIG. 6 is a block diagram showing a conventional phase locked loop circuit designed to reduce the time required for establishing synchronization after returning from a frame signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Modulation / demodulation part, 2 ... Data transmission part, 3 ... Phase synchronization circuit, 7 ... Switch, 10 ... Comparator, 11 ... Reference voltage source, 12 ... Voltage storage part, 13 ... Switch, 14
... Voltage detector, 15 frequency divider, 16 frequency divider, 1
7 Processing circuit 103 Phase synchronization circuit 105
Phase comparator, 106 ... Low-pass filter, 108 ...
Voltage-controlled oscillator, 109 frequency divider, 122 frame signal, 203 phase-locked loop, 207 switch, 208 voltage-controlled oscillator, 212 reference voltage source, 214 voltage detector, 300 ... Communication system,
301 ... wireless base station, 305 ... line interface, 306 ... telephone, 307 ... telephone network.

Claims (6)

[Claims] A voltage-controlled oscillator that is incorporated in a slave device that receives a reference frame signal from a master device and transmits and receives a digital signal to and from the master device, and that generates a clock signal; A frequency divider that divides the clock signal; and a phase comparison unit that generates a voltage representing a phase difference between the reference frame signal and the output signal of the frequency divider and supplies the voltage as a control voltage to the voltage controlled oscillator. A voltage detecting means for detecting the control voltage supplied to the voltage controlled oscillator; a voltage storing means for storing the control voltage detected by the voltage detecting means; and Storage control means for controlling whether the control voltage detected by the detection means is stored in the voltage storage means, and the control output by the phase comparison means Switching means for supplying one of a voltage and the control voltage stored in the voltage storage means to the voltage controlled oscillator, and indicating whether the reference frame signal output by the master device is normal or not. Based on the identification signal, when the reference frame signal is normal, the control means controls the switching means to supply the control voltage output from the phase comparison means to the voltage controlled oscillator, and controls the storage control means. The control voltage detected by the voltage detection means is stored in the voltage storage means. On the other hand, when the reference frame signal is abnormal, the control means controls the switching means to store the control voltage stored in the voltage storage means. Control voltage control means for causing the voltage control oscillator to supply the control voltage and controlling the storage control means to stop storing the control voltage in the voltage storage means. Phase locked loop circuit characterized by comprising a. 2. The switching device according to claim 1, wherein the switching device includes a switching device for connecting one of an output of the phase comparing device and an output of the voltage storage device to a control input of the voltage controlled oscillator. The phase-locked loop circuit according to claim 1, wherein 3. The storage control means according to claim 1, wherein said storage control means includes switch means for opening and closing a connection between an output of said voltage detection means and an input of said voltage storage means. Phase synchronization circuit. 4. The phase comparison means according to claim 1, wherein said phase comparator outputs a pulse of a high level or a low level with respect to a reference level according to whether a phase of an output signal of said frequency divider is advanced or delayed with respect to a phase of said reference frame signal. 2. The phase-locked loop according to claim 1, further comprising: a comparing unit that outputs a signal; and a low-pass filter that extracts and outputs a low-frequency component included in an output signal of the comparing unit. 5. The control voltage control means includes a reference voltage source, and a second comparison means for comparing a voltage of the reference voltage source with a voltage of the identification signal, and a comparison result by the second comparison means. 2. The phase-locked loop according to claim 1, wherein said switching means and said storage control means are controlled based on said control means. 6. The master device and the slave device are provided in a wireless mobile station, the master device constitutes a modem unit for performing wireless communication with a wireless base station, and the slave device is connected via a line interface. 2. The phase-locked loop according to claim 1, wherein the data transmission unit transmits and receives signals to and from the telephone, and the identification signal indicates the intensity of radio waves from the wireless base station.