JPH11225071A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep a locked frequency even on the occurrence of a fault including the loss of a reference signal leading to inoperability in a phase locked loop(PLL) circuit suitable for use in applications where synchronizing operations are required. SOLUTION: A PLL circuit is provided with an A/D converter 6, a memory 7 and a D/A converter 8 between a loop filter 5 and a voltage controlled oscillator 3, with a period detector 9 that detects normality/abnormity of the period of a reference signal, and with a control means 10 that repetitively controls a digital control voltage outputted from the A/D converter 6 to the memory 7 when the PLL circuit is locked, and reads a digital control voltage before the occurrence of a fault from the memory 7 and outputs it to the D/A converter 8 when the period detector 9 detects that the period the reference signal is faulty.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Lo
More particularly, the present invention relates to a PLL circuit suitable for applications that need to operate in synchronization with each other.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration example of a PLL circuit. P
As shown in FIG. 4, the LL circuit includes a reference oscillator 41, a first frequency divider 42, a phase comparator 43, a loop filter 4
4, a voltage controlled oscillator (VCO) 45, and a second frequency divider 4
6. Note that the reference oscillator 41 is generally formed of a crystal oscillator. Also, the first frequency divider 42
Is a 1 / N frequency divider, and the second frequency divider 46 is a 1 / M frequency divider.

[0003] The operation of this PLL circuit is well known. The phase comparator 43 converts the output of the reference oscillator 41 into 1 /
N and the output of the VCO 45 to the second frequency divider 4
The phase difference from the signal divided by 1 / M in step 6 is detected, and an error signal is output to the loop filter 43. Loop filter 4
4 generates a predetermined control voltage from the error signal,
5 is applied. The VCO 45 oscillates at a frequency corresponding to the value of the applied control voltage. Then, the phase difference is detected by the phase comparator 43.

The above operation is repeated, and the phase comparator 4
A control voltage such that the phase difference detected in step 3 becomes 0
The control is performed to lock the oscillation frequency of the VCO 45 to a desired frequency. Here, in this type of PLL circuit, if the locked state is released for some reason, an operation of adjusting the control voltage is performed again, and thus there is a problem that it takes time to return to the original locked state. In order to solve this problem, a technique has been proposed in which a control voltage at the time of locking is stored, and when the lock is released, the stored control voltage is used (for example, Japanese Unexamined Patent Application Publication No. H11-163873). No. 5-114857).

[0005] This prior art is based on the premise that the reference signal is sound, and when the lock is released, the lock can be returned to the locked state in a short time. is there.

[0006]

By the way, PLL circuits are used for various purposes, but applications that need to operate in synchronism with each other include, as a simple example, a clock in each base station of mobile communication. PLL used in playback circuit
Circuits can be mentioned. In mobile communication, a method is employed in which each base station generates and uses its own operation clock based on a common reference signal (reference clock).

[0007] In the PLL circuit for such an application, occurrence of unlocking is not allowed.
Not applicable. This is because the loss of the lock of the PLL circuit immediately leads to the loss of synchronization of the reproduced clock, so that a measure for returning to the locked state in a short time does not make sense. On the other hand, in the case of mobile communication, each base station has a GP
Considering the case where the S radio wave is received and used as a common reference signal, the reception state of the GPS radio wave differs for each base station, and the reference signal may temporarily disappear in some base stations. When the common reference signal disappears, the clock recovery circuit performs clock recovery using the free-running frequency of the VCO. In this case, the frequency of the recovered clock is different from the normal frequency when the clocks are synchronized with each other. Therefore, there is a problem that clock synchronization is lost in a short time.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a PLL circuit having a means for maintaining a frequency at the time of locking even if an abnormality that cannot be used due to a loss of a reference signal occurs.

[0009]

FIG. 1 is a block diagram showing the principle of the first and second aspects of the present invention.

According to the first aspect of the present invention, there is provided a reference oscillator for outputting a reference signal, and a frequency divider for dividing the reference signal.
A voltage controlled oscillator 3 for outputting a frequency signal corresponding to the value of the control voltage, a phase comparator 4 for detecting a phase difference between the frequency signal and an output signal of the frequency divider 2, and an output of the phase comparator 4. A / D converter for digitizing the output of the loop filter 5 between the loop filter 5 and the voltage controlled oscillator 3 in a PLL circuit including a loop filter 5 for outputting the control voltage having a value corresponding to the phase difference Vessel 6 and A / D
A memory 7 in which the digital control voltage output from the converter 6 is written, and a D / A converter 8 that converts the digital control voltage read from the memory 7 into an analog control voltage and outputs the analog control voltage to the voltage controlled oscillator 3; , A period detector 9 for detecting normal / abnormal of the period of the reference signal,
When the LL circuit is in the locked state, the digital control voltage output from the A / D converter 6 is repeatedly written into the memory 7, and the cycle detector 9 detects that the cycle of the reference signal is abnormal. And a control means 10 for reading a digital control voltage before the occurrence of an abnormality from the memory 7 and outputting the digital control voltage to the D / A converter 8.

That is, according to the first aspect of the invention, the cycle detector 9 detects whether the cycle of the reference signal output from the reference oscillator 1 is normal or abnormal. The control means 10 repeats writing the output of the A / D converter 6 to the memory 7 when the period detector 9 detects the normality of the reference signal when the phase locked loop is in the locked state. At the same time, the control voltage at the time of locking is supplied to the voltage controlled oscillator 3 via the D / A converter 8, and the locked state is maintained.

When the period detector 9 detects an abnormality in the reference signal, the control means 10 reads the digital control voltage before the occurrence of the abnormality from the memory 7 and outputs the digital control voltage to the D / A converter 8. As a result, the normal control voltage is applied to the voltage controlled oscillator 3. Even if an error occurs in the reference signal, there is a delay due to frequency division.
Generally, it occurs after a timing that is appropriately delayed from the time of occurrence of an abnormality. Therefore, if the control voltage before the timing when the abnormality of the reference signal occurs is applied to the voltage-controlled oscillator 3, the phase lock loop can prevent the occurrence of the loss of lock beforehand, and can maintain the frequency and the phase when it is normal. .

According to a second aspect of the present invention, in the PLL circuit of the first aspect, the output of the D / A converter is delayed between the D / A converter and the voltage controlled oscillator. It is characterized in that a delay circuit 11 applied to the voltage controlled oscillator is provided. That is, according to the second aspect of the present invention, when the control voltage to be applied to the voltage controlled oscillator 3 is switched due to the occurrence of an abnormality in the reference signal, the delay circuit 11 prevents the control voltage from being applied to the voltage controlled oscillator 3 at one time. The delay operation is performed so that the voltage is suppressed and applied for a while. This makes it possible to correct a transient response caused by a sudden change of the control voltage or the like, and to avoid the possibility that the phase lock loop may be momentarily unlocked.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows the configuration of the PLL circuit according to the first and second embodiments. The same parts as those shown in FIG. 4 are denoted by the same reference numerals and names. In this embodiment, the loop filter 44 and the VCO 4
5, the A / D receiving the output of the loop filter 44
A converter 24, a memory 25 receiving an output of the A / D converter 24, and a D / A converter 26 receiving an output of the memory 25
And a CR time constant circuit 27 which receives the output of the D / A converter 26 and outputs it to the VCO 45.

A reference clock 21 is used as a reference oscillator.
And an oscillation detection counter 22 to which the reference clock 21 is input, and a control unit 23 that receives the output of the oscillation detection counter 22 and controls the memory 25. The control unit 23 includes a CPU (central processing unit), a program memory, and a working memory.
And a write / read control circuit for the memory 25. Note that the memory 25 has a built-in R
AM or external RAM. Also, the first frequency divider 4
The division ratio of 2 is fixed, and the division ratio of the second divider 46 is variable. That is, this embodiment assumes a PLL synthesizer.

The correspondence between the above configuration and the claims is as follows. The reference oscillator 1 has a reference clock 2
1 corresponds. The first frequency divider 42 corresponds to the frequency divider 2. The VCO 45 corresponds to the voltage controlled oscillator 3. The phase comparator 43 corresponds to the phase comparator 4. The loop filter 44 corresponds to the loop filter 5. A / D
The A / D converter 24 corresponds to the converter 6. Memory 7
Corresponds to the memory 25. The D / A converter 8 has D
The / A converter 26 corresponds. An oscillation detection counter 22 corresponds to the cycle detector 9. The control unit 10 includes the control unit 2
3 corresponds. The delay circuit 11 includes a CR time constant circuit 27
Corresponds.

The operation of this embodiment will be described below. P
Although the basic operation of forming the frequency locked state by the LL circuit is described above, the frequency locked state can be similarly formed by the configuration of FIG. However, until the PLL circuit is turned on and the frequency is locked, for example, the output of the loop filter 44 is directly connected to the input of the VCO 45, and when the frequency is locked by the above-described basic operation, the lock of the phase comparator 43 is detected. , The loop filter 44 and the VCO 45
May be disconnected to obtain the connection relationship shown in FIG. This embodiment will be described on the assumption that a frequency locked state is formed.

In FIG. 2, the A / D converter 24 outputs an output voltage (control voltage of the VCO 45) V of the loop filter 44.
1 is digitized and output to the memory 25. Further, the oscillation detection counter 22 measures the period of the reference clock 21, determines whether or not the value is close to a normal value, and notifies the control unit 23 of the determination result (normal / abnormal). The reference clock 21 is, for example, a network-synchronized clock signal, a clock signal reproduced from a carrier wave, a clock signal generated from a GPS radio wave, and the like, and includes a clock signal with a deteriorated C / N and a clock signal with a lot of jitter. .

If the content of the judgment notification from the oscillation detection counter 22 is "normal", the control unit 23
The output (digital control voltage) of the A / D converter 24 is written into the memory 25 while confirming that the phase locked loop is in the locked state by the lock detection of No. 3. The memory 25 has a capacity capable of storing each digital control voltage within a time of, for example, N seconds. That is, in the memory 25,
Each digital control voltage for N seconds is repeatedly written.

The controller 23 supplies the latest digital control voltage to the D / A converter 26 in parallel with the writing to the memory 25 to generate the analog control voltage V2.
As a result, the analog control voltage V2 changes to the CR time constant circuit 27.
To the VCO 45 to maintain the locked state of the phase locked loop. The analog control voltage V2 at this time has a value equal to the output voltage V1 of the loop filter 44.

Next, FIG. 3 is an operation time chart when an abnormality such as the disappearance of the reference signal occurs. Less than,
This will be described with reference to FIGS. FIG. 3A shows the signal state of the reference clock 21 and shows a case where the clock disappears at point A in the middle. FIG. 3B shows an output state of the first frequency divider 42. In the illustrated example, the first frequency divider 42 is assumed to divide by four, but outputs a constant value that does not change after the abnormality occurrence point A. However, the frequency division abnormality of the first frequency divider 42 becomes apparent at the time when it is delayed by several clocks. As a result, as shown in FIG. 3D, the output voltage V1 of the loop filter 44 starts to change after point B, which is delayed by a certain time.
Unlocking occurs. That is, the phase locked loop is
Since there is a delay due to the frequency dividing circuit, generally, the point of occurrence of the abnormality A
, The lock is not unlocked immediately, but unlocked after point B, which is delayed by a certain time.

At this time, in this embodiment, when the reference clock 21 becomes abnormal at the point A, the oscillation detection counter 22 immediately detects the period abnormality of the reference clock as shown in FIG. Notification of the occurrence of an error. Then, the control unit 23 takes out the digital control voltage N seconds before the abnormality occurrence point A from the memory 25 and supplies the digital control voltage to the D / A converter 26, and converts the analog control voltage V2 in the locked state to the CR time constant. The supply to the VCO 45 via the circuit 27 is started (FIG. 3 (5)).

As a result, although the phase locked loop is substantially unlocked, it can maintain the frequency and phase when it is normal, and can prevent the occurrence of unlock. Note that “N seconds before” means a predetermined time before the abnormality occurrence point A including immediately before the occurrence of the abnormality.

Next, the function of the CR time constant circuit 27 will be described. The time point A at which the abnormality of the reference clock 21 is detected and the time point B at which the lock is released are generally separated from each other and are rarely simultaneous. Is about to transition to In such a situation, if a normal control voltage is applied to the VCO 45 to return the phase locked loop to the locked state, a transient response occurs.

Further, even if the time point A at which the abnormality occurs and the time point B at which the lock is released are separated, it is assumed that the control voltage N seconds before and the control voltage at the time of the lock state are not the same value. In such a case, the control voltage of the VCO 45 is suddenly changed, so that a transient response similarly occurs. When the analog control voltage output from the D / A converter 26 is applied to the VCO 45 at one time, the above-described transient response may occur.

Therefore, the CR time constant circuit 27 is provided to suppress the control voltage from being applied to the VCO 45 at one time, to apply the control voltage slowly, and to prevent a transient response from occurring.

[0027]

As described above, according to the first aspect of the present invention, means for detecting abnormality such as disappearance of the reference signal is provided, and the control voltage in the locked state is stored one by one to store the reference signal. When an abnormality occurs, the digital control voltage before the occurrence of the abnormality is read out from the memory and used as the control voltage of the voltage-controlled oscillator, so that the control voltage at the time of normal operation can be applied to the voltage-controlled oscillator. Can prevent loss of lock beforehand, and can maintain the frequency and phase when it is normal.

According to the second aspect of the present invention, since the transient response generated when the control voltage applied to the voltage controlled oscillator is switched can be corrected, it is possible to avoid the possibility that the phase lock loop may be out of lock momentarily. Therefore, according to the first and second aspects of the invention, it is possible to prevent the voltage-controlled oscillator from returning to the free-running frequency due to the abnormality of the reference signal, and to maintain the locked state. PL suitable for applications where unlocking is not allowed, such as certain applications
An L circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a configuration example of an embodiment corresponding to claims 1 and 2;

FIG. 3 is an operation time chart when an abnormality such as the disappearance of a reference signal occurs.

FIG. 4 is a general configuration example of a PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference oscillator 2 Divider 3 Voltage controlled oscillator 4 Phase comparator 5 Loop filter 6 A / D converter 7 Memory 8 D / A converter 9 Period detector 10 Control means 11 Delay circuit 21 Reference clock 21 22 Oscillation detection counter Reference Signs List 23 control unit 24 A / D converter 25 memory 26 D / A converter 27 CR time constant circuit 42 first frequency divider 43 phase comparator 44 loop filter 45 voltage controlled oscillator (VCO)

Claims (2)

[Claims] 1. A reference oscillator for outputting a reference signal, a frequency divider for dividing the reference signal, a voltage controlled oscillator for outputting a frequency signal corresponding to a value of a control voltage, the frequency signal and the frequency division PLL comprising a phase comparator for detecting a phase difference from an output signal of a phase comparator, and a loop filter for outputting the control voltage having a value corresponding to the phase difference output from the phase comparator.
An A / D converter for digitizing an output of the loop filter between the loop filter and the voltage controlled oscillator, a memory in which a digital control voltage output from the A / D converter is written, A D / A converter that converts a digital control voltage read from the memory into an analog control voltage and outputs the analog control voltage to the voltage controlled oscillator; and a cycle detector that detects whether the cycle of the reference signal is normal or abnormal. When the PLL circuit is in the locked state, the digital control voltage output from the A / D converter is repeatedly written into the memory, and the cycle detector detects that the cycle of the reference signal is abnormal. Control means for reading the digital control voltage before the occurrence of the abnormality from the memory and outputting the digital control voltage to the D / A converter. PLL circuit, characterized in that it comprises. 2. The PLL circuit according to claim 1, wherein a D / A converter is provided between said D / A converter and said voltage controlled oscillator.
A PLL circuit having a delay circuit for delaying an output of an A converter and applying the delayed output to a voltage controlled oscillator.