KR19980066118A - Holdover Circuits and Methods in Synchronous Devices - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

Synchronous device

I. The technical problem that the invention is trying to solve

Synchronous devices have holdover and jitter suppression.

All. Summary of the Solution of the Invention

The synchronous device includes a phase detector for detecting a state of an input reference clock and a holdover selector configured to determine the input reference clock as a failure and perform a holdover function when the input clock exceeds an allowable frequency.

la. Important uses of the invention

If the synchronous device detects a case above the allowable frequency threshold, the holdover function can be performed immediately.

Description

Holdover Circuits and Methods in Synchronous Devices

The present invention relates to a holdover circuit and method in a synchronous device, and more particularly to a holdover circuit and method having a jitter suppression function of a supplied clock.

Fig. 1 is a diagram showing the structure of a holdover circuit in a conventional synchronous device, which is composed of a reference clock receiver 101, a phase difference detector 102, a controller 103, a D / A converter 104, a VCXO105, and a divider 106.

Referring to Fig. 1, the operation of the holdover circuit in the conventional synchronous device will be described. The reference clock receiver 101 receives the synchronization reference clock and transmits it to the phase difference detector 102. The phase difference detection unit 102 detects the phase difference in synchronization with a clock of 8 kHz and applies it to the control unit 103. The controller 103 receives data on the phase difference detected by the phase difference detector 102 and transmits the data to the D / A converter 104. The D / A converter 1014 converts the digital signal transmitted from the controller 103 into an analog signal and transmits the analog signal to the VCXO105. The VCXO105 supplies a clock of 19.44 MHz to the divider 106 and to the motherboard. The divider 106 receives a clock of 19.44 MHz, divides the clock, and supplies a clock of 8 kHz to the phase difference detector 102.

When the synchronization reference clock or data failure as described above occurs, the D / A converter 104 continuously applies a value applied before the failure to perform a holdover function of controlling the VCXO105. That is, when all of the input reference clocks fail, the switch is switched to the holdover function, and the latched value before the reference clock fails is continuously applied to the D / A converter 104. When the available reference clock is restored, if the available reference clock has ± 0 ppm frequency deviation, the network synchronization time is delayed because the digital PLL function must be performed again when the hold mode is entered while latched to any value within the oscillator capture range. And jitter increases. In addition, since the system clock is supplied to the motherboard in both the operation / protection unit, there is a problem in that jitter in the system is increased. There is a problem that the network quality is degraded by tracking even above the frequency tolerance threshold of each timing mode.

It is therefore an object of the present invention to provide a holdover circuit and method in a synchronous device.

Another object of the present invention is to provide a hold over circuit and a method for inputting a threshold frequency threshold or more in a synchronous device.

It is yet another object of the present invention to provide a holdover circuit and method for suppressing jitter in a synchronous device.

According to an aspect of the present invention, a phase detector for detecting a state of an input reference clock in a synchronous device and a holdover selection for determining the input reference clock as a failure and performing a holdover function when the input clock exceeds an allowable frequency It is characterized by consisting of parts.

1 is a diagram showing the configuration of a holdover circuit in a conventional synchronous device.

2 is a diagram showing the configuration of a holdover circuit in a synchronous device according to an embodiment of the present invention;

3 is a diagram showing the configuration of an output circuit in a synchronous device according to an embodiment of the present invention;

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating a holdover circuit in a synchronous device according to an embodiment of the present invention, wherein a reference clock receiver 101, a phase detector 102, a controller 103, a D / A converter 104, a VCXO105, a divider 106, 202, and a holdover circuit are shown in FIG. It consists of a selection and determination unit 200 and TCXO201.

3 is a diagram showing the configuration of an output circuit in a synchronous device according to an embodiment of the present invention, which is composed of a control unit 103, a VCXO105, and an output unit 300. As shown in FIG.

2 and 3, the operation of the holdover circuit in the synchronous device according to the embodiment of the present invention will be described. The reference clock receiver 101 receives the synchronization reference clock and transmits it to the phase difference detector 102. The phase difference detection unit 102 detects the phase difference in synchronization with a clock of 8 kHz and applies it to the control unit 103. The controller 103 receives data on the phase difference detected by the phase difference detector 102 and transmits the data to the D / A converter 104. The D / A converter 104 converts the digital signal transmitted from the controller 103 into an analog signal and transmits the analog signal to the VCXO105. The VCXO105 supplies a clock of 19.44 MHz to the divider 106 and to the motherboard. The divider 106 receives a clock of 19.44 MHz, divides the clock, and supplies a clock of 8 kHz to the holdover selection and determination unit 200. If all of the input reference clocks fail, the holdover selection and determination unit 200 detects whether the holdover mode has been entered or not. The TCXO201 determines the state of the divided 8 kHz clock and, if good, determines it as the reference clock. In TCXO201, the reference clock has a frequency deviation of approximately ± 6ppm and performs digital phase locked loop operation. The phase locked loop stops further phase control and declares a locked state when it is locked with a TCXO frequency of about ± 0 ppm. When an available reference input clock is received, the reference clock receiver 101 monitors the state of the clock, and if it is satisfactory, performs the digital phase locked loop function by performing a good input reference clock switching while holding the TCXO divided clock as the reference clock. . On the other hand, the control unit 103 monitors the state of the operation / protection unit to apply the control signal to the buffer only in the case of the operation unit to output the output. If the allowable frequency is greater than or equal to the threshold, the controller 103 detects this and declares a clock failure to immediately perform the holdover function.

As described above, the present invention maintains the frequency deviation near 0 ppm by using the internal oscillator when the synchronous device enters the holdover mode, thereby quickly performing network synchronization. In addition, the output is sent only to the operation unit, thereby suppressing the increase of jitter in the system.

Claims (3)

A holdover circuit in a synchronous device, comprising: a reference clock receiver for receiving an external reference clock, a phase detector for detecting a phase error by receiving a clock received from the reference clock receiver, and an excess frequency input from the external reference clock; A holdover circuit in a synchronous device, comprising: an allowable frequency monitoring unit for monitoring; and a clock generation unit for generating an internal clock. A holdover method in a synchronous device, wherein when a clock exceeding an allowable frequency threshold is input, the holdover mode is entered in the synchronous device, considering the clock input failure. 3. The holdover method in a synchronous device as set forth in claim 2, wherein the frequency is converted to ± 0 ppm upon entering the holdover mode.