JPH0256134A - Clock recovery system - Google Patents

Abstract

PURPOSE:To make a high speed synchronizing locking characteristic and a highly accurate steady-state characteristic available at the same time by providing a means detecting an input signal being a burst signal so as to control the operating parameter of a loop filter in a DPLL and a VCO. CONSTITUTION:A detector 5 detecting a phase difference or the like of a frame synchronizing signal, a preamble, a reception level or a recovered clock, a digital VCO 4 and a control circuit 6 controlling the operating parameter of a loop filter 3 are added to a component 1 of a DPLL. Such conditions as a phase difference of a recovery clock smaller than a setting value, a frame synchronizing signal detected, a preamble signal detected and a reception level larger than the setting value are satisfied, then constants of the DPLL are changed to vary the characteristic of the DPLL.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a clock using a digital phase-locked loop to realize high-speed synchronization pull-in in burst signal transmission technology and to realize highly reliable data transmission. This relates to the playback method.

[Conventional technology]

In a system that communicates in burst mode, it is necessary to recover the reference clock for demodulation, and a digital phase-locked loop (hereinafter referred to as r) is used as a clock recovery method.
DPLLJ) is often used.

FIG. 7 shows a system configuration diagram of a conventional digital phase-locked loop, in which 51 is a phase comparator, 52 is a loop filter, and 53 is a digital voltage controlled oscillator (hereinafter also referred to as "Dinotal VCOJ").

As shown in the figure, when using a DPLL or using the lock regeneration method, the clock regeneration circuit includes a phase comparator 51 that compares the phases of the input signal a and the regenerated clock b, and a digital VCO 53 that determines the synchronization characteristics and steady-state characteristics of the DPLL. and a loop filter 52.

FIG. 8 shows a circuit configuration block diagram of a conventional digital phase locked loop, in which 54 is a binary quantization phase comparator, 55 is an up/down counter, 56 is a frequency divider, 57 is a pulse removal adder, 58 represents a fixed frequency oscillator.

In the conventional example shown in FIG.
In this example, an up/down counter 55 is used as the loop filter 52, and a divider 56, a pulse removal adder 57, and a fixed frequency oscillator 58 are used as the digital VCO 53.

Further, in this example, clock recovery is performed as follows.

The binary quantization phase comparator 54 compares the phases of the input signal a and the reproduced clock b, and outputs leading (1) and delayed (-1) signals. The up/down counter 55 counts 1 and -1, and when the count matches the set value N and -N, it notifies the pulse removal adder 57 of the lead/lag. The pulse removal adder 57 advances and adds or removes M-bit pulses (hereinafter also simply referred to as rMJ) in response to the delay.

Therefore, the smaller the set value N (hereinafter simply referred to as rNJ), the more sensitive the pulse removal adder 57 is to the phase difference, and the larger M is, the larger the amount of correction per phase difference becomes. , suitable for high-speed synchronous pull-in.

Conversely, when N is large and M is small, errors in the binary quantization phase comparator 54 caused by noise have little effect on the pulse removal adder 57, and synchronization accuracy improves, making it highly stable and suitable for lock playback. .

[Problem to be solved by the invention]

In burst mode signal transmission, in order to perform demodulation with few errors, a highly accurate and highly stable recovered clock is required. It is desirable to set the constant (also referred to as constant J) to a constant that is highly stable and can reproduce the lock with high precision.

However, if the above-mentioned constants are set with emphasis on this steady-state characteristic, the burst synchronization characteristics will deteriorate and the synchronization pull-in will become slow. etc., resulting in a disadvantage that the burst transmission efficiency decreases. Especially in burst signal transmission with short signal length,
This is an important issue.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a clock regeneration method that can achieve both high-speed synchronization pull-in characteristics and highly accurate steady-state characteristics, which have conventionally been in a contradictory relationship. .

[Means to solve the problem]

According to the invention, the above objects are achieved by the means specified in the claims.

That is, the present invention provides a clock regeneration method for demodulating a burst signal, which includes a phase comparison means for performing a phase comparison between the burst signal and the reproduced clock signal, and a loop that performs a filtering action on the output of the phase comparison means. When using a DPLL which is a digital phase locked loop having a filter means and a voltage controlled oscillation means controlled by the output of the loop filter means, means attached to the DPLL to detect an input signal which is a burst signal. This is a clock regeneration system that includes means for controlling the operating parameters of at least one of the loop filter means and the voltage controlled oscillation means in the DPLL based on the output of the detection means.

[For production]

FIG. 1 is a system configuration block diagram for explaining the principle of the present invention, in which 1 is a conventional DPLL component, 2 is a phase comparator, 3 is a loop filter, and 4 is a digital Co., which is a voltage controlled oscillation means. , 5 represents a detector, and 6 represents a control circuit.

That is, the present invention adds 7 to the component 1 of the conventional DPLL.
A detector 5 that detects the frame synchronization signal, preamble, received level, or phase difference between the reproduced clocks, etc., and a control circuit 5 that controls the operating parameters of the digital VCO 4 and the loop filter 3 are added. When conditions such as the reception level is smaller than the set value, a frame synchronization signal is detected, a preamble signal is detected, or the reception level is higher than the set value,
The constants of the DPLL are switched to change the characteristics of the DPLL.

〔Example〕

FIG. 2 is a block diagram of a circuit configuration of a clock regeneration method showing a first embodiment of the present invention, in which 7 is a binary quantization phase comparator (hereinafter also simply referred to as a "phase comparator"), 8 is a 9 is a frequency divider, 10 is a pulse removal adder, 11 is a fixed frequency oscillator (hereinafter also simply referred to as a "frequency oscillator"), 12 is a frame detector, and 13 is a control circuit.

In this embodiment, a binary quantization DPLL consisting of a binary quantization phase comparator 7, an up-grain counter 8, a frequency divider 9, a pulse removal adder 10, and a fixed frequency oscillator 11 is used as the DPLL. , an up-grain counter 8 is used as the loop filter 3, and a frequency divider 9, a pulse removal adder 10, and a fixed frequency oscillator 11 are used as the digital VCO 4.

In addition to the DPLL, the clock recovery circuit of the embodiment of the present invention controls the constants of a 7-frame detector 12 that detects a frame synchronization signal of an input signal, an up-run counter 8 in the DPLL, and a pulse removal adder 10. A control circuit 13 is also provided.

Clock recovery is performed as follows.

The binary quantization phase comparator 7 receives the input signal a and the reproduced clock b.
It compares the phase with that of the signal and outputs leading (1) and delayed (-1) signals. The up-run counter 8 counts 1 and -1, and when the count matches the set value N and -N, it advances and notifies the pulse removal adder 10 of the delay.

The pulse removal adder 10 adds and removes M-bit pulses in accordance with the advance and delay. The smaller N is, the more sensitive the pulse removal adder 10 is to the phase difference, and the larger M is, the larger the amount of correction for the phase difference becomes at one time, which is suitable for high-speed synchronization pull-in.

Conversely, when N is large and M is small, errors in the phase comparator 7 due to noise have little effect on the pulse remover 10, and synchronization accuracy improves, making it suitable for highly stable and accurate lock regeneration.

The digital VCO 4 and upper loop filter 3 are controlled by taking advantage of the above characteristics.

That is, at the time of synchronization pull-in, the constants of the digital VCO 4 and the loop filter 3 are set for high-speed synchronization pull-in, and clock synchronization is quickly pulled in with a short preamble.

Further, when the 7-frame detector 12 detects a 7-frame synchronization signal indicating the start of data, the constants of the digital VCO 4 and the loop filter 3 are switched to constants for high stability and high precision.

As a result, the reproduced clock used for demodulating the data portion becomes highly stable and highly accurate, allowing demodulation with fewer errors.

In this way, high-speed burst synchronization pull-in is possible, and highly stable locking can be used during data demodulation, so highly efficient and reliable burst data transmission can be realized.

Note that it is not necessary to control the operating parameters of both the digital VCO 4 and the loop filter 3, and similar high-speed clock recovery can be performed by controlling only one of them.

Furthermore, although the up/down counter 8 is controlled using binary values, there is also a method of controlling using multiple values.

Furthermore, the digital VC,04 can be controlled by controlling the frequency division ratio of the divider 9 and the frequency of the frequency oscillator 11 in addition to adding pulse removal, and high-speed clock regeneration can be performed similarly.

FIG. 3 is a 70-chart for explaining the operation of the first embodiment shown in FIG. 2, and the clock recovery 70-1 shown in FIG. Clock regeneration flow 2 shown in FIG. 3(b) represents an operation flowchart during highly stable and highly accurate clock/reproduction.

In the initial state of step 20, the operating parameters M,
N is set to be a parameter for high-speed synchronization pull-in, and in step 21 a seven-frame synchronization signal in the input signal is detected.

If the 7-rem synchronization signal in the input signal cannot be detected,
The process moves to step 22 and enters clock recovery 70-1 for high-speed synchronization pull-in.

In step 22, the phase relationship between the input signal and the reproduced clock is compared, and if the phase of the reproduced clock is delayed,
Proceeding to step 23, the up/down counter (referred to as "rU/D counter" in the figure) is incremented by (-1).

In step 24, it is determined whether the count value of the up-running force wanta has reached the set value -N, and
If the result is N, the process moves to step 26, where an M-bit pulse is added to the pulse removal adder to advance the phase of the recovered clock.

If it is determined in step 22 that the phase of the reproduced clock is ahead of the input signal, the process moves to step 27, and the phase of the reproduced clock is delayed by the processing procedure from step 28 to step 30.

Further, if a frame synchronization signal in the input signal is detected in step 21, the process moves to step 31 shown in clock recovery 70-2, and the operating parameter MSN enables highly stable and highly accurate clock recovery. The operating parameters M' and N' are changed.

In step 32, the phase relationship between the input signal and the reproduced clock is compared, and if the phase of the reproduced clock is delayed, the phase of the reproduced clock is advanced by the steps from step 33 to step 36*, and the phase of the reproduced clock is If it is ahead of the input signal, the phase of the reproduced clock is delayed in steps from step 37 to step 40.

FIG. 4 is a block diagram of a circuit configuration of a clock recovery system showing a second embodiment of the present invention, in which 14 represents a preamble detector, and other symbols are the same as in FIG. 2.

In this embodiment, a binary quantization DPLL consisting of a binary quantization phase comparator 7, an up/down counter 8, a frequency divider 9, a pulse removal adder 10, and a fixed frequency oscillator 11 is used as the DPLL. , an up/down counter 8 is used as the loop filter 3, and a frequency divider 9, a pulse removal adder 10, and a fixed frequency oscillator 11 are used as the inverter VCO 4.

Closing of the embodiment of the present invention? In addition to the DPLL, the regeneration circuit includes a preamble detector 14 that detects a preamble signal of an input signal, and a 7pg count counter 8 in the DPLL.
and a control circuit 13 for controlling constants of the pulse removal adder 10.

Clock recovery is performed as follows.

The binary quantization phase comparator 7 receives the input signal a and the reproduced clock b.
It compares the phase with that of the signal and outputs leading (1) and delayed (-1) signals. The up/down counter 8 counts 1 and -1, and when the count matches the set value 10N and -N, it advances and notifies the pulse removal adder 10 of the delay.

The pulse removal adder 10 adds and removes M-bit pulses in accordance with the advance and delay. The smaller N is, the more sensitive the pulse removal adder 10 is to the phase difference, and the larger M is, the larger the amount of correction for the phase difference becomes at one time, which is suitable for high-speed synchronization pull-in.

Conversely, when N is large and M is small, errors in the phase comparator 7 due to noise have less influence on the pulse remover 10, and synchronization accuracy improves, making it suitable for highly stable and highly accurate lock reproduction.

The digital VCO 4 and loop filter 3 are controlled by taking advantage of the above features.

That is, at the time of synchronization pull-in, the constants of the digital VCO 4 and the loop filter 3 are set for high-speed synchronization pull-in, and clock synchronization is quickly pulled in with a short preamble.

Further, when the preamble detector 14 detects a preamble signal, the digital VCO 4 and the loop filter 3
Switch the constant to a constant for high stability and high precision.

As a result, the reproduced clock used for demodulating the data portion becomes highly stable and highly accurate, allowing demodulation with fewer errors.

In this way, high-speed burst synchronization pull-in is possible, and highly stable locking can be used during data demodulation, so highly efficient and reliable burst data transmission can be realized.

Note that it is not necessary to control the operating parameters of both the digital VCO 4 and the loop filter 3, and similar high-speed clock recovery can be performed by controlling only one of them. Furthermore, although the up/down counter 8 is controlled using binary values,
There is also a method of controlling with multiple values.

Furthermore, the digital VCO 4 can be controlled by controlling the frequency division ratio of the frequency divider 9 and the frequency of the frequency oscillator 11 in addition to adding pulse removal, and high-speed clock regeneration can be performed similarly.

FIG. 5 is a block diagram of a circuit configuration of a clock recovery method showing a third embodiment of the present invention, in which 15 represents a reception level detector, and other symbols are the same as in FIG. 2.

In this embodiment, a binary quantization DPLL consisting of a binary quantization phase comparator 7, an up/down counter 8, a frequency divider 9, a pulse removal adder 10, and a fixed frequency oscillator 11 is used as the DPLL. , an up/down counter 8 is used as the loop filter 3, and a frequency divider 9, a pulse removal adder 10, and a fixed frequency oscillator 11 are used as the digital VCO 4.

In addition to the DPLL, the tarock reproducing circuit according to the embodiment of the present invention includes a reception level detector 15 for detecting the level of the reception signal.
and a control circuit 13 for controlling the constants of a seven-step down counter 8 and a pulse removal adder 1o in the DPLL.

Clock recovery is performed as follows.

The binary quantization phase comparator 7 receives the input signal a and the reproduced clock b.
It compares the phase with that of the signal and outputs leading (1) and delayed (-1) signals. The up/down counter 8 counts 1 and -1, and when the counted number matches the set planting soil N and -N, it advances and notifies the pulse removal adder 10 of the delay.

The pulse removal adder 10 adds and removes M-bit pulses in accordance with the advance and delay. The smaller N is, the more sensitive the pulse removal adder 10 is to the phase difference, and the larger M is, the larger the amount of correction for the phase difference becomes at one time, which is suitable for high-speed synchronization pull-in.

Conversely, when N is large and M is small, errors in the phase comparator 7 due to noise have less influence on the pulse remover 10, and synchronization accuracy improves, making it suitable for highly stable and highly accurate lock reproduction.

The digital VCO 4 and loop filter 3 are controlled by taking advantage of the above features.

That is, at the time of synchronization pull-in, the constants of the digital VCO 4 and the loop filter 3 are set for high-speed synchronization pull-in, and clock synchronization is quickly pulled in with a short preamble.

Further, when the reception level detected by the reception level detector 15 exceeds a preset value, the constants of the digital VCO 4 and the loop filter 3 are switched to constants for high stability and precision. As a result, the reproduced clock used for demodulating the data portion becomes highly stable and highly accurate, allowing demodulation with fewer errors.

In this way, high-speed burst synchronization pull-in is possible, and highly stable locking can be used during data demodulation, so highly efficient and reliable burst data transmission can be realized.

Note that it is not necessary to control the operating parameters of both the digital VCO 4 and the loop filter 3, and similar high-speed clock recovery can be performed by controlling only one of them. Furthermore, although the up/down counter 8 is controlled using binary values,
There is also a method of controlling with multiple values.

Furthermore, the digital VCO 4 can be controlled by controlling the frequency division ratio of the divider 9 and the frequency of the frequency oscillator 11 in addition to adding pulse removal, and high-speed clock regeneration can be performed similarly.

FIG. 6 is a block diagram of a circuit configuration of a clock regeneration system showing a fourth embodiment of the present invention, in which 16 represents a phase difference detector, and other symbols are the same as in FIG. 2.

In this embodiment, a binary quantization DPLL consisting of a binary quantization phase comparator 7, an up/down counter 8, a frequency divider 9, a pulse removal adder 10, and a fixed frequency oscillator 11 is used as the DPLL. An up-down power converter 8 is used as the loop filter 3, and a frequency divider 9, a pulse remover 10 and a fixed frequency oscillator 11 are used as the digital VCO 4.

In addition to the DPLL, the clock regeneration circuit of the embodiment of the present invention includes a phase difference detector 16 that detects the phase difference between the input signal and the regenerated clock, an up/down counter 8 derived from the DPLL, and a constant of the pulse removal adder 10. Control circuit 1 to control
3.

Clock recovery is performed as follows.

The binary quantization phase comparator 7 inputs the input signal a and the reproduced black? Rib
It compares the phase with that of the signal and outputs leading (1) and delayed (-1) signals. The up/down counter 8 counts 1 and -1, and when the counted number matches the set planting soil N and -N, it advances and notifies the pulse removal adder 10 of the delay.

The pulse removal adder 10 adds and removes M-bit pulses in response to advance and delay.The smaller 6N is, the more sensitive the pulse removal adder 10 is to the phase difference, and the larger M is, the more sensitive the pulse removal adder 10 is to the phase difference. Since the amount of supplementary JIE per time is large, it is suitable for high-speed synchronization pull-in.

Conversely, when N is large and M is small, errors in the phase comparator 7 due to noise have less influence on the pulse remover 10, and synchronization accuracy improves, making it suitable for highly stable and highly accurate lock reproduction.

The digital VCO 4 and loop filter 3 are controlled by taking advantage of the above characteristics.

That is, at the time of synchronization pull-in, the constants of the digital VCO 4 and the loop filter 3 are set for high-speed synchronization pull-in, and a short preamble is used to quickly pull the clock synchronization.

Further, when the phase difference detected by the phase difference detector 7 becomes smaller than a set value, the constants of the digital VCO 4 and the loop filter 3 are switched to highly stable and high precision constants.

As a result, the reproduced clock used for demodulating the data portion becomes highly stable and highly accurate, allowing demodulation with less M').

In this way, high-speed burst synchronization pull-in is possible, and highly stable locking can be used during data demodulation, so highly efficient and reliable burst data transmission can be realized.

Note that it is not necessary to control the operating parameters of both the digital VCO 4 and the loop filter 3, and similar high-speed blackout reproduction can be performed even with only one I17aj.

Furthermore, although the seven-way down counter 8 is controlled using binary values, there is also a method of controlling it using multiple values.

Furthermore, the digital VCO 4 can be controlled by controlling the frequency division ratio of the frequency divider 9 and the frequency of the frequency oscillator 11 in addition to adding pulse removal, and high-speed clock regeneration can be performed similarly.

〔Effect of the invention〕

As explained above, according to the present invention, high-speed burst synchronization is possible during synchronization, and the clock can be regenerated with high stability and precision during data demodulation. Signal transmission can be realized.

[Brief explanation of the drawing]

Fig. 1 is a system MIl configuration block diagram for explaining the principle of the present invention, Fig. 2 is a block diagram of a clock regeneration system circuit configuration showing the first embodiment of the present invention, and Fig. 3 is shown in Fig. 2. 70-chart for explaining the operation of the first embodiment, FIG. 4 is a block diagram of the circuit configuration of a clock regeneration system showing the second embodiment of the present invention, and FIG. 5 shows the third embodiment of the present invention. 6 is a circuit configuration block diagram of a clock regeneration method showing a fourth embodiment of the present invention. FIG. 7 is a system configuration diagram of a conventional digital phase-locked loop. FIG. 8 is a circuit configuration block diagram of a conventional digital phase-locked loop. 1... Components of conventional DPLL, 2.
...Phase comparator, 3 ...Loop filter, 4 ...Digital VC
O. 5 ・・・・・・Detector, 6 ・・・・・・
Control circuit, 7... Binary quantization phase comparator,
8 ・・・・・・Upgrade counter,
9... Frequency divider, 10...
. . . Pulse removal adder, 11 . . . Fixed frequency oscillator, 12 . . . 7 frame detector, 13 . . . Control circuit, 14
・・・・・・Preamble detector, 15 ・・・・・・
Reception level detector, 16...Phase difference detector, 20-40...70-Representative for each step on the chart Patent attorney Takashi Honma (a) Calculation 1 Figure 2 Figure 2 3 evil (I no /) (b) 3rd Medical C Part 2) 3rd Horror Picture Recruitment Round 1

Claims (1)

[Claims] In a clock regeneration method for demodulating a burst signal, there is provided a phase comparison means for performing a phase comparison between the burst signal and the reproduced clock signal, and a loop that performs a filtering action on the output of the phase comparison means. When using a DPLL, which is a digital phase-locked loop, which has a filter means and a voltage-controlled oscillation means controlled by the output of the loop filter means, means for detecting an input signal, which is a burst signal, attached to the DPLL. . A clock regeneration system comprising: means for controlling an operating parameter of at least one of a loop filter means and a voltage controlled oscillation means in a DPLL according to the output of the detection means.