JP2531614B2 - PLL device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital PLL (Phose Locked Loop) circuit used in a modulation / demodulation circuit or the like such as a modem.

(Conventional Technology) Conventionally, as a technology in such a field, “Electronic Outlook Editor” edited “PLL Usage Guide” (Sho 51-7) Seibundo Shinkosha P.125
There was one described in -132. The configuration will be described below with reference to the drawings.

FIG. 2 is a block diagram showing a configuration example of a conventional digital PLL circuit.

This PLL circuit has an input terminal 1 for inputting an input signal F _i ,
And an output terminal 2 for outputting the feedback signal F _f . A phase comparator 3, a low-pass filter 4 including an integral counter, a voltage-controlled oscillator 5, and a frequency divider 6 are connected between the input and output terminals 1 and 2.

In this PLL circuit, the phase comparator 3 outputs the input signal F _i
The phase difference of the feedback signal F _f with respect to is detected, and the detected signal is given to the low-pass filter 4. In the low pass filter 4,
The high frequency component of the detection signal is attenuated and the filtered signal is sent to the voltage controlled oscillator 5. The voltage controlled oscillator 5 outputs the oscillation signal F ₀ having a frequency corresponding to the voltage of the filtered signal to the frequency divider 6. Then, the frequency divider 6 divides the frequency of the oscillating signal F ₀ by a constant ratio N, and supplies the signal F _f (= F ₀ / N) to the phase comparator 3 as a feedback signal. As a result, the feedback signal F _f synchronized with the input signal F _i is obtained.

When the PLL circuit as described above is used for a modulation / demodulation circuit to reproduce a carrier wave or demodulated data timing,
The performance of the PLL circuit is the same as that of the demodulation function (for example, S / N
Bit error rate).

An important parameter in the PLL circuit is a certain input signal F
_The time required to synchronize the feedback signal F _f with respect to _i (this is called the "pull-in time", which has a unit of ms, for example), and the change in the signal caused by system instability etc. "Jitter"). Both have opposite properties, and when one is improved, the other becomes worse. Therefore, conventionally, the amount of jitter that appears steadily was reduced to improve the performance of the demodulation function, but the pull-in time was sacrificed.

Recently, it has been desired to develop a PLL circuit in which the pull-in time is as short as possible and the stationary jitter amount is small. The pull-in time is basically determined by the time constant of the low-pass filter 4 in FIG. 2 and the amount of phase correction of the voltage-controlled oscillator 5 that changes according to its output.

Therefore, in order to realize a high-speed pull-in and low-jitter PLL circuit, a proposal has been made in which the pull-in time is shortened by making the time constant of the low-pass filter 4 variable rather than fixed. This proposal is equivalent to switching the RC product of the resistor R and the capacitor C with a switch of R or C, as has been attempted in the analog type PLL circuit. In the case of a digital type PLL circuit, the low-pass filter 4 is generally composed of an integrating counter, so that the number of counts of the counter is variable.

(Problems to be Solved by the Invention) However, in the PLL circuit having the above configuration, it is possible to shorten the lead-in time by making the count number of the low-pass filter variable, but the jitter amount is shortened as the lead-in time is shortened. Grows larger. Therefore, it has been difficult to obtain a digital PLL circuit which is technically sufficiently satisfactory.

The present invention has the following problems.
The present invention provides a PLL circuit that solves the problem that it is difficult to satisfy both high-speed pull-in and low jitter.

(Means for Solving Problems) In order to solve the problems, the present invention provides a phase comparator that detects a phase difference between an input signal and a feedback signal and outputs a detection signal, and A low-pass filter that outputs a filtered signal having a pulse of a first or second width, which is a filtered signal obtained by attenuating the high frequency component of the above, and an oscillating signal having a first or a second frequency according to the filtered signal. In a PLL circuit including a voltage-controlled oscillator that outputs any of the above, and a frequency divider that divides the frequency of the oscillation signal by 1 / N (N is an integer value) and outputs the feedback signal. A circuit, a second circuit, and a control circuit are provided.

The first circuit receives the feedback signal,
A circuit for outputting a modified feedback signal obtained by changing the feedback signal by a predetermined phase difference. The second circuit inputs the modified feedback signal and the input signal, and outputs a modified detection signal of a first potential level when the phase difference between the modified feedback signal and the input signal is a first magnitude. However, when the phase difference between the correction feedback signal and the input signal is the second magnitude larger than the first magnitude, the circuit outputs the correction detection signal of the second potential level. The control circuit is a circuit that defines the width of the pulse output by the low-pass filter.

The low pass filter outputs the filtered signal having the pulse of the first width defined by the control circuit in response to the correction detection signal of the first potential level, and outputs the second potential level. The filtered signal having a second width pulse longer than the first width defined by the control circuit in response to the modified detection signal of
The oscillation signal having the first or second frequency is output during the period defined by each of the first and second widths of the filtered signal.

(Operation) According to the present invention, since the PLL circuit is configured as described above, the first and second circuits have the phase difference between the feedback signal and the input signal within a certain range (that is, the first and second circuits). Size)
Then, the correction detection signal of the first potential level or the second potential level is output from the second circuit according to the range of the divided phase difference. The low pass filter is responsive to the modified detection signal of the first potential level to output a filtered signal having a pulse of a first width defined by the control circuit and responsive to the modified detection signal of the second potential level. And outputs a filtered signal having a pulse of the second width defined by the control circuit, and supplies the filtered signal to the voltage controlled oscillator. Then, the voltage controlled oscillator outputs the oscillation signal having the first or second frequency in the period defined by each of the first and second widths of the filtered signal.

That is, in the present invention, the magnitude of the phase difference is detected by the first and second circuits to change the degree of correction of the phase difference. When changing the degree of correction of the phase difference depending on the magnitude of this phase difference, the pulse width of the filtered signal output by the low-pass filter is changed to a pulse of the width specified by the control circuit, and the width of this changed pulse is changed. Desired frequency (first or second frequency) used for phase correction in the period defined by
The voltage controlled oscillator outputs an oscillation signal having As a result, not only can the timing control itself of the pulse width of the filtered signal be performed simply and accurately, but also high-speed pull-in and low-jitter control can be performed. Therefore, the above problems can be solved.

(Embodiment) FIG. 1 is a configuration block diagram of a digital PLL circuit showing an embodiment of the present invention.

This PLL circuit has an input terminal 11 for inputting an input signal F _i ,
Output terminal 12 that outputs the feedback signal F _f , and MHz
It has a clock input terminal 13 for inputting a unit master clock signal CP. A phase comparator 30, a low-pass filter 40, a voltage controlled oscillator 50, and a frequency divider 60 are provided between the input and output terminals 11 and 12.
Is connected.

The phase comparator 30 includes a first phase comparison circuit 31 and a second circuit including second, third phase comparison circuits 32 and 33 and a control circuit 34. The first phase comparison circuit 31
The phase of the input signal F _{i and} the phase of the feedback signal F _f are compared, and when the phase of the feedback signal F _f is delayed with respect to the input signal F _i , the phase delay signal F1 is output and the feedback signal F _f is output. Is a circuit that outputs a phase advance signal F2 when the phase of is advanced and supplies them to the low-pass filter 40.

The second phase comparison circuit 32 performs a phase comparison between the input signal F _i and a modified feedback signal (for example, a phase lead signal whose phase leads the feedback signal F _f by X) F _f (+ X), This is a circuit that outputs the comparison signal F3 to the control circuit 34. For example, if the phase lead signal F _f (+ X) is the input signal F _i
If it is more advanced than that, it means a large phase lead, and therefore the comparison signal F3 of the large phase lead is given to the control circuit 34.

The third phase comparison circuit 33 performs a phase comparison between the input signal F _i and a modified feedback signal (for example, a phase delay signal whose phase is delayed by X from the feedback signal F _f ) F _f (−X), This circuit outputs the comparison signal F4 to the control circuit 34. For example, if the phase delay signal F _f (−X) is the input signal F _i
If it is later than that, it means a large phase delay, and therefore the comparison signal F4 of the large phase delay is given to the control circuit 34.

The control circuit 34 outputs a correction detection signal corresponding to the comparison signal F3 or F4, which is given when there is a significant phase advance or delay, that is, the control signal CS1 to output the low-pass filter 40.
And a circuit to be applied to the voltage controlled oscillator 50.

The low pass filter 40 includes counters 41 and 42, a phase delay decoder 43, a phase advance decoder 44, and a control circuit 45. The counter 41 is a circuit that integrates the phase delay signal F1 given from the first phase comparison circuit 31 and outputs the integrated signal CT1 to the phase delay decoder 43. counter
The reference numeral 42 integrates the phase advance signal F2 given from the first phase comparison circuit 31 and outputs the integrated signal CT2 to the phase advance decoder 4
This is a circuit to output to 4. The phase delay signal F1 and the phase advance signal F2 are signals of logic “1”, “0”, and the counters 41, 42
Is designed to sequentially count this signal.

The phase delay decoder 43 and the phase advance decoder 44 are
Input the integration signals CT1 and CT2 and the control signal CS1, and enter the counter 4
This circuit detects whether or not the count value of 1,42 is equal to a preset value, and when it is equal, gives "1" to the control circuit 45.

The control circuit 45 is a circuit for controlling the frequency of the voltage controlled oscillator 50, receives the output signals of the decoders 43 and 44, outputs a control signal CS2 which is a filtered signal corresponding to the output signal, and supplies the control signal CS2 to the voltage controlled oscillator 50. It has a function. Further, the control circuit 45 outputs the reset signal CS3 to output the counters 41, 42.
Has the function of resetting.

The voltage controlled oscillator 50 has an oscillation circuit 51 including a programmable counter and the like, and a control circuit 52 including a counter and the like.

The oscillating circuit 51 inputs the master clock signal CP and normally divides the signal CP by n to output an oscillating signal F ₀ . However, when the decoder 43 sends "1" to the control circuit 45, the control circuit 45 determines that the current phase is in a delayed state, and the control signal CS2 for increasing the oscillation frequency is output.
To the oscillator circuit 51. As a result, the oscillator circuit 51 divides the master clock signal CP by (n-1) and outputs the oscillation signal F ₀ . Here, l is a preset value. When the decoder 44 sends "1" to the control circuit 45, the control circuit 45 determines that the current phase is advanced, and outputs the control signal CS2 for decreasing the oscillation frequency to the oscillation circuit 51. Give to. As a result, the oscillator circuit 51 divides the master clock signal by (n + 1) and outputs the oscillation signal F ₀ . When a programmable counter is used as the oscillation circuit 51, the preset data of the programmable counter will be sequentially changed by the control signal CS.

The control circuit 52 is a circuit that defines the width of the pulse output by the low-pass filter 40. That is, the control circuit 52 is a circuit that makes the phase correction performed in the oscillation circuit 51 variable based on the control signal CS1.
It has a function of controlling how many times (-1) or (n + 1) frequency division is performed. When the number of phase corrections of the oscillation circuit 51 reaches the preset number of times, the control circuit 52 gives a command signal CS4 for ending the phase correction to the control circuit 45 to end the phase correction operation. At the same time, the control circuit 45 sends the command signal CS
Upon receiving 4, the reset signal CS3 is output and the counters 41 and 42 are reset.

The frequency divider 60 is composed of a fixed frequency dividing circuit 61 and a phase difference changing circuit 62 which is a first circuit. Fixed divider circuit
Reference numeral 61 designates the feedback signal F _{f obtained by} dividing the oscillation signal F ₀ by N.
Is a circuit for providing the phase difference changing circuit 62 and the output terminal 12. The phase difference changing circuit 62 is configured by a shift register or the like, and based on the feedback signal F _f , a phase advance signal F _f (+ X) whose phase is advanced by X and a phase delay signal F _f (phase is delayed by X). -X) is output and given to the second and third phase comparison circuits 32 and 33, respectively.

FIG. 3 is a circuit diagram showing a configuration example of the phase comparator 30 in FIG.

In this phase comparator 30, the first, second, and third phase comparison circuits
31, 32 and 33 are composed of D-type flip-flops (hereinafter referred to as D-FF), and the control circuit 34 is composed of 2-input AND gates 34-1 and 34-2 and 2-input OR gate 34-3. ing.

An input signal F _i is applied to the clock input terminals CK of the phase comparison circuits 31 to 33, a feedback signal F _f is supplied to the delay input terminal D of the first phase comparison circuit 31, and a second phase comparison circuit 32. The phase lead signal F _f (+ X) is applied to the delay input terminal D of
However, the phase delay signal F _f (−X) is input to the delay input terminal D of the third phase comparison circuit 33, respectively. In the first phase comparison circuit 31, the comparison signal F1 delayed in phase from the positive output terminal Q and the comparison signal advanced in phase from the negative output terminal
F2 is output respectively. The positive output terminal Q of the second phase comparison circuit 32 outputs a comparison signal F3 having a large phase lead, and the negative output terminal of the third phase comparison circuit 33 outputs a comparison signal F4 having a large phase delay. .

In the control circuit 34, the two-input AND gate 34-1 performs a logical product of the comparison signals F1 and F3 to obtain the output signal F5, and
After the logical product of the comparison signals F2 and F4 is obtained by the input AND gate 34-2 to obtain the output signal F6, the output signals F5 and F6 are logically ORed by the 2-input OR gate 34-3, and the phase is significantly corrected. The control signal CS1 for outputting is output.

FIG. 4 is a circuit diagram showing a configuration example of the low-pass filter 40 in FIG.

In this low-pass filter 40, the counters 41 and 42 are 2-bit integral counters, and the decoder 43 is a 2-input exclusive OR.
Gate (hereinafter referred to as 2-input XOR gate) 43-1, 43-2
And a 2-input NOR gate 43-3, the decoder 44 includes a 2-input exclusive OR gate 44-1, 44-2 and a 2-input OR gate 44-3.
, And are respectively configured. In addition, the control circuit 45,
It is composed of a latch circuit. Here, the decoder 43 and
The variable detection circuit is composed of 44.

The counter 41 integrates the phase-delayed comparison signal F1 input to the clock input terminal CK, and outputs from the first-stage positive output terminal Q1 to 1
The second-stage integration signal CT1-1 is output from the second-stage positive output terminal Q2 as the second-stage integration signal CT1-2. Counter 42
Is the integration signal of the phase advance comparison signal F2 input to the clock input terminal CK, and the integration signal from the first stage positive output terminal Q1 to the first stage integration signal.
Connect CT2-1 to the 2nd stage integration signal CT2 from the 2nd stage positive output terminal Q2.
-2 is output respectively. Each of the counters 41 and 42 is adapted to be reset by a reset signal CS3 given to the reset input terminal R.

The decoder 43 has 2-input XOR gates 43-1, 43-2 and 2
By the input NOR gate 43-3, the integrated signals CT1-1, CT1-2
And the control signal CS1 having a preset value and the logic "1" or "0" which is a signal obtained by inverting the control signal CS1 with the inverter 43, and the integrated value of the phase delayed integration signal CT1 is compared with the control signal CS1.
It is detected whether or not it has become equal to the set value of and the output signal is given to the control circuit 45. Similarly, the decoder 44 has two inputs
The XOR gates 44-1 and 44-2 and the 2-input NOR gate 44-3 compare the integrated signals CT2-1 and CT2-2 with the control signal CS1, and the integrated value of the integrated signal CT2 with the phase lead is compared with the control signal CS1. It is detected whether or not it has become equal to the set value of and the output signal is given to the control circuit 45.

The control circuit 45 latches the output signals of the decoders 43 and 44, gives the output to the oscillation circuit 51 as the control signal CS2,
It has a function of controlling the oscillation frequency of the oscillation circuit 51. When the command signal CS4 output from the control circuit 52 shown in FIG. 1 is input to the control circuit 45 as a reset signal, the control circuit 45 releases the control of the oscillation circuit 51.

Next, the operation of the PLL circuit configured as above will be described with reference to FIGS. 5 and 6.

Incidentally, FIG. 5 is an operation explanatory diagram showing the positional relationship between the input signal F _i and the feedback signal F _f of Figure 1, and Figure 6 is the phase of the phase inputs F _i of the feedback signal F _f of Figure 1 FIG. 6 is an operation explanatory view schematically showing a state of being synchronized with.

First, as shown in FIG. 5, when the phase X of the phase difference changing circuit 62 in FIG.
The feedback signal F _f and the signal F _f (+ 60 °) whose phase is 60 ° ahead of this signal F _f
A region A in which the phase is delayed by 60 ° with respect to the F _f input signal F _i (that is, a region in which the input signal F _i is advanced by 60 ° or more with respect to the feedback signal F _f ) is detected.

Similarly, the phase comparator 30 has a feedback signal F _f
A region (that is, the input signal F _i ) in which the feedback signal F _f has a phase advanced by 60 ° or more with respect to the input signal F _i by the signal F _f (−60 °) whose phase is delayed from this signal F _f by 60 ° Detects a region B where the phase is delayed by 60 ° or more with respect to the feedback signal F _f . These detection results are given to the decoders 43 and 44 and the control circuit 52 as the control signal CS1.

Next, as shown in FIG. 6, unlike FIG. 5, the phase X of the phase difference changing circuit 62 in FIG. 1 is set to 90 °, and the feedback signal F _f becomes maximum with respect to the input signal F _i . It is assumed that there is a 180 ° phase lag of. It should be noted that FIG. 6 shows phase comparison points (logically the rising edge of the clock signal).

If the feedback signal F _f has a phase delay of 180 °,
This is detected by the phase comparison circuit 33 in FIG. 1, and the comparison signal FS is input to the control circuit 34. The control circuit 34 determines that the phase is significantly delayed, and applies the control signal CS1 corresponding thereto to the decoders 43 and 44 and the control circuit 52 in FIG. Then, since the decoder 43 gives the output signal of "1" to the control circuit 45, the control circuit 45 judges that the phase is currently delayed, and sends the control signal CS2 for raising the oscillation frequency to the oscillation circuit 51. give. As a result, the oscillator circuit 51 becomes
The master clock signal CP (n-
l) Divide and output oscillation signal F ₀ .

Here, the integration time constant of the low-pass filter 40 of FIG. 1 is set to, for example, once, and the phase correction amount (n-1) of the oscillation circuit 51 is set.
Since the number of times is set to several tens, the phase correction is performed faster than the normal phase correction operation until the phase is delayed by 90 °.

When the phase delay falls within 90 °, it is detected by the phase comparison circuit 31 in FIG. 1, and the comparison signal F1 is given to the counter 41. The counter 41 decodes the integrated signal CT1 by the decoder 43.
The control circuit 45 and the oscillation circuit 51 are controlled by the output signal of the decoder 43.

Here, the integration time constant of the low-pass filter 40 is set to, for example, two times, and the number of phase correction amounts (n-1) of the oscillation circuit 51 is also set to several times. Therefore, a normal phase correction operation is performed. The phase correction is performed at a slower speed.

Timing charts of the above phase correction operation are shown in FIG. 7 and FIG.

FIG. 7 is a timing chart showing the overall operation of the PLL circuit of FIG.

The F (-90 °) in FIG. 7 is a basic signal whose phase is delayed by 90 ° from the feedback signal F _f output from the PLL circuit in FIG. 1, and is generated inside the PLL circuit to generate the low-pass filter 40. Is being supplied to. The control signal CS1 is a signal output from the control circuit 34 of FIG. 1 when a significant phase delay or phase advance is detected, and the input signal F _i is the signal F _f (output from the phase difference change circuit 62 It becomes "1" when the position is out of ± X). As shown in FIG. 7, depending on whether or not the input signal F _i exists at the phase position of the shaded area, the PL of FIG.
It is determined whether the phase of the feedback signal F _f output from the L circuit is corrected at a low speed or at a high speed. The control signal CS2 is an output signal of the low-pass filter 40 (an output signal of the control circuit 45) determined according to the information of the phase delay signal F1, the phase advance signal F2, and the control signal CS1, and as shown in FIG. Is a signal which is output from the control circuit 45 in synchronism with the falling edge of the basic signal F (-90 °) and controls the oscillation circuit 51 when performing phase lead or phase lag correction.

Feedback signal F output from the PLL circuit of FIG.
_f of phase, or is ahead of the input signal F _i, or either lagging is simply determined by the phase comparator 30 for comparing the feedback signal F _f with the input signal F _i. Phase lead signal F2 and phase delay signal F1 shown in FIG.
Shows the relationship obtained by the phase comparison of the feedback signal F _f with the input signal F _i, initially has progressed phase of the feedback signal F _f, then the feedback signal if there is some phase shift to the input signal F _i It indicates that the phase of F _f has been delayed. The degree of advance / delay of these phases is indicated by the control signal CS1, and when the control signal CS1 is "1", it means that the phase is greatly advanced / delayed.

When the phase advance signal F2 or the phase delay signal F1 output from the phase comparison circuit 31 is input to the low pass filter 40, the advance / delay of the phase advance signal F2 is made in the low pass filter 40 according to the basic signal F (−90 °). The counters 41 and 42 operate. In the initial state, it is significantly advanced (CS = "1"), and the decode values of the counters 41 and 42 are set to 1, for example. Therefore, the control circuit 45 indicates the phase correction instruction with the phase advance information of one time.
2 is output to the oscillation circuit 51. The control signal CS2 is output from the control circuit 45 every time when the control signal CS1 is "1" (second potential level).

When the control signal CS1 becomes "0" (first potential level), the decode values of the counters 41 and 42 are set to 2, for example. Therefore, the control signal CS2 indicating the phase correction command is not output from the control circuit 45 to the position shown by the broken line in the control signal CS2 in FIG. 7, and appears at the second position.

Also in the case of phase delay, it is set in the low-pass filter 40 as in the case of phase advance described above.

FIG. 8 is a timing chart showing the operation of the voltage controlled oscillator 50 shown in FIG. In this timing chart, by the control signal CS2 set as described above,
How to change the oscillation state of the oscillation circuit 51 is shown.

In FIG. 8, the oscillation signal output from the oscillation circuit 51
F ₀ is a source clock that is then divided to produce a basic signal F (−90 °), the rising edge of which is the basic signal F (−90 °).
90 °) falling edge.

As for the operation in the case of phase advance, as shown in the upper part of FIG. 8, the control signal CS2 output from the control circuit 45 is set to "1" in synchronization with the falling edge of the basic signal F (-90 °). (The first and second periods). As a result, the oscillator circuit 51
Normally shifts from the state in which the master clock signal CP is divided by 1/4 to the state in which it is divided by 1/6 (n = 4, l = 2; n + 1). The oscillation signal F ₀ output from the oscillation circuit 51 is input to the control circuit 52 shown in FIG. Therefore, the control circuit 52 constantly monitors the oscillation signal F _0, for example, the clock of the oscillation signal F ₀ at 5 times the count state, the control signal CS
Reset 2 In this control circuit 52, for example, a counter provided therein can be changed by a predetermined value. This predetermined value is the control signal
Its value can be changed by CS1. At the same time, the control circuit 52
Also has a function of determining the amount of phase correction itself.

On the other hand, the operation in the case of the phase delay is shown in the lower part of FIG. In the operation in the case of a phase delay, for example, the oscillation circuit 51 normally divides the master clock signal CS by 1/4 and divides it by 1/2 (n = 4, l = 2; n → n + 1). Move to. Thus, in FIGS. 7 and 8, the basic signal F
The phase correction of the oscillator circuit 51 is performed starting from the falling edge of (-90 °).

As described above, in the present embodiment, by adding the phase comparison circuits 32 and 33, the current feedback signal F _f is compared in detail with what phase relationship the input signal F _i has, Based on the comparison signals F3, F4, the decoder 43,
The feature is that an adaptive phase correction system having a high-speed phase correction function and a low-speed phase correction function is configured by changing the integration time constant and the phase correction amount set in advance by the control circuit 44 and the control circuit 52.

By adopting such a phase correction system, it is possible to perform phase correction at high speed, and at the same time, after pulling in a certain phase, shift to the low speed phase correction state and reduce the amount of phase correction once. The feedback signal F _f is slowly synchronized with the input signal F _i . Therefore, the steady-state jitter amount is small, and even if synchronization is lost, synchronization can be performed in a short time. The phase X, which is the switching point for phase correction,
Although the set value varies depending on the usage condition of the PLL circuit, it may be appropriately selected in view of the consistency of the entire device. Further, it is possible to construct an adaptive phase correction system in any number of stages by increasing the number of phase comparison circuits 32 and 33.

 In the above example, the following experimental results were obtained.

Input signal F _i = 1200Hz, master clock signal CP = 1.8432
If you set the MHz and phase X = 22.5 ° and select the integration time constant and the amount of phase correction optimally, it is possible to synchronize with about 30 bits, and the jitter amount can be suppressed to about 2 μsec by synchronizing with 1200 Hz. It was When this PLL circuit is used for timing recovery of a modem, the S / N-to-bit error rate is improved by about 3 dB compared with the case where the conventional digital PLL circuit is used. This PLL circuit has many parameters (for example, X, the number of phase comparison circuits 32 and 33, etc.) that should be determined by the designer, and further has the flexibility to set them freely. It can be applied to a wide range of devices that require

(Effect of the Invention) As described in detail above, according to the present invention, the first circuit outputs the correction feedback signal, and the second circuit outputs the magnitude of the phase difference between the correction feedback signal and the input signal. A correction detection signal of a first potential level or a second potential level is output in accordance with the above, and a low-pass filter outputs a filtered signal having a pulse width defined by a control circuit in accordance with the potential level of the correction detection signal. Therefore, the oscillation frequency of the voltage controlled oscillator is controlled.

Therefore, when the phase difference between the modified feedback signal and the input signal is large, the low pass filter outputs a filtered signal having a pulse having a long width defined by the control circuit in accordance with the modified detection signal of the second value potential level. Thus, the oscillation frequency of the voltage controlled oscillator is controlled, and the phase can be corrected at high speed. When the phase difference between the modified feedback signal and the input signal becomes small when the phase difference between the modified feedback signal and the input signal becomes small, the filtered signal having a pulse with a short width defined by the control circuit responds to the modified detection signal of the first potential level in the low range. The oscillating frequency of the voltage controlled oscillator is controlled by the filter to shift to the low-speed phase correction state, and the feedback signal output from the PLL circuit is slowly synchronized with the input signal. Therefore, not only can the timing control itself of the pulse width of the filtered signal be performed simply and accurately, but the steady-state jitter amount is small, and
High-speed retraction becomes possible.

[Brief description of drawings]

1 is a block diagram of a PLL circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional PLL circuit, FIG. 3 is a circuit diagram of the phase comparator in FIG. 1, and FIG. Is a circuit diagram of the low-pass filter in FIG. 1, FIGS. 5 and 6 are explanatory diagrams of the operation of FIG. 1, FIG. 7 is a timing chart of the entire operation of FIG. 1, and FIG. 6 is an operation timing chart of the voltage controlled oscillator in the figure. 30 …… Phase comparator, 31,32,33 …… Phase comparator circuit, 34 ……
Control circuit, 40 ... Low-pass filter, 41,42 ... Counter, 43,
44 …… decoder, 45 …… control circuit, 50 …… voltage controlled oscillator, 51 …… oscillation circuit, 52 …… control circuit, 60 …… divider,
61 …… divider circuit, 62 …… phase difference change circuit, F _i …… input signal, F ₀ …… oscillation signal, F _f …… feedback signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-54-31260 (JP, A) JP-A-57-83934 (JP, A) JP-B-46-38162 (JP, B1)

Claims (1)

(57) [Claims] 1. A phase comparator which detects a phase difference between an input signal and a feedback signal and outputs a detection signal, and a filtered signal which attenuates a high frequency component in the detection signal and has a first or second width. A low-pass filter that outputs a filtered signal having a pulse, a voltage controlled oscillator that outputs either an oscillating signal having a first frequency or a second frequency according to the filtered signal, and a frequency of the oscillating signal that is 1 / N frequency divider (N is an integer value) and a frequency divider for outputting the feedback signal
In the circuit, the feedback signal is input, a first circuit that outputs a modified feedback signal obtained by changing the feedback signal by a predetermined phase difference, and the modified feedback signal and the input signal are input, and the modified feedback When the phase difference between the signal and the input signal is the first magnitude, the correction detection signal of the first potential level is output, and the phase difference between the correction feedback signal and the input signal is larger than the first magnitude. A second circuit that outputs a correction detection signal of a second potential level when the second magnitude is present; and a control circuit that defines the width of the pulse output by the low-pass filter, the low-pass filter Outputs the filtered signal having the pulse of the first width defined by the control circuit in response to the correction detection signal of the first potential level, and the second potential level. In response to the modified detection signal, the filtered signal having a second width pulse longer than the first width defined by the control circuit is output, and the voltage controlled oscillator outputs the filtered signal having the second width. A PLL circuit configured to output an oscillation signal having the first or second frequency in a period defined by each of the first and second widths.