JPS5783934A - Digital pll system - Google Patents

Digital pll system

Info

Publication number
JPS5783934A
JPS5783934A JP55159836A JP15983680A JPS5783934A JP S5783934 A JPS5783934 A JP S5783934A JP 55159836 A JP55159836 A JP 55159836A JP 15983680 A JP15983680 A JP 15983680A JP S5783934 A JPS5783934 A JP S5783934A
Authority
JP
Japan
Prior art keywords
output
frequency
counter
frequency division
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55159836A
Other languages
Japanese (ja)
Inventor
Toshihiko Tsunoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55159836A priority Critical patent/JPS5783934A/en
Publication of JPS5783934A publication Critical patent/JPS5783934A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain a PLL output which has less phase jitters even when there is no carrier component, by switching set frequency division ratios of a programmable frequency divider with time. CONSTITUTION:A counter 15 goes up regularly by the output of a programmable frequency divider 10 and, when its contents overflow, counts up again. Its output has bits as many as the low-order digit bits of an up/down counter 9. The output of the counter 15 is compared with the low-order digit bits 13 of the up/down counter 9 by a comparator 14. When the time from the start of the counting of the counter 15 to the overflow is regarded as one cycle, the period of a frequency division ratio 1/N is shortened as the phase difference between a frequency determined by the frequency division ratio 1/N and the carrier frequency of an input signal increases, and consequently the period of a 1/(N+1) is extended, so that the effective frequency of a PLL output 7 decreases.
JP55159836A 1980-11-13 1980-11-13 Digital pll system Pending JPS5783934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55159836A JPS5783934A (en) 1980-11-13 1980-11-13 Digital pll system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55159836A JPS5783934A (en) 1980-11-13 1980-11-13 Digital pll system

Publications (1)

Publication Number Publication Date
JPS5783934A true JPS5783934A (en) 1982-05-26

Family

ID=15702299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55159836A Pending JPS5783934A (en) 1980-11-13 1980-11-13 Digital pll system

Country Status (1)

Country Link
JP (1) JPS5783934A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61265922A (en) * 1985-05-20 1986-11-25 Oki Electric Ind Co Ltd Digital pll device
US5867544A (en) * 1994-03-04 1999-02-02 Fujitsu Limited Phase-locked loop oscillator, and moving-average circuit, and division-ratio equalization circuit suitable for use in the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61265922A (en) * 1985-05-20 1986-11-25 Oki Electric Ind Co Ltd Digital pll device
US5867544A (en) * 1994-03-04 1999-02-02 Fujitsu Limited Phase-locked loop oscillator, and moving-average circuit, and division-ratio equalization circuit suitable for use in the same

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