JPS57162526A - Phase synchronizing circuit - Google Patents

Phase synchronizing circuit

Info

Publication number
JPS57162526A
JPS57162526A JP56046941A JP4694181A JPS57162526A JP S57162526 A JPS57162526 A JP S57162526A JP 56046941 A JP56046941 A JP 56046941A JP 4694181 A JP4694181 A JP 4694181A JP S57162526 A JPS57162526 A JP S57162526A
Authority
JP
Japan
Prior art keywords
phase
terminal
signal
counter
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56046941A
Other languages
Japanese (ja)
Other versions
JPH0379888B2 (en
Inventor
Kuninosuke Ihira
Shigeyuki Umigami
Hiroya Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56046941A priority Critical patent/JPS57162526A/en
Publication of JPS57162526A publication Critical patent/JPS57162526A/en
Publication of JPH0379888B2 publication Critical patent/JPH0379888B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To ensure the stable working of a phase synchronizing circuit, by presetting a counter which devides the output signal of a variable frequency oscillator in case the phase of an input signal is outisde the range of syncronism. CONSTITUTION:When the control signal to be applied to a control terminal CONT is set at 0, AND circuits G1 and G2 are opened only for the period during which the output signal of a terminal Q of a flip-flop FF1 is set at 1. Then the output and input signals of a counter CTR are applied to a phase detector PD to detect the difference of phase. If the input signal has a phase within a period of 1 of the synchronizing range signal, an FF2 is set continuously with the terminal Q set at 1. At the same time, the phase difference is detected by the detector PD and a variable frequency oscillator VFO is controlled to control the frequency of oscillation to ensure the coincidence of phase. In case the input signal has a phase within the period of 0 and outside the synchronizing range, 1 and 0 are applied to a clock terminal C of an FF2 and a data terminal D, respectively. Thus the terminal Q of the FF2 is set at a set signal. This set signal is applied to a preset terminal PS of a counter CRT.
JP56046941A 1981-03-30 1981-03-30 Phase synchronizing circuit Granted JPS57162526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56046941A JPS57162526A (en) 1981-03-30 1981-03-30 Phase synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56046941A JPS57162526A (en) 1981-03-30 1981-03-30 Phase synchronizing circuit

Publications (2)

Publication Number Publication Date
JPS57162526A true JPS57162526A (en) 1982-10-06
JPH0379888B2 JPH0379888B2 (en) 1991-12-20

Family

ID=12761333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56046941A Granted JPS57162526A (en) 1981-03-30 1981-03-30 Phase synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS57162526A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6156513A (en) * 1984-08-27 1986-03-22 Sony Corp Pll circuit
JPS61222320A (en) * 1985-03-27 1986-10-02 Nec Corp Phase synchronizing circuit for magnetic recording and reproducing device
JPS61265934A (en) * 1985-05-21 1986-11-25 Japan Radio Co Ltd Bit synchronization circuit
JPH04301926A (en) * 1991-03-28 1992-10-26 Mitsubishi Electric Corp Pll circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6156513A (en) * 1984-08-27 1986-03-22 Sony Corp Pll circuit
JPS61222320A (en) * 1985-03-27 1986-10-02 Nec Corp Phase synchronizing circuit for magnetic recording and reproducing device
JPS61265934A (en) * 1985-05-21 1986-11-25 Japan Radio Co Ltd Bit synchronization circuit
JPH04301926A (en) * 1991-03-28 1992-10-26 Mitsubishi Electric Corp Pll circuit

Also Published As

Publication number Publication date
JPH0379888B2 (en) 1991-12-20

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