JPS61222320A - Phase synchronizing circuit for magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To decrease phase difference at switching between a data input signal and a return clock signal by switching a synchronous object input from a reference clock signal into the data input signal after a data input signal pulse comes. CONSTITUTION:A timing generator 6 inputs a switching input signal S8 for the switching control of a switch 1 and a data input signal S2 and after the switching input signal S8 is effective, a frequency division reset signal S9 is generated in response to the pulse of the data input signal S2 incoming at first and sends the result to a frequency divider 5. The frequency divider 5 sends the switching timing signal S10 to the switch 1 so as to switch the signal from the reference clock input signal S1 to the data input signal S2.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to a phase periodic circuit in a magnetic recording/reproducing device such as a magnetic disk device.

''ll1 Conventionally, this type of phase periodic circuit, as shown in Figure 2,
The reference clock input signal S1 and the data input signal S2 are selected using the switch 1 by the switching input signal S8, and these are selected by the phase comparator 2 in order to cause the output signal S3 of the switch 1 to cycle the return clock signal 811. By detecting the phase difference as a phase difference signal S4 and supplying the control voltage signal S5 converted by the filter 3 to a potential corresponding to this phase difference to the voltage controlled oscillator I14, the voltage controlled oscillator 4
The output clock S6, which is the output of ing.

In the conventional phase periodic circuit described above, when the periodic object is switched from the reference clock input signal S1 to the data input signal S2 by the switching input signal S8, the phase difference detected by the phase comparator 2 is detected. There is a drawback that it takes a while until the phase difference is generated up to the maximum value and the phase difference is reduced to below the specified value, in other words, it prevents speeding up of the pull-in time.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional circuit, and an object of the present invention is to provide a phase periodic circuit that can speed up the pull-in time.

11 Standing 11 The phase periodic circuit according to the present invention includes a switching means that receives a reference clock input signal and a data input signal and selects and outputs one of them, and a phase comparison circuit that receives an output signal of the selection means as one of the inputs. oscillation means for generating a clock signal with a frequency corresponding to the phase difference output of the phase comparator; and a frequency divider for dividing the output clock signal of the oscillation means and inputting the frequency to the other input of the phase comparator. a phase periodic circuit comprising a switching input signal for switching control of the switching means and the data input signal as inputs, the pulse of the data input signal arriving first after the switching input signal becomes valid; means for generating a frequency division reset signal in response to said frequency divider and then controlling said switching means to switch from said reference clock input signal to said data input signal; It is characterized by being initialized by a signal.

Tomokodan Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

As shown in FIG. 1, a reference zero input signal S1, a data input signal S2, and a switching timing signal S10 are input to a switch 1, and an output signal S3 of the switch 1 and a tank clock S7 are input to a phase comparator. The phase difference signal S4, which is the output of the phase comparator 2, is input to the filter 3, and the control voltage signal S5, which is the output of the filter 3, is input to the voltage controlled oscillator 4. A certain output clock signal @S6 is output to the outside and branched and input to the frequency divider 5 together with the frequency division reset signal S9, and the return clock signal S7 which is the output of the frequency divider 5 is input to the phase comparator 2. . The data input signal S2 and the switching input signal S8 are input to the timing generator 6, and the frequency division reset signal S9, which is the first output of the timing generator 6, is input to the frequency divider 5, and is the second output. The switching timing signal S10 is connected to be input to the switching device 1.

Next, the operation of the phase periodic circuit shown in FIG. 1 will be explained with reference to the waveform diagram shown in FIG. 3. The data input signal S2 and the switching input signal S8 are input to a timing generator 6, and when the switching input signal S8 transitions from low level to high level, the timing generator 6 outputs the data input signal S2 that arrives first after the transition. The pulse A is taken out and inverted, and sent to the frequency divider 5 as a frequency division reset signal S9. Furthermore, a switching timing signal 810 that changes from low level to high level at the trailing edge of this pulse A is sent to the switch 1. The reference clock signal S1 and the data input signal s2 are the switching timing signal 8.
10 is input to the switch 1, and the switch 1 receives the reference clock signal S1 when the switching timing generator number 0 is at low level.
is selected, and when the switching timing signal 810 is at a high level, the data input signal S2 is selected and output as the switching output signal s3.

The switching output signal S3 and the tank clock signal s7 are input to the phase comparator 2, and the phase comparator 2 detects the phase difference between the switching output signal S3 and the tank clock signal s7 and outputs it as a phase difference signal S4. The phase difference signal S4 is input to the filter 3, and the filter 3 outputs a control voltage signal S5 from which high frequency components of the phase difference signal S4 are removed. The control voltage signal s5 is input to the voltage controlled oscillator 4, and the voltage controlled oscillator 4
oscillates at a frequency proportional to the control voltage signal S5 and outputs an output clock signal S6 to the outside. This output clock signal S6 is branched and input to the frequency divider 5 together with the frequency division reset signal S9.
It consists of a flip-flop that is initialized when the level is
It divides the output clock signal and outputs the tank clock signal S7.

Next, the timing generator 4 will be explained with reference to FIG. 4, which shows an example of a typical circuit thereof. As shown in Figure 4,
The data input signal S2 and the switching input signal S8 are input to the D-type flip 70 block 8, and the D-type flip 70 block 8 converts the logic level of the switching input signal S8 input to the D input terminal into the data input to the clock input terminal. It reads in at the rising edge of the input signal S2 and outputs the signal 812. The data input signal S2 is also input to the inverter gate 9, and the data input signal S2 inverted by the inverter gate 9 is supplied to the clock input terminal of the D-type flip 70 tube 10. D
A signal 812, which is the output of the D-type flip 7O block 8, is input to the D input terminal of the type flip-flop 10, and the logic level of this signal @S12 is read at the falling edge of the data input signal S2, and the switching timing signal S10 is input. Output.

The switching timing signal S10, the output signal 812 of the D-type flip 70 tube 8, and the data input signal are input to the 3-input NANO gate 11, so that the switching timing signal S10, the output signal 812 of the D-type flip 70, and the data input signal are input to the 3-input NANO gate 11, so that the switching timing signal S10, the output signal 812 of the D-type flip 70, and the data input signal are input to the 3-input NANO gate 11. A frequency divider reset signal S9, which is obtained by extracting and inverting the pulse of the data input signal 812, is output from the 3-input NANO gate 11, and a switching timing signal @S10 that changes from low level to high level at the trailing edge of the first pulse is outputted. It is output from the D-type flip-flop 10.

Next, regarding the frequency divider 5, an example of a typical circuit is shown in the fifth section.
It is shown and explained in the figure. As shown in FIG. 5, the output clock signal S6 is input to the clock input terminal of the T-type flip-flop 7, and the frequency-divided reset signal S9 is input to the clock input terminal of the T-type flip-flop 7.
It is input to the reset terminal of 0 knob 12. When the frequency division reset signal S9 is at a low level, the output signal 313 of the T-type flip 70 tube 12 becomes a low level state, and after the frequency division reset signal S9 becomes a high level, the output clock signal S is output.
The output signal S13 is repeatedly inverted at every rising edge of the clock signal S13. Also, the output clock signal S6 is the inverter gate 1
3, and its inverted output is a D-type flip 70 tube 1.
It is input to the clock input terminal of No. 4. The D input terminal of the D-type flip-flop 14 receives the output signal S13 of the T-type flip 70 tube 12, and uses the frequency divider output, which is initialized when the frequency division reset signal S9 is at a low level, as the return clock signal S7. Output from the D-type flip 70 tube 14.

Due to the above operation, in the waveform diagram of FIG. 3, when the switching input signal S8 is low level, the switching output signal S3 is
Therefore, the falling position of the switching output signal S3 becomes the same signal as the reference clock signal S1 when the cycle is completed, and the falling position of the tank clock signal S7 coincides with that as shown by a, in other words, it is periodic.

When the switching input signal S8 transitions from low level to high level, the first arriving pulse A of the data input signal S2 after the transition is taken out and the retank clock signal S7 is initialized (reset) by the inverted frequency division reset signal S9. As a result, the time difference between the falling edge of the data input signal S2 and the falling edge of the tank clock signal S7, in other words, the phase difference is
The value becomes C from b shown in the figure, and after initialization, the switching timing signal S10 is changed from low level to high level, and the switching output signal S3 is made the same signal as the data input signal S2 by the switch 1.

Therefore, in this phase periodic circuit, when the periodic input is switched from the reference clock signal S1 to the data input signal S2, the phase comparison s! ! ! It is possible to reduce the detection phase difference caused by 2 and enable high-speed periodic operation.

As described in detail, according to the phase periodic circuit of the present invention, when the periodic input switches from the reference clock signal to the data input signal, the first arriving data input signal pulse is extracted and divided by that pulse. By initializing the frequency generator and switching the period target input from the reference clock signal to the data input signal after the arrival of the pulse, the phase difference between the data input signal detected by the phase comparator and the tank clock signal is reduced. This has the effect of enabling high-speed periodic operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the phase periodic circuit of the present invention, FIG. 2 is a block diagram showing an example of a conventional phase periodic circuit, and FIG. 3 is a waveform for explaining the operation of FIG. 1. figure,
4 is a circuit diagram showing details of an example of the timing generator of FIG. 1, and FIG. 5 is a circuit diagram showing details of an example of the frequency divider of FIG. 1. Explanation of symbols of main parts 1...Switcher 2...Phase comparator 4...Voltage controlled oscillator 5.7...Frequency divider

Claims (1)

[Claims] a switching means that receives a reference clock input signal and a data input signal and selects and outputs one of them; a phase comparator that receives an output signal of the selection means as one input; and a phase difference output of the phase comparator. and a frequency divider that divides the output clock signal of the oscillation means and provides the other input of the phase comparator, the phase periodic circuit comprising: A switching input signal for controlling switching of the means and the data input signal are input, and a frequency division reset signal is generated in response to a pulse of the data input signal that arrives first after the switching input signal becomes valid. , further comprising means for controlling the switching means to switch from the reference clock input signal to the data input signal, and the frequency divider is initialized by the frequency division reset signal. Phase periodic circuit.