JPH05206844A - Pll circuit - Google Patents

Abstract

PURPOSE:To window the capture range of a PLL circuit. CONSTITUTION:The PLL circuit is newly provided with a frequency discrimination means 102 and a control signal generation part 103. The frequency discrimination means 102 discriminates whether or not the oscillation frequency of a voltage control oscillation circuit 106 is in a specified range by counting the inversion cycle of a data train signal 100 by means of a clock 129 which the output of the voltage control oscillation circuit 106 as a time base. When such oscillation frequency of the voltage control oscillation circuit 106 is outside the specified range, a charger pump 104 is driven with the output signal of the frequency discrimination means 102 selectively outputted by the frequency discrimination means 102. When such oscillation frequency is within the specified range, the charger pump 104 is driven by the output signal of a phase comparator 101 selectively outputted by the control signal generation part 103. Thus, since a frequency pull-in operation is made by the frequency discrimination means 102 outside the capture range (frequency take-in range) of the PLL circuit and the same operation is made by phase comparator 101 when the frequency has been pulled in, substantial capture range can be windened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data string signal on which a clock is superimposed (for example, a digital audio interface signal used for exchanging data signals between digital audio devices such as CD and DAT).
To generate a demodulation clock whose phase and frequency are synchronized with the received data string signal in order to demodulate this.
It relates to the L circuit.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional PLL for generating a demodulated clock.
It is a block diagram which shows the example of a circuit. In FIG. 7, 704
Is a voltage controlled oscillator circuit, which generates a signal having a frequency according to the applied voltage.

Reference numeral 705 is a frequency dividing circuit for dividing the output of the voltage controlled oscillator circuit 704, and the output of the frequency dividing circuit 705 is a demodulation clock. 701 is a phase comparator, which uses the received data string signal 700 as a reference input and the demodulation clock 706, which is the output of the frequency dividing circuit 705, as a variable input to compare the phases of the two.
The control signal DN711 is output when the phase of the demodulation clock is advanced with respect to the data string signal, and conversely, the control signal UP710 is output when the phase of the demodulation clock is delayed with respect to the data string signal.

Reference numeral 702 denotes a charge pump, which operates to raise the control voltage of the voltage controlled oscillator circuit 704 by the control signal UP710 which is the output of the phase comparator 701, while
By the control signal DN711 which is the output of the phase comparator 701,
It operates to lower the control voltage of the voltage controlled oscillator circuit 704. A low-pass filter 703 smoothes a voltage change due to the operation of the charge pump 702 and applies a DC voltage as a control voltage 713 to the voltage controlled oscillator circuit 704.

The PLL circuit for generating a demodulated clock having the above-described structure controls the phase comparator 701 when the phase of the demodulated clock 706 is delayed with respect to the data string signal 700.
UP710 is output, which causes charge pump 702
Operates to increase the control voltage of the voltage controlled oscillator circuit 704. The low-pass filter 703 is the charge pump 702
The smoothing of the voltage rise due to the operation of the voltage control oscillation circuit 704 is smoothed to increase the control voltage 713 to the voltage control oscillation circuit 704, which raises the oscillation frequency of the voltage control oscillation circuit 704 and advances the phase of the demodulation clock 706. ..

On the contrary, when the phase of the demodulation clock 706 advances with respect to the data string signal 700, the control signal DN711 of the phase comparator 701 is output, which causes the charge pump 702 to control the voltage of the voltage controlled oscillator circuit 704. Works to lower. The low-pass filter 703 smoothes the rapid voltage drop change due to the operation of the charge pump 702 and lowers the control voltage 713 to the voltage controlled oscillator circuit 704, which lowers the oscillation frequency of the voltage controlled oscillator circuit 704.
It operates so that the phase of the demodulation clock 706 is delayed.

As described above, the operation is performed so that the phase difference between the demodulated clock 706 and the data string signal 700 is reduced, and when the phase difference disappears, the output DC voltage of the low pass filter 703 becomes constant. This state is called a locked state, and the state in which the phase difference changes in the process of being pulled into the locked state is called an unlocked state.

[0008]

In order to demodulate a received data string signal on which a clock is superimposed, such as a digital audio interface signal, a clock component is extracted from the data string signal and based on the extracted clock component. It is necessary to read the data with the demodulation clock generated by this. To read data, a demodulation clock having a frequency twice the maximum repetition frequency of the data string signal and having a predetermined phase relationship with the data string signal is generally required.

Therefore, the data string signal is used as the reference input of the phase comparator of the PLL circuit, and the output signal of the voltage controlled oscillator circuit is used as the variable input of the phase comparator, which is twice the maximum repetition frequency of the data string signal. The demodulated clock whose phase is matched to the data string signal is input by inputting each of the demodulated clocks that have been divided so that the frequency becomes Is generated in a voltage controlled oscillator circuit.

However, the frequency of the data string signal, which is the reference input of the phase comparator, and the frequency of the demodulation clock, which is the variable input, are too far apart, and the difference between the two frequencies is within a predetermined range called the frequency pull-in range (capture range). If not, the control of the voltage controlled oscillation circuit by the phase comparator will not be performed in the direction in which the phase difference between the demodulated clock and the data string signal is reduced, and there is a problem that the PLL circuit is never in the phase locked state. ..

The above-mentioned problem can be solved by expanding the frequency pull-in range (capture range) of the PLL circuit. However, in the conventional PLL circuit that controls only by the phase comparator, There was no one with sufficient frequency pull-in ability to satisfy.

The present invention solves the above conventional problems, and an object of the present invention is to provide a PLL circuit capable of substantially expanding the capture range.

[0013]

In order to achieve the above object, the PLL circuit of the present invention generates a clock having a frequency N times that of the demodulation clock in order to obtain the demodulation clock from the data string signal on which the clock is superimposed. Voltage control oscillator circuit, phase comparator that compares the phase of demodulated clock and data string signal, charge pump, low-pass filter, and determine whether the oscillation frequency of the voltage control oscillator circuit is within a specified range Frequency control means for controlling the charge pump, and control signal generation means for controlling the charge pump, the control signal generation means, when the oscillation frequency of the voltage controlled oscillation circuit is determined to be within a predetermined range by the frequency determination means, The output signal of the phase comparator is selectively output as the control signal of the charge pump, and the oscillation frequency of the voltage controlled oscillation circuit is determined by the frequency determination means. If it is determined that the constant range,
The output signal of the frequency determining means is selectively output as a control signal of the charge pump.

Further, in the PLL circuit of the present invention, in order to obtain the demodulation clock from the data sequence signal on which the clock is superimposed, a voltage controlled oscillator circuit for generating a clock having a frequency N times the demodulation clock, the demodulation clock and the data. A phase comparator that compares the phases of the column signals, a charge pump, a low-pass filter, and frequency determination means that determines whether the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range,
Control signal generating means for controlling the charge pump, wherein the control signal generating means outputs the output signal of the phase comparator when the frequency determining means determines that the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range. Is output as the control signal of the charge pump, and when the frequency determining means determines that the oscillation frequency of the voltage controlled oscillator is out of the predetermined range, the output signal of the frequency determining means is added to the output signal of the phase comparator. It is configured to be time-division multiplexed and output as a control signal for the charge pump.

Further, in the PLL circuit of the present invention, in order to obtain the demodulation clock from the data string signal on which the clock is superimposed, a voltage controlled oscillator circuit for generating a clock having a frequency N times the demodulation clock, the demodulation clock and the data. A phase comparator that compares the phases of the column signals, a charge pump, a low-pass filter, and frequency determination means that determines whether the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range,
The frequency determining means counts the inversion cycle of the data string signal with a clock whose time base is the output of the voltage controlled oscillation circuit, and controls the charge pump. Expected count value C _MAX
When a larger count value appears, it is configured to determine that the oscillation frequency of the voltage controlled oscillator circuit is high and is outside the predetermined range.

Further, in the PLL circuit of the present invention, in order to obtain the demodulation clock from the data sequence signal on which the clock is superimposed, a voltage controlled oscillator circuit for generating a clock having a frequency N times the demodulation clock, the demodulation clock and the data. A phase comparator that compares the phases of the column signals, a charge pump, a low-pass filter, and frequency determination means that determines whether the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range,
The frequency determining means counts the inversion cycle of the data string signal with a clock whose time base is the output of the voltage controlled oscillation circuit, and determines the minimum inversion cycle of the data string signal. Expected count value C _MIN
When a smaller count value appears, it is configured to determine that the oscillation frequency of the voltage controlled oscillator circuit is low and is outside the predetermined range.

[0017]

With the above-mentioned structure, the control signal generating means selects the output signal of the phase comparator based on the judgment result of the frequency judging means when the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range. When the oscillation frequency of the voltage controlled oscillation circuit is out of a predetermined range, it acts to control the charge pump according to the output signal of the frequency determination means.

Further, the frequency judging means counts the inversion cycle of the data string signal with a clock whose output is from the voltage controlled oscillation circuit as a time base, and is larger than the expected count value C _MAX of the maximum inversion cycle of the data string signal. When it appears, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is high and out of the predetermined range, or when a _count value smaller than the expected count value C _MIN of the minimum inversion cycle of the data string signal appears, the voltage It is determined that the oscillation frequency of the control oscillation circuit is low and out of the predetermined range, and based on this, the control signal generation means causes the output signal of the phase comparator to output when the oscillation frequency of the voltage controlled oscillation circuit is within the predetermined range. When the oscillation frequency of the voltage controlled oscillator is out of a predetermined range, the charge pump is controlled according to the output signal of the frequency determining means.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit for generating a demodulation clock whose phase and frequency are synchronized with a data string signal superposed with a clock, which is an embodiment of the present invention, will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a PLL circuit of an embodiment of the present invention, and FIG. 2 is a configuration diagram showing an example of a control signal generating means in the PLL circuit. In FIG. 1, 106
Is a voltage controlled oscillator circuit, 107 is a demodulation clock 108 obtained by dividing the output 128 of the voltage controlled oscillator circuit 106 by N, and is also divided by K (1≤K≤N) the output 128 of the voltage controlled oscillator circuit 106. It is a frequency dividing circuit for generating each of the comparison clocks 129.

Reference numeral 101 is a phase comparator for comparing the phases of the demodulated clock 108 output from the frequency divider circuit 107 and the data string signal 100, 120 and 121 are output signals of the phase comparator 101, and 120 is a logical level " Reference numeral 121 is a control signal (PUP) indicating a phase delay of the demodulation clock at 1 ", and 121 is a control signal (PDN) indicating a phase advance of the demodulation clock at a logic level" 1 ".

Reference numeral 102 compares the comparison clock 129, which is the output of the frequency dividing circuit 107, with the data string signal 100 to obtain a demodulation clock.
The frequency deciding means for deciding whether or not the frequency f _{PCK of} 108 is within a predetermined range and outputting a signal according to the frequency difference, 122 and 123 are output signals of the frequency deciding means 102, and 122 is a logic level "1". , A control signal (FUP) indicating that the frequency f _PCK of the demodulation clock is low, 123
Is a control signal (FDN) indicating that the frequency f _PCK of the demodulation clock is high at the logic level "1".

Reference numeral 103 denotes output signals 120 and 12 of the phase comparator 101.
1 and a control signal generating means for generating a control signal (UP) 124 and a control signal (DN) 125 for directly controlling the charge pump 104 on the basis of the output signals 122 and 123 of the frequency determining means 102. 104 indicates whether to raise or lower the control voltage of the voltage controlled oscillation circuit 106 by charging or discharging the low-pass filter 105 based on the control signal 124 and the control signal 125 which are the output signals of the control signal generating means 103. , Or lower it. The low-pass filter 105 smoothes the voltage change due to the operation of the charge pump 104, and applies the control voltage 127 to the voltage controlled oscillator circuit 106.

In the PLL circuit configured as shown in FIGS. 1 and 2, when the frequency f _{PCK of the} demodulated clock is outside the frequency pull-in range (capture range) of the PLL circuit,
A control signal (FU which is an output signal of the frequency determination means 102
Either P) 122 or (FDN) 123 becomes the logic level "1", and the control signal generating means is based on this.
103 selectively outputs the control signals (UP) 124 and (DN) 125 so as to become the output signals 122 and 123 of the frequency determination means 102.

The above operation is performed by using the frequency f of the demodulation clock 108.
_{Until PCK} falls within the frequency pull-in range (capture range) of the PLL circuit and is reflected in the output signals 122 and 123 indicating the determination result of the frequency determining means 102 (that is,
(Until both the output signals 122 and 123 indicating the determination result of the frequency determination means 102 are constantly at the logic level "0")
repeat.

The operation of the PLL circuit in this case will be described below. First, the case where the frequency f _PCK of the demodulation clock 108 is low and is outside the predetermined range will be described. When the frequency is low and out of the predetermined range, the output signal 122 of the frequency determining means 102 becomes the logic level "1" for a predetermined fixed time.

As shown in FIG. 2, the control signal generating means 103 includes OR gates 200, 206 and 207, an inverter 201,
Composed of AND gates 202, 203, 204 and 205
When the output signal 220 of the gate 200 is the logic level "1", the output signals (FUP) 122 and (FDN) 123 of the frequency determining means 102 are selectively output, and the output signal 221 of the inverter 201 is the logic level "1". If the phase comparator 10
The frequency determining means 10 operates as a selector for selectively outputting the output signals (PUP) 120 and (PDN) 121 of 1
When the output signal 122 of 2 becomes the logic level "1", the output signal 220 of the OR gate 200 becomes the logic level "1".
Therefore, the control signal (UP) 124 and the control signal (D
The output signals (FUP) 122 and (FDN) 123 of the frequency determining means 102 are selectively output to N) 125.

By the above operation, the charge pump 104
Further, the output signal (FUP) 122 of the frequency judging means 102 and the output signal (FDN) 123 of the frequency judging means 102 are given as control signals, and in this case, the frequency judging means 102.
The output signal (FUP) 122 of FIG. 2 has the logic level "1" (the output signal 123 is the logic level "0"), and thus the control voltage 127 of the voltage controlled oscillation circuit 106 is increased.

The degree of increase of the control voltage 127 is controlled by the time width t _FUP in which the control signal (FUP) 122, which is the output signal of the frequency determining means 102, becomes the logic level "1". Control signal (FUP) 122 from frequency determination means 102
The predetermined fixed time width t _{FUP at} which the logical level is "1" is set longer than the output signal width t _PUP of the control signal (PUP) 120 which is the output signal of the phase comparator 101.

The low-pass filter 105 smoothes a sudden voltage rise change due to the operation of the charge pump 104 and raises the control voltage 127 to the voltage controlled oscillator circuit 106, which raises the oscillation frequency of the voltage controlled oscillator circuit 106. ,
It operates so that the frequency f _PCK of the demodulation clock 108 becomes higher.

Next, the case where the frequency f _PCK of the demodulated clock 108 is high and is outside the predetermined range will be described. When the frequency is high and out of the predetermined range, the output signal 123 of the frequency determining means 102 becomes the logical level "1" for a predetermined fixed time.

As shown in FIG. 2, the control signal generating means 103 includes OR gates 200, 206 and 207, an inverter 201,
Composed of AND gates 202, 203, 204 and 205
When the output signal 220 of the gate 200 is the logic level "1", the output signals (FUP) 122 and (FDN) 123 of the frequency determining means 102 are selectively output, and the output signal 221 of the inverter 201 is the logic level "1". If the phase comparator 10
The frequency determining means 10 operates as a selector for selectively outputting the output signals (PUP) 120 and (PDN) 121 of 1
When the output signal 123 of 2 becomes the logic level "1", the output signal 220 of the OR gate 200 becomes the logic level "1".
Therefore, the control signal (UP) 124 and the control signal (D
The output signals (FUP) 122 and (FDN) 123 of the frequency determining means 102 are selectively output to N) 125.

By the above operation, the charge pump 10
The output signal (FUP) 122 of the frequency determining means 102 and the output signal (FDN) 123 of the frequency determining means 102 are given to 4 as control signals. In this case, the frequency determining means 10
Since the second output signal (FDN) 123 has the logic level "1" (the output signal 122 has the logic level "0"), the control voltage 127 of the voltage controlled oscillation circuit is lowered.

The degree of decrease of the control voltage 127 is controlled by the time width t _FDN in which the control signal (FDN) 123, which is the output signal of the frequency determining means 102, becomes the logic level "1". Control signal (FDN) 123 from the frequency determination means 102
Is set to a logic level "1", and the predetermined fixed time width t _FDN is set longer than the output time width t _PDN of the control signal (PDN) 121 which is the output signal of the phase comparator 101.

The low-pass filter 105 smoothes a sudden voltage drop change due to the operation of the charge pump 104, and drops the control voltage 127 to the voltage control oscillator circuit 106, which lowers the oscillation frequency of the voltage control oscillator circuit 106. ,
It operates so that the frequency f _PCK of the demodulation clock 108 becomes low.

As described above, if the difference between the frequency of the data string signal 100 and f _PCK / 2 is outside the frequency pull-in range (capture range) of the PLL circuit, the frequency difference between the demodulation clock 108 and the data string signal 100 is When the frequency difference falls within a predetermined range, the phase pull-in operation described below is started.

The frequency f _{PCK of the} demodulation clock 108 is the PLL
When it is within the frequency pull-in range (capture range) of the circuit, both the control signals (FUP) 122 and (FDN) 123, which are the output signals of the frequency determination means 102, become the logical level "0", and based on this, Control signal generation means
103 selectively outputs the control signals (UP) 124 and (DN) 125 so as to become the output signals 120 and 121 of the phase comparator 101.

The operation of the PLL circuit in this case will be described below. When the phase of the demodulated clock 108 is delayed with respect to the data string signal 100, the output signal 120 is output from the phase comparator 101 as the control signal, and the control voltage of the voltage controlled oscillation circuit 106 is output.
Works to raise 127. The low-pass filter 105 smoothes the rapid voltage rise change caused by the operation of the charge pump 104, and raises the control voltage 127 to the voltage control oscillator circuit 106, which raises the oscillation frequency of the voltage control oscillator circuit 106 and the demodulation clock. Operates to advance the phase of 108.

When the phase of the demodulated clock 108 advances with respect to the data string signal 100, the output signal 121 is output from the phase comparator 101 as a control signal, and the voltage controlled oscillator circuit
It operates to lower the control voltage 127 of 106. The low-pass filter 105 smoothes a rapid voltage drop change due to the operation of the charge pump 104, and the voltage-controlled oscillation circuit 106
The control voltage 127 for the voltage control oscillator 127 is lowered, whereby the oscillation frequency of the voltage controlled oscillator 106 is lowered, and the phase of the demodulation clock 108 is delayed.

As described above, the frequency f _{PCK of the} demodulated clock is the frequency pull-in range (capture range) of the PLL circuit.
If it is within the range, it operates so that the phase difference between the demodulated clock 108 and the data string signal 100 decreases, and when the phase difference disappears,
The output DC voltage of the low-pass filter 105 becomes constant,
At this point, the demodulation clock 108 becomes stable at a frequency twice the maximum repetition frequency f _MAX of the data string signal 100 and in a predetermined phase relationship with the data string signal 100. (Embodiment 2) FIG. 3 is a block diagram showing another example of the control signal generating means in the PLL circuit of the embodiment of the present invention. The basic configuration of the PLL circuit of this embodiment is the same as the block diagram of FIG. Therefore, detailed description thereof will be omitted.

In the PLL circuit configured as shown in FIGS. 1 and 3, when the frequency f _{PCK of the} demodulated clock is outside the frequency pull-in range (capture range) of the PLL circuit,
A control signal (FU which is an output signal of the frequency determination means 102
Either P) 122 or (FDN) 123 becomes the logic level "1", and the control signal generating means is based on this.
103 is a control signal generating means 103 when both output signals 120 and 121 of the phase comparator 101 are at a logic level "0".
The control signals (UP) 124 and (DN) 125 of the above are selectively output so as to become the output signals 122 and 123 of the frequency determining means 102.

The above operation is performed by using the frequency f of the demodulation clock 108.
_{Until PCK} falls within the frequency pull-in range (capture range) of the PLL circuit and is reflected in the output signals 122 and 123 indicating the determination result of the frequency determining means 102 (that is,
(Until both the output signals 122 and 123 indicating the determination result of the frequency determination means 102 are constantly at the logic level "0")
repeat.

The operation of the PLL circuit in this case will be described below. First, the case where the frequency f _PCK of the demodulation clock 108 is low and is outside the predetermined range will be described. When the frequency is low and out of the predetermined range, the control signal 122 of the frequency determining means 102 becomes the logical level "1" for a predetermined fixed time.

As shown in FIG. 3, the control signal generating means 103 includes a NOR gate 300, AND gates 301 and 302,
NOR gate 30 is constituted by OR gates 303 and 304.
When the output signal 310 of 0 is the logical level "1", the output signals (FUP) 122 and (FD) of the frequency determining means 102 are output.
N) 123 is selectively output and the output signal of the NOR gate 300
When 310 is a logic level "0", it operates as a selector for selectively outputting the output signals (PUP) 120 and (PDN) 121 of the phase comparator 101, and the output signal (FUP) 122 of the frequency judgment means 102 is a logic signal. When the level becomes “1”, the period when the output signal of the phase comparator 101 does not have the phase difference information, that is, the period when both the output signals 120 and 121 of the phase comparator 101 become the logical level “0”. And NO
The output signal 310 of the R gate 300 becomes a logic level "1", and the output signal (FUP) 122 of the frequency determining means 102 is selected and output as a control signal, thereby driving the charge pump 204.

With the above operation, in the same manner as the first embodiment,
The control voltage 127 to the voltage controlled oscillator circuit 106 is raised, whereby the oscillation frequency of the voltage controlled oscillator circuit 106 rises and the frequency of the demodulation clock 108 rises.

Next, the case where the frequency f _PCK of the demodulated clock 108 is high and is outside the predetermined range will be described. When the frequency is high and out of the predetermined range, the output signal (FD
N) 123 becomes the logic level "1". The control signal generating means 103, as shown in FIG.
When the output signal 310 of the NOR gate 300 is a logic level "1", it is composed of D gates 301 and 302 and OR gates 303 and 304.
UP) 122 and (FDN) 123 are selectively output, and NO
When the output signal 310 of the R gate 300 is at the logic level "0", the output signals (PUP) 120 and (PDN) 121 of the phase comparator 101 operate as selectors, and the output signal of the frequency judgment means 102. When the (FDP) 123 becomes the logic level “1”, the output signal of the phase comparator 101 does not have the phase difference information, that is, both the output signals 120 and 121 of the phase comparator 101 are at the logic level. Output signal of NOR gate 300 during the period of "0"
The logic level of 310 is "1", and the output signal (FDN) 123 of the frequency determination means 102 is selected and output as the control signal 125, whereby the charge pump 204 is driven.

By the above operation, in the same manner as the first embodiment,
The control voltage 127 to the voltage controlled oscillation circuit 106 is lowered, whereby the oscillation frequency of the voltage controlled oscillation circuit 106 is lowered, and the frequency of the demodulation clock 108 is lowered.

In this way, the frequency f of the demodulation clock 108
_{If PCK} is outside the frequency pull-in range (capture range) of the PLL circuit, demodulation clock 108 and data string signal 10
When the frequency is within a predetermined range, the control signals (FUP) 122 and (FDN) 123, which are the output signals of the frequency determination means 102, both become the logic level "0". Based on this, the control signal generating means 103 controls the control signals (UP) 124 and (DN) 125.
Are selected and output so as to become the output signals 120 and 121 of the phase comparator 101.

Thereafter, similar to the first embodiment, if the frequency f _PCK of the demodulation clock 108 is within the frequency pull-in range (capture range) of the PLL circuit, the demodulation clock 108.
And the data string signal 100 operate so as to reduce the phase difference, and when the phase difference disappears, the output DC voltage of the low-pass filter 105 becomes constant, and at this point, the demodulation clock 108
Is stable at a frequency twice the maximum repetition frequency of the data string signal 100 and in a predetermined phase relationship with the data string signal 100. (Embodiment 3) FIG. 4 is a block diagram showing an example of frequency determining means in a PLL circuit according to an embodiment of the present invention. In FIG. 4, 100 is a data string signal, and in this embodiment, IE
It will be described as a digital audio interface signal (DAI signal) compliant with the C-958 standard. 12
Reference numeral 9 is a comparison clock (FCMP).

Reference numeral 401 denotes an inversion cycle of the DAI signal 100 (in the example of FIG. 4, a logical level “H” section of the DAI signal), a counter that counts the comparison clock (FCMP) 129 as a clock, and 402 a count value of the counter 401. A D flip-flop held by the inverter 408 at the falling timing of the DAI signal, 403 is a decoder A, 406 for detecting a value smaller than the count value C _MIN in the minimum inversion cycle of the data string signal when the PLL is in the locked state. PL
Decoder B that detects a value larger than the count value C _MAX in the maximum inversion cycle of the data string signal in the locked state of L, 404 is a pulse stretch circuit that holds the detection result of the decoder A 403 for a predetermined time, and 407 is a decoder A pulse stretch circuit for holding the detection result by B406 for a predetermined time, 405 is a decoder A
403 or a reset pulse generation circuit for generating a reset signal of the D flip-flop 402 based on the output signal of the decoder B406.

FIG. 5 is a timing diagram showing the format of the DAI signal. In FIG. 5, 501 is a sampling clock, 502, 503 and 505 are DAI signals conforming to the IEC-958 standard, 504 is a demodulation clock (128fs) extracted from the DAI signal, 505 and 508 are preamble “W”, and B channel data. D that indicates
AI signal synchronization pattern, 506 and 509 are preambles "M", DAI signal synchronization pattern 507 indicating that it is A channel data that is not the beginning of the block
And 510 are the preamble "B", which is the synchronization pattern of the DAI signal indicating that it is the A channel data at the beginning of the block, and the detailed operation will be described below.

As shown by 502, 503 and 505 in FIG. 5, the DAI signal 100 is bi-phase coded of digital audio data, and the data is composed of two kinds of signals 1T and 2T.

Here, T is T = 1 / 128fs, and fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (A channel, B channel).

FIG. 5 shows an example of DAT, and one channel is the L channel of audio data,
The other data is the R channel of audio data. A 2-channel signal has a frame composed of three types of preambles "B", "M", and "W", and is transmitted with 192 frames as one block.

Now, the counter 401 for the DAI signal described above is used.
Input to the reset terminal of the comparison clock (F
By inputting CMP) 129, the inversion period of the DAI signal can be obtained as a count value. Here, the comparison clock (FCMP) 129 is a signal whose time base is the output of the voltage controlled oscillation circuit, but here it is described as N frequency division for simplicity. That is, the comparison clock (FCM
P) 129 is the demodulation clock (PCK) itself.

First, the case where the PLL is in the locked state will be described. The relationship between the DAI signal, the comparison clock (FCMP), and the count value of the counter at this time is shown in FIG. 6A (however, here, the comparison clock is the demodulation clock, and FCMP = PCK = 128fs).
Is).

The counter has a logic level "L" of the DAI signal.
Then, the count-up operation is performed using the comparison clock (FCMP) as a clock in the section of the logic level "H" of the DAI signal. When the PLL is locked and the relationship between the DAI signal and the comparison clock (FCMP) becomes as shown in FIG. 6A, when 3T appears in the logical level “H” section of the DAI signal (preamble appears. In this case, the count value is always "3", and this count value "3"
Is the maximum count value C _MAX when the PLL is in the locked state (C _MAX = 3).

Further, the logical level "H" section of the DAI signal
If a 2T appears in the, the count value is always "2".
When 1T appears, the count value is always "1".
It The count value "1" is the maximum when the PLL is in the locked state.
Small count value C_MINIs (C _MIN= 1).

The count value C _{DT of the} counter is the D flip-flop at the timing of the falling edge of the DAI signal.
It is held at 402, and immediately thereafter, it is reset by the logic level "L" of the DAI signal.

[0059] D count value held in the flip-flop 402 C _DT is, C _DT by the decoder A403 is determined whether C _MIN smaller, C _MIN (= 1) decoder A403 If less than the logic level "H Is output. The pulse stretch circuit 404 outputs the output signal 122 of logic level "H" as a control signal (FUP) for a predetermined time from the rising edge of the output signal 423 of the decoder A403.

When the PLL is locked, it is the minimum value C _MIN of C _DT as described above, and therefore the decoder A40
The output of 3 does not go to logic level "H". Therefore, the control signal (FUP) which is the output signal 122 of the pulse stretch circuit 404 does not become the logic level "H".

[0061] The count value held in the D flip-flop 402 C _DT is determined whether greater than C _MAX by the decoder B406, if greater than C _MAX decoder B406 outputs a logic level "H". The pulse stretch circuit 407 outputs the output signal 123 of the logical level “H” as a time control signal (FDN) which is predetermined from the rising edge of the output signal 425 of the decoder B406.
Is output.

When the PLL is locked, the output of the decoder B does not become the logic level "H" because it is the minimum value C _MAX of C _DT as described above. Therefore, the control signal (FD) which is the output signal 123 of the pulse stretch circuit 407
N) also does not go to the logic level "H". As described above, when the PLL is locked, the control signals (FUP) 122 and (F) output from the frequency determination means 102 are output.
Both DN) 123 are constantly at the logic level "L",
Based on this, the control signal generating means 103 in FIG.
Is the control signal (UP) 12 as shown in the first and second embodiments.
4 and (DN) 125 are the output signals 120 of the phase comparator 101.
And output so that it becomes and 121. That is, like the conventional PLL circuit shown in FIG. 7, it operates as a PLL circuit including a phase comparator, a charge pump, an LPF, a VCO, and a frequency dividing circuit.

Next, the case where the frequency f _PCK of the demodulation clock is high when the PLL is unlocked will be described. FIG. 6B shows the relationship between the DAI signal, the comparison clock (FCMP), and the count value of the counter at this time (however, here, the comparison clock is the demodulation clock, and FCMP = PCK when the PLL is locked). =
128 fs).

The counter has a logic level "L" of the DAI signal.
Then, the count-up operation is performed using the comparison clock (FCMP) as a clock in the section of the logic level "H" of the DAI signal. When the PLL is unlocked, D
The count value does not always become “3” when 3T appears in the section where the AI signal and the logic level are “H” (when the preamble appears). For example, when the frequency f _{PCK of the} demodulation clock is high as shown in the period indicated by d in FIG. 6B, the count value C _DT exceeds C _MAX . Similarly, D
When 2T appears in the logic level “H” section of the AI signal,
Also, when 1T appears, the count value is "2".
Above, it becomes "1" or above.

The count value C _{DT of the} counter is the D flip-flop at the timing of the falling edge of the DAI signal.
It is held at 402, and immediately thereafter, it is reset by the logic level "L" of the DAI signal.

The count value C _DT held in the D flip-flop 402 is judged by the decoder A 403 whether C _DT is smaller than C _{MIN, and} when it is smaller than (C _MIN = 1), the decoder A 403 has a logic level "H". Is output. The pulse stretch circuit 404 outputs the output signal 122 of logic level "H" as a control signal (FUP) for a predetermined time from the rising edge of the output signal 423 of the decoder A403.

However, when the frequency f _PCK of the demodulation clock is high when the PLL is unlocked, the count value becomes equal to or greater than the count value when C _DT is locked as described above, and therefore the output of the decoder A403 is It does not become the logic level "H". Therefore, the output signal of the pulse stretch circuit 404
The control signal (FUP) which is 122 does not become the logic level "H".

[0068] The count value C _DT held in the D flip-flop 402, it is determined whether or larger than C _MAX by the decoder B406, if greater than C _MAX decoder B406 outputs a logic level "H". The pulse stretch circuit 407 outputs the output signal 425 of the decoder B406.
Output signal 12 of logic level "H" as control signal (FDN) for a predetermined time from the rising edge of
Outputs 3.

When the frequency f _PCK of the demodulated clock is high when the PLL is in the unlocked state, the count value becomes equal to or greater than the count value when C _DT is locked, as described above, for example, in the period indicated by d in FIG. 6B. As can be seen, a value "4" greater than C _MAX may appear. At this time, the output of the decoder B406 becomes the logic level "H", and the control signal (FD) which is the output signal 123 of the pulse stretch circuit 407 is output.
N) is a logic level "H" for a predetermined time from the rising edge of the output signal 425 of the decoder B406.
Becomes

As described above, when the frequency f _PCK of the demodulated clock is high when the PLL is unlocked,
A control signal (FU which is an output signal of the frequency determination means 102
P) 122 is constantly at the logic level "L", while the control signal (FDN) 123 is at the logic level "H" every time a value larger than C _MAX appears in the count value C _DT .

As a result, as described in the first and second embodiments, the control voltage to the voltage controlled oscillator circuit 106 in FIG. 1 is increased, which raises the oscillation frequency of the voltage controlled oscillator circuit 106 and the frequency f of the demodulation clock 108. It works to increase the _PCK .

Next, the case where the frequency f _PCK of the demodulation clock is low when the PLL is unlocked will be described. FIG. 6C shows the relationship between the DAI signal, the comparison clock (FCMP), and the count value of the counter at this time (however, here, the comparison clock is the demodulation clock, and FCMP = PCK when the PLL is locked). =
128 fs).

The counter has a logic level "L" of the DAI signal.
Then, the count-up operation is performed using the comparison clock (FCMP) as a clock in the section of the logic level "H" of the DAI signal. When the PLL is unlocked, D
The count value does not always become "1" when 1T (minimum inversion period) appears in the interval between the AI signal and the logic level "H". For example, when the frequency f _{PCK of the} demodulation clock is low, as seen in the period indicated by e in FIG. 6C, the count value C _DT becomes lower than C _MIN . Similarly, when 3T appears in the logical level "H" section of the DAI signal and when 2T appears, the count values are "3" or less and "2" or less, respectively.

The count value C _{DT of the} counter is the D flip-flop at the timing of the falling edge of the DAI signal.
It is held at 402, and immediately thereafter, it is reset by the logic level "L" of the DAI signal.

[0075] D count value held in the flip-flop 402 C _DT is, C _DT by the decoder A403 is determined whether C _MIN smaller, C _MIN (= 1) decoder A403 If less than the logic level "H Is output. The pulse stretch circuit 404 outputs the output signal 122 of logic level "H" as a control signal (FUP) for a predetermined time from the rising edge of the output signal 423 of the decoder A403.

When the frequency f _PCK of the demodulated clock is low when the PLL is in the unlocked state, the count value becomes equal to or smaller than the count value when C _DT is locked as described above. For example, at e in FIG. 6C. C _MIN as seen in the period shown
In some cases, a smaller value "0" may appear. At this time, the output of the decoder A403 becomes the logic level "H", and the control signal (FU) which is the output signal 122 of the pulse stretch circuit 404.
P) is a logic level "H" for a predetermined time from the rising edge of the output signal 423 of the decoder A403.
Becomes

[0077] The count value C _DT held in the D flip-flop 402, it is determined whether or larger than C _MAX by the decoder B406, if greater than C _MAX decoder B406 outputs a logic level "H". The pulse stretch circuit 407 outputs the output signal 425 of the decoder B406.
Output signal 12 of logic level "H" as control signal (FDN) for a predetermined time from the rising edge of
Outputs 3.

However, when the frequency f _PCK of the demodulation clock is low when the PLL is in the unlocked state, the count value C _DT becomes the count value at the time of lock or less as described above, and therefore the output of the decoder B406 is logical. It does not reach level "H". Therefore, the output signal 12 of the pulse stretch circuit 407
The control signal (FDN) of 3 does not become the logic level "H".

As described above, when the PLL is unlocked and the frequency f _PCK of the demodulation clock is low,
A control signal (FU which is an output signal of the frequency determination means 102
P) 122 becomes a logic level "H" every time a value smaller than C _MIN appears in the count value C _DT . On the other hand, the control signal (F
DN) 123 is constantly at the logic level "L".

As a result, as described in the first and second embodiments, the control voltage to the voltage controlled oscillator circuit 106 in FIG. 1 is lowered, whereby the oscillation frequency of the voltage controlled oscillator circuit 106 is lowered and the frequency f of the demodulation clock 108 is lowered. It works to lower the _PCK .

[0081]

As described above, according to the present invention, when the frequency difference between the maximum repetition frequency of the data string signal and the frequency of the demodulation clock is outside the frequency pull-in range (capture range) of the PLL circuit, the frequency The determination means detects this and performs the frequency pull-in operation by the frequency determination means, and operates so that the frequency difference between the maximum repetition frequency of the data string signal and the frequency of the demodulation clock falls within the frequency pull-in range of the PLL circuit. It is possible to expand the substantial frequency pull-in range.

Further, since the frequency judging means is configured to make a relative comparison between the data string signal and the demodulated clock, the PLL circuit follows this even if the pitch of the data string signal changes greatly. Then, the frequency pull-in operation can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example of a control signal generating means in the PLL circuit according to the exemplary embodiment of the present invention.

FIG. 3 is a configuration diagram showing another example of the control signal generating means in the PLL circuit according to the exemplary embodiment of the present invention.

FIG. 4 is a configuration diagram showing an example of frequency determining means in a PLL circuit according to an embodiment of the present invention.

FIG. 5 is a timing diagram showing a format of a DAI signal.

FIG. 6 is a timing diagram showing the operation of the frequency determining means in the PLL circuit according to the embodiment of the present invention.

FIG. 7 is a block diagram showing an example of a conventional PLL circuit.

[Explanation of symbols]

 101 phase comparator 102 frequency judgment means 103 control signal generation means 104 charge pump 105 low-pass filter 106 voltage controlled oscillation circuit 107 frequency divider circuit 401 counter 402 D flip-flop 403 decoder A 404 pulse stretch circuit 405 reset pulse generation circuit 406 decoder B 407 Pulse stretch circuit 408 Inverter

Claims (4)

[Claims] 1. A voltage controlled oscillator circuit for generating a clock having a frequency N times as high as that of the demodulation clock in order to obtain a demodulation clock from the data sequence signal on which the clock is superimposed, and the demodulation clock having a variable input, and the data sequence signal A phase comparator that compares the phases of both as a reference input and outputs a signal according to the phase difference, a charge pump that charges or discharges a charge for applying a control voltage to the voltage controlled oscillator circuit, and the charge A PLL circuit configured by a low-pass filter that smoothes a voltage change due to the operation of a pump and applies a control voltage to the voltage controlled oscillator circuit, and a clock whose output is the time base of the voltage controlled oscillator circuit. The frequency judgment is performed by comparing with the data string signal and judging whether the oscillation frequency of the voltage controlled oscillation circuit is within the specified range. Means is provided between the output of the phase comparator and the input of the charge pump, and based on the output signal of the phase comparator and the output signal of the frequency determining means, a control signal for the charge pump is provided. And a control signal generation means for generating, the control signal generation means, when the oscillation frequency of the voltage controlled oscillator circuit is determined by the frequency determination means is within a predetermined range, the output signal of the phase comparator When the frequency determining means determines that the oscillation frequency of the voltage controlled oscillator is outside the predetermined range, the output signal of the frequency determining means is output as the control signal of the charge pump. Circuit that selectively outputs as. 2. The control signal generation means selects the output signal of the phase comparator as the control signal of the charge pump when the frequency determination means determines that the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range. Output, when it is determined by the frequency determination means that the oscillation frequency of the voltage controlled oscillator is out of a predetermined range, the output signal of the phase comparator is time-division multiplexed with the output signal of the phase comparator, The PLL circuit according to claim 1, which outputs as a control signal of a charge pump. 3. The frequency determining means includes counting means for counting the inversion cycle of the data string signal with a clock whose output is the time-base of the voltage controlled oscillator circuit, and the expected count value C of the maximum inversion cycle of the data string signal. 3. The PLL circuit according to claim 1, wherein when a count value larger than _MAX appears, it is determined that the oscillation frequency of the voltage controlled oscillator circuit is high and is outside the predetermined range. 4. The frequency determining means includes counting means for counting the inversion cycle of the data string signal with a clock whose output is the time base of the voltage controlled oscillation circuit, and the expected count value C of the minimum inversion cycle of the data string signal. 3. The PLL circuit according to claim 1, wherein when a count value smaller than _MIN appears, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is low and is outside a predetermined range.