JPH03230619A - Pll circuit - Google Patents

Abstract

PURPOSE:To expand a capture range substantially by operating this PLL circuit so that the difference of frequencies between a demodulation clock and a data string signal is decreased when the difference between the frequency of the data string signal and the frequency of the demodulation clock is at the outside of the capture range of the PLL circuit. CONSTITUTION:When the difference of a frequency of a data string signal 101 and the frequency of a demodulation clock 112 is at the outside of a frequency pulling-in range (capture range) of the PLL circuit, a frequency comparator 103 detects it. Then the difference of the frequency of the data string signal 101 and the frequency of the demodulation clock 112 is within the frequency pulling-in range (capture range) of the PLL circuit by applying frequency pulling-in operation of the frequency comparator 103. Thus, the frequency pulling-in range is substantially expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention receives a data string signal (for example, a digital audio interface signal used for sending and receiving data signals between digital audio devices), and converts the received signal into a signal. This invention relates to a PLL circuit that generates a demodulated clock whose phase and frequency are synchronized.

BACKGROUND OF THE INVENTION FIG. 4 is a diagram showing an example of a conventional demodulated clock generation PLL circuit.

In FIG. 3, 307 is a voltage controlled oscillation circuit, which generates a signal with a frequency proportional to the applied voltage. 30
8 is a frequency dividing circuit that divides the output of the voltage controlled oscillation circuit 307, and the output of this frequency dividing circuit 308 is a demodulated clock. 302 is a phase comparator, which receives the received data string signal 30.
1 as a reference input and a demodulated clock 309, which is the output of the frequency divider circuit 308, as a variable input to compare the phases of the two, and output a discharge control signal 312 when the phase of the demodulated clock leads the data string signal. Conversely, when the phase of the demodulated clock lags behind the data string signal, the charge control signal 311 is output. 303 is a charge pump, which has a P-channel FET 304 and an N-channel FET.
The P-channel FET 304 is turned on by the charge control signal 311 which is the output of the phase comparator 302, and charges the low-pass filter 306. On the other hand, the N-channel FET 305 is turned ON by the discharge control signal 312 which is the output of the phase comparator 302, and discharges the charge from the low-pass filter 306. A low-pass filter 306 smoothes voltage changes caused by charge pump 303 charging or discharging, and applies a DC voltage to the voltage controlled oscillation circuit 307 as a control voltage.

In the demodulated clock generation PLL circuit configured as described above, when the phase of the demodulated clock 309 lags behind the data string signal 301, the charge control signal 311 of the phase comparator 302 is outputted, which causes the charge pump to The P-channel FET 304 is turned on, and the low-pass filter 306 is charged with electric charge. The low-pass filter 306 smoothes the sudden voltage rise change caused by the charge, and increases the control voltage 314 to the voltage controlled oscillation circuit 307. This increases the oscillation frequency of the voltage controlled oscillation circuit 307, and the demodulated clock It operates so that the phase of 309 advances. Conversely, when the phase of the demodulated clock 309 leads the data string signal 301, the discharge control signal 312 of the phase comparator 302 is output, which causes the N-channel FE of the charge pump to
T305 is turned on, and electric charges are discharged from low-pass fist fill 306. Low-pass Toyo filter 30
6 smooths out the sudden voltage drop change caused by discharge of electric charge and lowers the control voltage 314 to the voltage controlled oscillation circuit 307, thereby lowering the oscillation frequency of the voltage controlled oscillation circuit 307 and changing the phase of the demodulated clock 309. works so that it is delayed.

In this way, it operates so that the phase difference between the demodulated clock 309 and the data string signal 301 decreases, and when the phase difference disappears,
The output DC voltage of the low-pass filter 306 becomes constant. This state is called a locked state, and the state in which the phase difference changes during the process of being pulled into the locked state is called an unlocked state.

Problems to be Solved by the Invention In order to demodulate a received data string signal, it is necessary to extract a clock component from the data string signal and read data using a demodulated clock generated based on the extracted clock component.

In order to read data, a demodulated clock having a frequency twice the maximum repetition frequency of the data string signal and having a predetermined phase relationship with the data string signal is required.

For this purpose, the data string signal is used as the reference input of the phase comparator of the PLL circuit, and the output signal of the voltage controlled oscillator circuit is used as the variable input of the phase comparator at a frequency twice the maximum repetition frequency of the data string signal. Input the demodulated clocks frequency-divided separately, and use the output of the phase comparator to charge and
The voltage controlled oscillation circuit is controlled via a pump and a low-pass filter to cause the voltage controlled oscillation circuit to generate a demodulated clock whose phase matches the data string signal.

However, the frequency of the data string signal, which is the reference input of the phase comparator, and the frequency of the demodulated clock, which is the variable input (generally a frequency that is an integer fraction of the oscillation frequency of the voltage controlled oscillation circuit), are too far apart, and the image frequency If the difference between the demodulated clock and the data string signal is not within a predetermined range called the frequency capture range, the phase comparator will no longer control the voltage controlled oscillation circuit in a direction that reduces the phase difference between the demodulated clock and the data string signal. There is a problem in that the PLL circuit is never in a phase locked state.

The above-mentioned problem can be solved by expanding the frequency capture range of the PLL circuit, but this is not possible for conventional PLL circuits that are basically controlled using only a phase comparator. There was no one with sufficient frequency pulling ability to satisfy the requirements.

The present invention solves the above-mentioned conventional problems, and aims to provide a PLL circuit that can substantially expand the capture range.

Means for Solving the Problems In order to achieve the above object, the PLL circuit of the present invention comprises a voltage controlled oscillation circuit and a frequency dividing circuit that divides the output of the voltage controlled oscillation circuit, as set forth in claim 1. , a phase comparator that compares the phase of the demodulated clock and the data string signal, a frequency comparator that compares the frequencies of the demodulated clock and the data string signal, a control circuit, and select output of the output signal of the phase comparator or frequency comparator. a selector, a charge pump,
The configuration includes a low-pass filter.

Further, the PLL circuit of the present invention compares the phases of a voltage controlled oscillation circuit, a frequency dividing circuit that divides the output of the voltage controlled oscillation circuit, and a demodulated clock and a data string signal. A phase comparator, a frequency comparator that compares the frequency of the output clock of the voltage controlled oscillation circuit and the data string signal, a control circuit, a selector that selectively outputs the output signal of the phase comparator or frequency comparator, and a charge pump. and,
The frequency comparator detects how many cycles the output clock of the voltage controlled oscillation circuit enters within the maximum inversion interval of the data string signal, and when the frequency exceeds a predetermined number, the data string signal In contrast, the frequency of the demodulated clock is high and it is determined that the frequency is outside the predetermined range.

Further, the PLL circuit of the present invention compares the phases of a voltage controlled oscillation circuit, a frequency dividing circuit that divides the output of the voltage controlled oscillation circuit, and a demodulated clock and a data string signal. A phase comparator, a frequency comparator that compares the frequency of the output clock of the voltage controlled oscillation circuit and the data string signal, a control circuit, a selector that selectively outputs the output signal of the phase comparator or frequency comparator, and a charge pump. and,
The frequency comparator detects how many cycles the output clock of the voltage controlled oscillator circuit enters within the minimum inversion interval of the data string signal, and if it is smaller than a predetermined number, the frequency comparator In contrast, the frequency of the demodulated clock is low and it is determined that it is outside the predetermined range.

In the invention of claim 1 configured as described above, the control circuit adjusts the phase when the frequency difference between the frequency of the demodulated clock and the frequency of the data string signal is within a predetermined range based on the comparison result of the frequency comparator. The output signal of the comparator acts as the selection output of the selector, and if the frequency difference between the frequency of the demodulated clock and the frequency of the data string signal is outside the predetermined range, the output signal of the frequency comparator acts as the selection output of the selector. Acts to produce an output.

Further, in the invention of claim 2, the frequency comparator detects how many cycles the output clock of the voltage controlled oscillation circuit enters within the maximum inversion interval of the data string signal, and when the frequency exceeds a predetermined number, On the other hand, it is determined that the frequency of the demodulated clock is high and outside the predetermined range, and based on this, the control circuit outputs the output of the phase comparator if the frequency difference between the frequency of the demodulated clock and the frequency of the data string signal is within the predetermined range. The signal acts as the selected output of the selector, and when the frequency difference between the frequency of the demodulated clock and the frequency of the data string signal is outside a predetermined range, the output signal of the frequency comparator acts as the selected output of the selector. It acts on

Further, in the invention according to claim 3, the frequency comparator detects how many cycles the output clock of the voltage controlled oscillation circuit enters within the minimum inversion interval of the data string signal, and if it is smaller than a predetermined number, the frequency comparator On the other hand, the control circuit determines that the frequency of the demodulated clock is low and outside the predetermined range, and based on this, the control circuit outputs the output of the phase comparator if the frequency difference between the frequency of the demodulated clock and the frequency of the data string signal is within the predetermined range. The signal acts as the selected output of the selector, and when the frequency difference between the frequency of the demodulated clock and the frequency of the data string signal is outside a predetermined range, the output signal of the frequency comparator acts as the selected output of the selector. It acts on

Embodiment Below, a PLL circuit that generates a demodulated clock synchronized in phase and frequency with a data string signal, which is an embodiment of the present invention, will be explained with reference to the drawings.

(Embodiment 1) In FIG. 1, 110 is a voltage controlled oscillation circuit, and 111 is a demodulated clock 11 which divides the output of the voltage controlled oscillation circuit 110.
102 is a phase comparator that compares the phase of the demodulated clock 112, which is the frequency-divided output of the frequency dividing circuit 111, and the data string signal 101; 121 is a phase comparator 10;
2 is the charge control signal, 122 is the phase comparator 102
The discharge control signal 1o3 is the output clock 130 of the voltage controlled oscillation circuit 110 and the data string signal 101.
The frequency of the demodulated clock and the data string signal 10 are compared.
123 is a charge control signal by the frequency comparator 103, and 124 is a discharge control by the frequency comparator 103. The signals 104 are the output signals of the frequency comparator 103, which are the charge control signal 123 and the discharge control signal 1.
24 goes to the logic level "H", the control signal 125 to the selector 105 goes to the logic level "H".
”, 1o5 is the output signal of the phase comparator 102 (charge control signal 121 and discharge control signal (122)) and the output signal of the frequency comparator 103 (charge control signal 123 and discharge control signal 124).
), and when the output signal 125 of the control circuit 104 is at the logic level "L", the output signal of the phase comparator 1020 is input, and when the output signal 125 of the control circuit 104 is at the logic level "H", the output signal of the frequency comparator 103 is input. A selector 126 selectively outputs a charge control signal and a discharge control signal.
A charge control signal 127 is a selection output from the selector 105, a discharge control signal 106 is a selection output from the selector 105, and a charge control signal 126 and a discharge control signal 127 are output signals from the selector 105. A charge pump 109 smoothes voltage changes caused by the operation of the charge pump 106 and is connected to the voltage controlled oscillation circuit 11.
This is a low-pass filter that applies a control voltage to 0, and its detailed operation will be explained below.

The PLL circuit configured as shown in FIG.
The difference between the frequency of 01 and the frequency of demodulation clock 112 is PL
When the frequency is outside the frequency capture range of the L circuit, the control circuit 104 outputs the charge control signal 123 and the discharge control signal 124, which are the output signals of the frequency comparator 103, based on the comparison result of the frequency comparator 103. When either one of them becomes a logic level "H", the control signal 125 is set to a logic level "H", and the selected output of the selector 105 is controlled to become the output signal of the frequency comparator 103, and the frequency When both the charge control signal 123 and the discharge control signal 124, which are the output signals of the comparator 103, reach the logic level "L11", the control signal 125 is set to the logic level "L", and the selected output of the selector 105 changes in phase. The output signal is controlled to be the output signal of the comparator 102.

In the above operation, the difference between the frequency of the data string signal 1010 and the frequency of the demodulated clock 112 is within the frequency capture range of the PLL circuit, and the frequency comparator 10
This is repeated until it is reflected in the control signals 123 and 124, which are the comparison results of the frequency comparator 103 (that is, until both the control signals 123 and 124, which are the comparison results of the frequency comparator 103, are constantly at the logic level "L").

The operation of the PLL circuit in this case will be described below.

When the frequency of the demodulated clock 112 is low with respect to the data string signal 101 and is out of a predetermined range, the charge control signal 123 of the frequency comparator 103 is
becomes a logic level "H"', which causes the control circuit 1 to
04, the selected output of the selector 105 is the frequency comparator 10
The selection control signal 125 is set to the logic level "H11" so that the output signal is 3.

The selector 105 outputs a charge control signal 126 and a discharge control signal 127, which are selected outputs, to the frequency comparator 10 according to the instruction of the selection control signal 125.
The charge control signal 123 and discharge control signal 124, which are the output signals of No. 3, are selected and output.

The above operation causes the charge control signal 123 of the frequency comparator 103 to be applied to the P-channel FET 107 of the charge pump 106, and the charge control signal 123 of the frequency comparator 103 to the N-channel FET of the charge pump 106
The discharge control signal 124 of the frequency comparator 103 is given to the ET 108, and in this case, the frequency comparator 10
3 charge control signal 123 is at logic level IIH" (
Since the discharge control signal 124 is at logic level “L”, the P channel F of the charge pump 106
The ET 107 is turned on, and the low-pass filter 109 is charged with electric charge.

Since the amount of charge to be charged has a monotonically increasing relationship with the time width during which the P-channel FET is ON, the amount of charge is controlled by the charge control signal 123 that is the output of the frequency comparator 103.

A predetermined constant time width t during which the charge control signal 123 from the frequency comparator 103 is at logic level "H",
. 9 is a charge control signal 12 from the phase comparator 102;
1 output time width t,. Set longer than 9.

In this case, since the frequency of the demodulated clock 112 is low relative to the data string signal 101 and is outside the predetermined range, the output time width t of the charge control signal 121 by the phase comparator 102. 9 is 0<1. . , <(phase comparison period). Therefore, the predetermined constant time width j rag during which the charge control signal 123 from the frequency comparator 1O3 reaches the logic level +18'' is determined by (phase comparison period) < j ro.

and set.

The low-pass filter 109 smoothes the sudden voltage rise change caused by the charge, and increases the control voltage to the voltage controlled oscillation circuit 110. This increases the oscillation frequency of the voltage controlled oscillation circuit 110, and the demodulated clock 112 frequency becomes high.

On the other hand, for the data string signal 101, the demodulated clock 112
When the frequency of is high and out of the predetermined range, the discharge control signal 124 of the frequency comparator 103 becomes logic level "H" for a predetermined period of time, thereby causing the control circuit 104 to change the selection output of the selector 105. The selection control signal 12 is selected to be the output signal of the frequency comparator 103.
5 is the logic level "H".

The selector 105 outputs a charge control signal 126 and a discharge control signal 127, which are selected outputs, to the frequency comparator 103 according to the instruction of the selection control signal 125.
The charge control signal 123 and discharge control signal 124, which are the output signals of , are selected and output.

By the above-described operation, the charge control signal 123 of the frequency comparator 103 is transferred to the P-channel FET 107 of the charge pump 106, and the charge control signal 123 of the frequency comparator 103 is transferred to the N-channel FET of the charge pump 106.
The discharge control signal 124 of the frequency comparator 103 is given to the ET 108, and in this case, the frequency comparator 10
3 discharge control signal 124 is at logic level “H”
(Since the charge control signal 123 is at logic level "L", the N-channel F of the charge pump 106
Charge is discharged from the low-pass filter 109 when the ET 108 is turned on.

The amount of charge discharged is N-channel FET1
Since there is a monotonically increasing relationship with the time width when 08 is ON,
Discharge control signal 12 which is the output of the frequency comparator
4 controls the amount of charge.

Discharge control signal 12 from frequency comparator 103
The predetermined constant time width t1dOQ in which the signal 4 becomes the logic level "HII" is set to be longer than the output time width jpdog of the discharge control signal 122 by the phase comparator 102.

In this case, the frequency of the demodulated clock 112 is higher than the data string signal 101 and is outside the predetermined range, so the output time width j pdog of the discharge control signal 122 by the phase comparator 102 is 0 < t pdOo <
(phase comparison period). Therefore, the discharge control signal 124 from the frequency comparator 103
A predetermined constant time width j tdoo during which the logic level is “H” is set as (phase comparison period)<t+d6g.

The low-pass filter 109 smoothes the sudden voltage rise change caused by the discharge of charges, and lowers the control voltage to the voltage-controlled oscillation circuit 110. This lowers the oscillation frequency of the voltage-controlled oscillation circuit 110, and the demodulated clock 112 frequency is lowered.

In this way, if the difference between the frequency of the data string signal 101 and the frequency of the demodulated clock 112 is outside the frequency capture range of the PLL circuit, the demodulated clock 112
12 and the data string signal 101, and when the frequency difference falls within a predetermined range, the phase pull-in operation described below is performed.

When the difference between the frequency of the data string signal 101 and the frequency of the demodulated clock 112 falls within the frequency capture range of the PLL circuit, the control circuit 104 controls the selector based on the comparison result of the frequency comparator 103. 10
5 is controlled so that the selected output becomes the output signal of the phase comparator 102.

The operation of the PLL circuit in this case will be described below.

When the phase of demodulated clock 112 is delayed with respect to data string signal 101, charge control signal 121 is output from phase comparator 102, P-channel FET 107 of charge pump 106 is turned on, and low-pass filter 10
9 is charged with electric charge.

The low-pass filter 109 smoothes the sudden voltage rise change caused by the charge, and increases the control voltage to the voltage controlled oscillation circuit 110. This increases the oscillation frequency of the voltage controlled oscillation circuit 110, and the demodulated clock It operates so that the phase of 112 advances.

Also, a demodulated clock 112 is used for the data string signal 101.
When the phase of the charge pump 10 advances, the phase comparator 102 outputs the discharge control signal 122,
6 N-channel FETIO3 is turned on and low-pass
Charge is discharged from filter 109.

The low-pass filter 109 smoothes the sudden voltage drop caused by discharge of charges, and lowers the control voltage to the voltage-controlled oscillation circuit 110. This lowers the oscillation frequency of the voltage-controlled oscillation circuit 110, and the demodulated clock It operates so that the phase of 112 is delayed.

In this way, if the difference between the frequency of the data string signal 101 and the frequency of the demodulated clock 112 is within the frequency capture range of the PLL circuit, the demodulated clock 11
2 and the data string signal 101, and when the phase difference disappears, the low-pass filter 109
The output DC voltage becomes constant, and at this point, the demodulation clock 112 reaches 2 of the maximum repetition frequency of the data string signal 101.
It becomes stable at twice the frequency and in a predetermined phase relationship with the data string signal 101.

(Example 2) FIG. 2 is a diagram showing the internal configuration of the frequency comparator 103 in FIG. 1, and is an example of the frequency comparator according to claims 2 and 3.

In FIG. 2, 201 is an output clock 211 of the voltage controlled oscillation circuit (voltage controlled oscillation circuit 110 in FIG. 1).
(130 in FIG. 1) and data string signal 212 (first
101) in the figure to determine whether the frequency difference between the demodulated clock frequency and the data string signal 212 is within a predetermined range, and also to output the charge control signal 213 and discharge control signal 214 according to the frequency difference. The output frequency comparator 202 detects the rising edge of the data string signal 212, rises simultaneously with the rising edge of the data string signal 212, and rises for a fixed period of time t rptt.
an edge detection circuit that generates a pulse that later falls, 20
3 is a counter that uses the output clock 211 of the voltage controlled oscillator circuit as a clock, performs a counting operation in the interval where the data string signal 212 is at the logic level "H", and resets the counted value by the output pulse of the edge detection circuit 202; an inverter 2 that inverts the polarity of the data string signal 212;
05 is the count result of the counter 203 as the data string signal 2.
A D-flip flop 206 is held at the timing of the falling edge of 12, and a demodulation clock 206 is a demodulation clock that should originally be generated within the minimum inversion interval of the data string signal 212 (that is, a clock with twice the frequency of the data string signal 212). The output clock 211 of the voltage controlled oscillation circuit to obtain N
A detection circuit 207 detects N, , +n 1 when input to m l n, within the maximum inversion interval of the data string signal 212, generates a demodulated clock that should be originally generated (that is, twice the data string signal 212). The output clock 211 of the voltage controlled oscillation circuit for obtaining a frequency clock) is N. 8
a detection circuit for detecting N, ,x+1 if it enters 2;
08 is a charge control circuit that generates the charge control signal 213 based on the output signal 225 of the detection circuit 206, and 209 is a discharge control circuit that generates the discharge control signal 214 based on the output signal 226 of the detection circuit 207. The operation is explained below.

The frequency detector 201, configured as shown in FIG. It is determined that the frequency of the demodulated clock is high relative to the column signal 212 and is outside the predetermined range, and it is also detected how many cycles the output clock 211 of the voltage controlled oscillation circuit enters within the minimum inversion interval of the data column signal 212, and the frequency is determined to be outside the predetermined range. If the frequency of the demodulated clock is smaller than the number, it is determined that the frequency of the demodulated clock is low relative to the data string signal and is outside the predetermined range.

This operation will be explained in detail using FIG.

FIG. 3 is a waveform diagram for explaining the operation of the frequency detector.

In FIG. 3, a is a digital audio interface signal which is an example of a data string signal, the part indicated by A is the maximum signal inversion interval (3T), and the part indicated by B is the minimum signal inversion interval (3T). IT).

However, the maximum inversion interval can be as long as 108% of the original interval of 3T due to the definition of the duty of the transmission signal according to the digital audio interface standard. Further, the minimum reversal interval can be shortened to 80% of the original interval IT due to the above regulation.

b is a demodulated clock, which is a clock obtained by dividing the output clock of the voltage controlled oscillation circuit by two. Demodulation clock is PL
When the L circuit is in the clocked state, the period is IT.

C1, C2, and C3 are output clocks of the voltage controlled oscillation circuit in the PLL circuit whose frequency is almost completely pulled in.

However, C1 is the case where the phase is also completely drawn in, and both C2 and C3 are the output clocks of the voltage controlled oscillation circuit in the PLL circuit in a state where the phase is not completely drawn in.

Now, the number of cycles of the output clock of the voltage controlled oscillator circuit is detected within the maximum inversion interval of the data string signal, and if it exceeds a predetermined number, the frequency of the demodulated clock is higher than the data string signal, and the frequency falls within the specified range. In this case, the predetermined number N0. × can be determined by considering the case where the maximum reversal interval is increased to 108% of the original interval of 3T.
, NNAX is 7. Therefore, it is detected how many cycles the output clock of the voltage controlled oscillation circuit enters within the maximum inversion interval of the data string signal, and if it is greater than 7, it is determined that the frequency of the demodulated clock is higher than the data string signal and is outside the predetermined range. do.

For example, when the detected value is 12 to 14, it can be determined that the frequency of the demodulated clock is about twice as high as the data string signal and is outside the predetermined range.

Next, it detects how many cycles the output clock of the voltage controlled oscillator circuit enters within the minimum inversion interval of the data string signal, and if it is smaller than a predetermined number, the frequency of the demodulated clock is low relative to the data string signal, and it falls within the predetermined range. However, in this case, the predetermined number N M I N is as short as 80% of the original interval IT. Therefore, the number of cycles of the output clock of the voltage controlled oscillation circuit within the minimum inversion interval of the data string signal is detected, and if it is less than 1, it is determined that the frequency of the demodulated clock is low relative to the data string signal and is outside the predetermined range. judge.

Next, the operation of the frequency detector in the configuration shown in FIG. 2 will be explained.

The counter 203 receives the data string signal 212 at the count enable terminal, the output clock 211 (130 in FIG. 1) of the voltage controlled oscillation circuit 110 shown in FIG. 1 at the clock terminal, and the output of the edge detection circuit 202 at the reset terminal. A signal 221 is input.

The edge detection circuit 202 detects the rising edge of the data string signal 212, and generates a pulse that rises simultaneously with the rising edge of the data string signal 212 and falls after a predetermined time t rpir. Here, the time t79. which becomes the output pulse width of the edge detection circuit 202. is the time j r required to reset the count value of the counter 203
If it is mln or more, it will be set as short as possible.

With the above configuration, the counter 203 counts the number of output clocks 211 of the voltage controlled oscillator circuit during the period of the logic level "H" of the data string signal 212 (excluding the time trpw after the rising edge). is counted, and the count value is reset at the leading edge of the next logical level "H" interval (an interval of time width t rpw from the rising edge).

Therefore, the count value of the counter 203 becomes maximum when the maximum inversion interval of the data string signal 212 appears at the logic level "HI+", and when the minimum inversion interval of the data string signal 212 appears at the logic level "H". is the minimum.

However, if the PLL circuit is in the phase pulling process,
The data string signal 212 and the output clock 211 of the voltage controlled oscillation circuit do not have a constant phase relationship and rotate within one cycle of the output clock 211 of the voltage controlled oscillation circuit.
The count value of the counter 203 is the maximum value (i.e., the count value when the maximum inversion interval of the data string signal 212 appears at logic level "H") and the minimum value (i.e., the minimum inversion interval of the data string signal 212 is at the logic level "H"). “H
”) also has a width of 1 count.

Therefore, the output clock of the voltage controlled oscillator circuit for obtaining the demodulated clock that should originally be generated (that is, the clock with twice the frequency of the data string signal) within the minimum inversion interval and the maximum inversion interval of the data string signal 212. When considering how many times 211 will enter lock, if we estimate that the minimum value is 1 clock less and the maximum value is 1 clock more, we get the minimum count value that counter 203 can actually take when the PLL circuit is in the phase pull-in process. , the count dissipates to the maximum value. Let these be Nm1n (minimum count value) and N1°8 (maximum count value), respectively.

The D flip-flop 205 receives the count result of the counter 203 and a signal 223 obtained by inverting the data string signal 212 by the inverter 204 as a clock. hold it.

The detection circuit 206 determines that the count result N of the counter 203 held in the D flip-flop 205 satisfies N<N-t.

When it is detected that the oscillation frequency of the voltage controlled oscillation circuit is low, the D flip-flop 205
N71. While the count result of l is held,
The output signal 225 is set to logic level "H".

The charge control circuit 208 rises simultaneously with the rising edge of the output signal 225 of the detection circuit 206 for a predetermined time t. . A charge control signal 213 that falls later is generated.

Here, the predetermined constant time width j 169 is determined by the phase comparator (the first
The output time width t of the charge control signal (121 in FIG. 1) by 102) in the figure.

. Set longer.

In this case, since the frequency of the demodulated clock is low with respect to the data string signal 212 and is outside the predetermined range, the output time width t of the charge control signal by the phase comparator. , is 0〈t. . It changes within the range of (phase comparison period).

Therefore, the charge control signal 213 reaches the logic level H11.
A predetermined constant time width t"..., (phase comparison period) <t"...

and set.

The detection circuit 207 detects that the count result N of the counter 203 held in the D flip-flop 205 is N, , <
When N is detected, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is high, and the D flip-flop 205 is set to N,
, , While the count result of <N is held, the output signal 226 is set to the logic level "'H".

The discharge control circuit 209 rises simultaneously with the rising edge of the output signal 226 of the detection circuit 207.
A discharge control signal 214 that falls after a predetermined time t0°9 is generated.

Here, the predetermined constant time width ttdoa is determined by the phase comparator (the first
It is set longer than the output time width j pdog of the discharge control signal (122 in FIG. 1) by 102 in the figure.

In this case, the frequency of the demodulated clock is higher than the data string signal 212 and is outside the predetermined range, so the output time width j pd of the discharge control signal by the phase comparator
ag changes within the range of 0 < j pdoa < (phase comparison period).

Therefore, the discharge control signal 214 is at the logic level "
A predetermined constant time width jzoo at which the signal becomes “H” is set as 1 (phase comparison period)<t+daa.

In this way, the difference between the frequency of the data string signal 212 and the frequency of the demodulated clock is the frequency pull-in range of the PLL circuit (
The data string signal 21 indicates that it is outside the capture range.
2 and the oscillation frequency of the voltage controlled oscillation circuit, and based on the frequency comparison result, the PLL circuit shown in Example 1 detects the frequency difference between the demodulated clock and the data string signal 212. A signal is generated to operate the device so that the amount decreases.

As described in detail of the invention, when the difference between the frequency of the data string signal and the frequency of the demodulated clock is outside the frequency capture range of the PLL circuit, the frequency comparator detects this and The frequency pull-in operation is performed so that the difference between the frequency of the data string signal and the frequency of the demodulated clock is within the frequency pull-in range of the PLL circuit, so it is possible to expand the actual frequency pull-in range.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a PLL circuit which is a first embodiment of the present invention, Fig. 2 is a block diagram of a frequency comparator which is a second embodiment of the invention, and Fig. 3 is an operation of the same embodiment. A waveform diagram for explanation and FIG. 4 is a block diagram showing an example of a conventional PLL circuit. 101...Data string signal, 102...Phase comparator, 103.201...Frequency comparator, 104.
...Control circuit, 105...Selector, 106
...Charge pump, 107...P channel FET1 108...N channel FET, 10
9...Low pass filter, 110...Voltage controlled oscillation circuit, 111...Frequency dividing circuit, 112.
... Demodulation clock, 202 ... Edge detection circuit,
203...Counter, 204...Inverter,
205...D flip-flop, 206,
207...Detection circuit, 208...Charge control circuit, 209...Discharge control circuit.

Claims (3)

[Claims] (1) A voltage-controlled oscillator circuit that generates a demodulated clock for a data string signal, a frequency divider circuit that divides the output of the voltage-controlled oscillator circuit, and a frequency-divided output of the frequency divider circuit as a variable input, and a data string signal. a phase comparator that compares the phases of the two using as a reference input and outputs a signal according to the phase difference; a charge pump that charges or discharges a charge for applying a control voltage to the voltage controlled oscillation circuit; In a PLL circuit comprising a low-pass filter that smoothes voltage changes due to charge pump operation and applies a control voltage to the voltage controlled oscillation circuit, the output clock of the voltage controlled oscillation circuit and the data string signal are compared. a frequency comparator that determines whether the frequency difference between the demodulated clock frequency and the data string signal is within a predetermined range and outputs a signal according to the frequency difference for a predetermined time; and the frequency comparator a control circuit that generates a control signal to the selector based on the determination result; and an output signal of the phase comparator and an output signal of the frequency comparator are input, and depending on the output signal of the control circuit, one of the and a selector that selectively outputs a control signal for controlling charge and discharge operations of the charge pump, and the selector is configured to select whether the comparison result by the frequency comparator is
When the frequency difference between the frequency of the demodulated clock and the frequency of the data string signal is within a predetermined range, the output signal of the phase comparator is selected and output based on the instruction of the control circuit, and the frequency comparator performs a comparison. A PLL circuit that selectively outputs the output signal of the frequency comparator based on an instruction from the control circuit when the result is outside a predetermined range. (2) The frequency comparator detects how many cycles the output clock of the voltage controlled oscillation circuit enters within the maximum inversion interval of the data string signal, and if it exceeds a predetermined number, the frequency comparator detects the demodulated clock for the data string signal. 2. The PLL circuit according to claim 1, wherein the frequency is determined to be high and outside a predetermined range. (3) The frequency comparator detects how many cycles the output clock of the voltage controlled oscillation circuit enters within the minimum inversion interval of the data string signal, and if it is smaller than a predetermined number, 2. The PLL circuit according to claim 1, wherein the PLL circuit determines that the frequency is low and outside a predetermined range.