GB2161660A - Digital phase/frequency detector having output latch - Google Patents

Digital phase/frequency detector having output latch Download PDF

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GB2161660A
GB2161660A GB08512666A GB8512666A GB2161660A GB 2161660 A GB2161660 A GB 2161660A GB 08512666 A GB08512666 A GB 08512666A GB 8512666 A GB8512666 A GB 8512666A GB 2161660 A GB2161660 A GB 2161660A
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phase
frequency
means
input
duty ratio
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GB8512666D0 (en
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Steven P Cok
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Fluke Corp
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Fluke Corp
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Abstract

A digital phase/frequency detector circuit in a phase locked loop comprises a logic gate 24 interconnected with a pair of bistable devices 20, 22 clocked respectively by input and reference digital signals to V, R generate a square wave having a duty ratio corresponding to the phase/frequency difference between the two signals. The duty ratio of the square wave sweeps repetitively between minimum and maximum values as the phase/frequency difference changes monotonically. The square wave is integrated 36 to obtain a repetitive sawtooth having a maximum average output that is one-half the sawtooth peak. To increase the maximum average output of the detector for improving the phase/ frequency acquisition of the loop when the phase/frequency difference is greater than 360 DEG , additional bistable devices 64, 66 latch the detector output to the maximum duty ratio (peak value of the sawtooth) as the phase/frequency difference sweeps past one full cycle in either direction. <IMAGE>

Description

SPECIFICATION Digital Phase/Frequency Detector having Output Latch Technical Field This invention relates generally to circuits for comparing the phase/frequency difference between two digital input signals, and more particularly, toward a method of and circuitry for improving phase/frequency acquisition of a digital phase/ frequency detector in a phase locked loop by increasing the effective maximum average output of the detector when the phase/frequency difference between the two input signals is greater than one cycle.

Background Art Circuitry for detecting the difference in phase and frequency between two digital input signals has general utility in signal analysis and is of particular importance in digital communications and frequency synthesis. In a digital phase locked loop, for example, an input signal is applied to a phase detector for comparison with a reference signal. An error signal, which is a function of the instantaneous phase/frequency difference between the input signals, is filtered and applied to control a voltage controlled oscillator (VCO). The output of the VCO, which constitutes the output of the phase locked loop, is applied as the reference signal to the phase detector to cause the phase/frequency of the VCO to "lock" to the phase/frequency of the input signal.In some applications, phase locked loops are used for signal demodulation as discussed in Gardner, Floyd M., Phase Lock Techniques, Second Edition, 1979, John Wiley & Sons. Chapter 9. In other applications, phase lock loops are used for signal modulation (Gardner, Chapter 9, supra) or in frequency synthesis as described in Erps petal U.S. Patent 4,360,788, assigned to us.

In any case, a conventional digital phase/ frequency detector comprises a pair of flip flops or other bistable devices connected together and with a logic gate in a feedback circuit. The logical states of the two flip flops are determined both by the two digital input signals whose frequency/phase difference is to be detected and by the feedback gate. With the flip flops initially reset, the data terminals of both are connected to a logic "1" and the clock terminals are connected respectively to the two input digital signals. The output of each flip flop is set to a logic "1" upon detection of a positive transition of its input signal. Thus, if the input signal applied to the first flip flop has the first positive transition, the first flip flop is set to a logic "1" and thereafter, the second flip flop, upon a positive transition by its input signal, becomes set to a logic "1".Immediately after the second flip flop becomes set, however, both of the flip flops are reset by the logic gate which responds to the outputs of the two flip flops, and both remain reset until one flip flop or the other detects a positive signal transition at its input.

The outputs of the two flip flops thus are square waves having duty ratios that correspond to the phase/frequency difference between the two input signals. If the first signal leads the second signal, only the first flip flop develops a square wave, with the duty ratio corresponding to the amount of phase/frequency lead between the two input signals. If the second input signal leads, only the second flip flop develops a square wave with a duty ratio that corresponds to the amount of phase lead of the second input signal relative to the first. The two square waves are combined in a difference circuit and the resultant is integrated to obtain a sawtooth centered about zero, that is, the sawtooth has one polarity when the first input signal leads and the opposite polarity when the second input signal leads.The sawtooth has an amplitude that corresponds to the phase/frequency difference between the two digital input signals and has a fixed period of 360 . As the phase/frequency difference between the two input signals increases monotonically, the output of the detector is a sawtooth train having a number of sawtooth cycles that corresponds to the number of full cycles of phase/frequency difference between the two digital input signals.

The output of the detector, when filtered to cause the output of the VCO to lock to the input signal, is one-half the peak magnitude of the sawtooth. This factor seriously limits the maximum slew rate of the detector output, increasing the amount of time required to return the reference signal into the active region (within one full cycle of an input signal) of the detector to acquire phase lock.

Furthermore, because filtering in the phase locked loop to reduce spurious signals imparts a phase shift into the loop, a voltage bias corresponding to a phase offset is applied to the loop to reduce modulation distortion. In practice, the amount of bias required in a frequency synthesizer of the type disclosed in the Erps patent, supra, is 40 percent of the peak output of the detector. Because the maximum average output of the detector is only 50 percent of the sawtooth peak, the 10 percent margin between the bias and maximum average is inadequate, and the phase lock loop has a tendency to "false-lock". A detailed discussion of this and other deleterious effects of phase shift caused by filtering in a phase locked loop is covered in Section 8.1 of the Gardner text, supra.

There accordingly exists a need to eliminate false lock and other problems caused by interaction between the loop filter and small margin between bias and.maximum average output in the phase detector of a digital phase locked loop by increasing the maximum average output of the detector. A need further exists to reduce the acquisition speed of a digital phase locked loop by increasing the maximum average output of its phase detector when the input and reference signals are out of lock.

Disclosure of invention A primary object of the invention is, therefore, to provide a method of and circuit for increasing the maximum average output of a digital phase/ frequency detector.

Another object is to provide a digital phase locked loop wherein signal acquisition time is reduced by increasing the maximum average output of its phase/frequency detector.

A further object is to provide a method of and circuit for increasing the maximum average output of a digital phase/frequency detector by latching the detector output to a peak value when the phase/ frequency difference between the input and reference signals is greater than a predetermined amount.

An additional object is to improve the conventional digital phase/frequency detector of a type that generates a repetitive sawtooth as a function of the phase/frequency difference between the input and reference digital signals by latching the detector output to the sawtooth peak when the phase/frequency difference is greater than one cycle.

The above and other objects of the invention are achieved, in accordance with the invention, by peak latching the output of a conventional digital phase/ frequency detector of a type that generates a repetitive sawtooth as a function of the phase/ frequency difference between input and reference digital signals. In accordance with the method of the invention, input and reference signals are applied to the inputs respectively of a pair of bistable devices, such as flip flops, having a logic gate connected in a feedback circuit with the devices. Outputs of the two devices constitute square waves having duty ratios depending upon the instantaneous phase difference between the input and reference signals and on which of the two signals leads.These two signals are subtracted and integrated to obtain a repetitive sawtooth having a slope and polarity corresponding to the duty ratios of the square waves generated by the two bistable devices. The average maximum output of the repetitive sawtooth is one-half the sawtooth peak. To effectively double the maximum average output, the outputs of the bistable device are latched to cause the square wave generated by one or the other of the bistable devices, depending upon whether the input or reference signal leads, to have a duty ratio of 100 percent when the phase/ frequency difference exceeds one cycle. The sawtooth is thus latched to its peak, doubling the magnitude of the detector signal to move the phase locked loop toward acquisition.

Circuitry comprising the conventional digital frequency/phase detector includes means for receiving input and reference signals and means for generating square waves having a duty ratio corresponding to the phase/frequency difference between the input and reference signals, wherein the duty ratio is repetitive with each cycle of the phase/frequency difference. The improvement comprises a means for latching the output of the square waves generating means to be at maximum when the phase/frequency difference between the input and reference signals is greater than the fixed period.

In accordance with more specific aspects of the invention, the phase/frequency detector constitutes the detector of a phase locked loop comprising a filter and voltage controlled oscillator as well as the detector, with the output of the oscillator being applied as the reference signal to the phase detector. The square waves generating means preferably comprises bistable devices, particularly D-type flip flops, and the fixed period is a full cycle, or 360 , of the phase/frequency difference.

In accordance with a further more specific aspect of the invention, the latching means comprises a pair of additional flip flops connected in circuit with the square waves generating flip flops and with an additional pair of logic gates to latch the output of one or the other of the square waves generating flip flops, depending upon whether the input signal or reference signal leads, when the phase/frequency difference is greater than one cycle.

Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description of an embodiment of the invention given simply by way of illustration. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention.

Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.

Brief Description of the Drawings Figure 1 is a block diagram of a conventional digital phase locked loop of the type within which the frequency/phase detector of the invention may be incorporated; Figure 2 is a circuit diagram of a conventional digital phase/frequency detector upon which the present invention is an improvement; Figures 3(1 )-3(5) are wave forms illustrating the operation of the conventional digital phase/ frequency detector of Figure 2; Figure 4 is the output characteristic of the conventional phase/frequency detector of Figure 2; Figure 5 is the desired characteristic of the digital phase/frequency detector improved in accordance with the principles of the invention; Figure 6 is a circuit diagram of an embodiment of the invention; and Figure 7(1 )-7(7) are wave forms explaining the output latching characteristic of the circuit shown in Figure 6.

Description of the Embodiment The invention is designed to reduce acquisition time and prevent false locking in a digital phase locked loop of the type described in Erps et al U.S.

Patent 4,360,788 and Cok et al US Patent Application Serial No. 638,631 filed 7th August 1984, incorporated within the Model 6060A frequency synthesizer, manufactured by John Fluke Mfg. Co., Inc., Everett, Washington. The improvement is made by latching the output of the digital phase/ frequency detector at a constant maximum value when phase and frequency error measured by the detector is greater than one cycle, as described in detail below.

With reference to Figure 1, the conventional phase locked loop, designated generally by 10, comprises a phase detector 12 of a type to which the present invention is directed, a filter 14 and a voltage control oscillator (VCO) 16 connected in a forward loop.

Phase detector 12 has one input that receives an input signal F, and a second input that receives a reference signal Fr and generates a signal corresponding to the difference in phase and frequency between the two input signals. The detector signal is filtered or smoothed by filter 14 and applied as a control input to VCO 16. The output of VCO 16 is fed back through programmable frequency divider 18 as the reference signal F, to phase detector 12. As described in detail in the Erps et al patent, supra, the signal generated by VCO 16 is controlled to have a frequency that is a multiple or submultiple, depending upon the programming of frequency divider 18, of the input signal Fi and a phase having a predetermined relationship, depending upon offset biasing incorporated in detector 12, relative to the phase of the input signal.

It is to be understood that, although a particularly important application of the phase detector of the invention is in a phase locked loop such as the one shown in Figure 1, the phase detector has numerous other significant applications in signal processing and in signal measurement.

The present invention has particular utility in a phase locked loop of the type incorporated into the Model 6060A frequency synthesizer, however, since the substantially increased maximum average output of the detector compared with the prior art is important to eliminate interaction between phase shift impressed in the loop by filter 14 and other components and a relatively small margin that exists between offset phase and the maximum average output of the conventional phase detector.

The relatively low maximum average output ot the conventional phase/frequency detector upon which the invention is an improvement must be fully understood before the present invention can be appreciated. A conventional detector, shown in Figure 2, comprises a pair of flip flops 20, 22 which for purposes of illustration are shown as D-type flip flops. In a D-type flip flop, a logic level applied to the D terminal is transferred to the Q output terminal upon the occurrence of a rising clock pulse applied to the clock terminal. Each D-type flip flop 20, 22 also has a output terminal which develops the logical complement of the 0 output terminal, and a reset terminal R that, in response to a logic "0" or "low" signal, resets the 0 output terminal to a logic "0".

For purposes of illustration, the flip flops 20, 22 are assumed to operate on positive logic, i.e., a logical "1" is defined as a "high" voltage and a logical "0" is defined as a "low" voltage.

A NAND gate 24 has two inputs connected respectively to the Q output terminals of flip flops 20, 22 and an output terminal connected to the reset terminals R of the two flip flops. The D input terminal of each of the flip flops 20, 22 is connected to a logic "1" and the two clock terminals are connected respectively to a first (input) signal V and a second (reference) signal R. The input signal V may correspond to Fj and input signal R may corresponds to signal Fr in Figure 1, although the two signals V, R may be arbitrary. Also, although both of the signals V, Rare, in the general case, digital or square wave signals having variable and different frequencies and phases, the signal R, may be a reference signal having a fixed frequency and phase.

The Q outputs of flip flops 20,22, designated respectively as 26, 28 are applied to optional filters 30,32 to develop output signals U, Land then to a subtractor or difference circuit 34. The output of difference circuit 34 is typically averaged or smoothed in integrator 36. When the detector circuit 12 is applied in a phase locked loop, output integration is performed by the standard phase locked loop filter, such as 14 in Figure 1.

As an overview of the detector 12, the Q output terminal of each flip flop 20, 22 is set to a logic "1" in response to the positive transition of its input clock caused by either input signal V or input signal R. If both of flip flops 20, 22 are set, however, the output of NAND gate 24 applies a logic "0" level to the reset terminals R of each flip flop, causing both Q output terminals to reset to logic "0". Thus, one or the other of flip flops 20, 22 will be set depending upon which of the input signals V or R has a positive transition that arrives first; both flip flops will become reset upon the arrival of the positive transition of the second one of the input signals V, R.

The two flip flops 20, 22 thus generate square waves having duty ratios that correspond to the phase and frequency difference between the two input signals; if input signal V leads input signal R, flip flop 20 dominates and generates a square wave and flip flop 22 does not; if input signal R leads flip flop 22 dominates and generates a square wave and flip flop 20 does not.

The operation of detector 12, and the manner by which it relates to the improvement, are explained in more detail with reference to Figure 3 showing typical wave forms generated within the phase detector and to Figure 4 illustrating the output wave form.

Figure 3(1) and Figure 3(2) represent respectively input signals V and R applied to the clock terminals of flip flops 20 and 22. These two input signals are at different frequencies and may have different duty ratios, although duty ratios are of no significance since each flip flop 20, 22 is leading edge responsive. Figures 3(3) and 3(4) are output signal wave forms of the signals on lines 26 and 28.

Assume that both flip flops 20,22 are initially reset by the first positive transition 38 of input signal V whereby the Q outputs of both flip flops 20 and 22 are at logic "0" as shown at 40, 42 in Figures 3(3) and 3(4). The next positive transition of input signal R at 44 in Figure 3(2) causes the output Q terminal of flip flop 22 to set to a logic "1" as shown at 46 in Figure 3(4). On the occurrence of the next positive transition of input signal V at48 in Figure 3(1), the Q output terminal of flip flop 20 begins to set at a logic "1", and gate 24 responds almost immediately to reset both flip flops driving the 0 output of flip flop 22 back to a logic "0" as shown at 50 in Figure 3(4).

It is apparent that this cycle of events repeats upon the occurrence of the positive transition of input signal R at 52 and of input signal V at 54, and is repeated again on the occurrence of the positive transitions of the R and V input signals at 56 and 58.

During this period of time, flip flop 22, being "dominant" generates a square wave having a duty ratio that decreases with a decreasing phase/ frequency difference between the two input signals R and V, and that the output of the other flip flop 20 is at a logic "0".

After the occurrence of the positive transition of input signal V at 60, however, the frequency of pulses applied to the clock terminal of flip flop 20 is such that there will be two pulses, one having a positive transition at 58 and the next pulse having a positive transition at 60 before the occurrence of the next pulse by input signal R at positive transition 62.

The effect of the second successive pulse at 60 is to now set the output of flip flop 22 to a logic "1" since both flip flops 20, 22 were previously reset prior to positive pulse transition 60. Subsequently, positive transition of input signal Rat 62 will reset the Q output of flip flop 20, and the sequence continues with flip flop 20 enabled and flip flop 22 disabled as shown in Figures 3(3) and 3(4). The sequence will eventually recycle as the phase and frequency difference between the input signals V and R changes, with one of the flip flops always being enabled and generating a square wave having a duty ratio that corresponds to the phase/frequency difference and the other flip flop being disabled.

Which of the two flip flops 20, 22 is the enabled one at any time depends upon which one of the input signals V, R leads.

As mentioned, the output lines 26,28 of flip flops 20,22 are passed through optional low pass filters 30,32 to difference circuit 34 whose output is averaged or smoothed by integrator 36.

The difference signal, smoothed by~36,~is a sawtooth shown in Figure 3(5) that passes through "0" when "dominance" is transferred between flip flops 20 and 22 as shown in the region illustrated by Figures 3(1)~3(4) and is repetitive with a period of a full cycle (2tut) of phase/frequency as shown in Figure 4. When two input signals V and R are within a positive or negative single cycle of being synchronized to each other or "locked", the detector characteristic is said to be in the "active region" as shown in Figure 4.When the two input signals are outside the active region, the phase detector 12 generates a sawtooth having a maximum average signal (see dotted lines in Figure 4) that has a magnitude of one-half the peak magnitude of the sawtooth and a polarity that depends upon which of the two signals leads.

Because the maximum average value of the sawtooth is only one-half the peak, the magnitude of the detector signal when the two input signals are substantially separated from each other in phase and frequency is limited, and the problem is aggravated by the small margin between offset phase and the maximum average output, as discussed above.

The present invention is an improvement on the conventional digital phase/frequency detector, wherein the maximum average output is increased to the peak value of the output sawtooth, as shown in Figure 5 when the phase/frequency difference between the two input signals is outside the active region. Thus, referring to Figure 6, the conventional digital phase/frequency detector circuit 12 is partitioned from the remainder of the circuit by a dotted line. A circuit to latch the output of the detector 12 to a maximum output corresponding to the peak value of the sawtooth of Figure 4 comprises an additional pair of D flip flops 64 and 66 and a pair of NOR gates 68,70. The gate 68 is connected in circuit with flip flops 64 and 20 whereas gate 70 is connected in circuit with flip flops 22 and 66.Gate 68 has its inverting inputs connected to thenoutput terminals of flip flops 64 and 20 and has its output connected to the D terminal of flip flop 64. Correspondingly, the inverting inputs of gate 70 are connected to theB outputs of flip flops 22 and 66 and the gate output is connected to the D terminal of flip flop 66. The reset terminal R of flip flop 64 is connected to then terminal of flip flop 22, and the reset terminal R of flip flop 66 is connected to theUterminal of flip flop 20.

Assume initially that input signals V and R have a frequency/phase difference that falls within the active region shown in Figure 4. Positive transistions applied to the clock terminals of flip flops 20 and 22 will alternate, causing one or the other of the flip flops to be dominant, depending upon which one of the signals V, R leads. With latching flip flops 64 and 66 being initially reset, the Output of each is at a logic "1" and gates 68,70 are enabled to pass the outputs of flip flops 20 and 22.

The outputs of the two flip flops 20 and 22 are thus as shown in Figures 3(3) and 3(4), and shall not be described. The outputs of flip flops 64 and 65 are latched, however, to disable gate 68 or 70, respectively, when the phase/frequency difference between the input signals sweeps beyond the active region shown in Figure 4.

Gate 68 is disabled it flip flop 20 is dominant and is outside the active region, latching gate output C and thus output U at a maximum and gate 70 is disabled if flip flop 22 is dominant and outside the active region, latching output Lto a maximum. Flip flop 64 detects that flip flop 20 is dominant and outside the active region by responding to two successive positive transitions of input signal V within two successive positive transitions of the other input signal R; flip flop 64 thus detects that the frequency and phase differential between input signals V and R is greater than one cycle and in response, disables output gate 68. Operation is shown in Figures 7(1 )-7(7). Input signals V and R are shown in Figures 7(1) and 7(7), respectively. The Output of flip flop 64 is designated as "a" in Figure 7(2), the outputUof flip flop 20 is designated as "b" in Figure 7(3), the output of gate 68 is designated as "c" as shown in Figure 7(4), and Figure 7(5) is the reset signal d on flip flop 20. The reset signal on flip flop 64 is shown in Figure 7(6) as e.

For simplicity, only the operation of the upper half of Figure 6 will be considered in detail; the operation of the lower half of the circuit is similar.

Assume that flip flops 20,22 are both initially reset by the output of gate 24 at 76 in waveform d, Figure 7(5), and that flip flops 64,66 are also initially reset.

Thenoutput of all four flip flops are thus at a iogicl "1" only outputsnof flip flops 64,20 are shown in figures 7(2) and 7(3) for simplicity. The output C of gate 68, together with the D input of flip flop 64, is thus initially at a logic "0". Upon the first positive transition of input signal V at 72 in Figure 7(1), then output b of flip flop 20 switches to a logic "0" at 74 in Figure 7(3). The output C of gate 68 switches to a logic "1" as shown at 75 in Figure 7(4), and a logic "1" is applied to the D input of flip flop 64.

Before a positive transition of signal R in Figure 7(7) occurs, a second positive transition of signal V takes place as shown at 77 in Figure 7(1); this is the condition that identifies that the phase/frequency difference between R and V is outside the active region. Thenoutput b of flip flop 20 remains at a logic "0" and thenoutput a of flip flop 64 at 78 in Figure 7(2) switches to a logic "0". The output C of gate 68 is now "latched"; the output C and corresponding signal U are at a logic "1" independent of the state of theUoutput b of flip flop 20. In other words, subsequent resetting of flip flop 20 [see cross/hatched region in Figure 7(3) ] by gate 24 does not affect the state of gate signal C.Thus, whereas flip flop 20 generates a variable duty ratio square wave which is integrated to develop a repetitive sawtooth in Figure 4 as the phase/frequency difference between input signal R, V sweeps past one cycle, the output VO of integrator 36 is clamped to the peak of the sawtooth, as shown in Figure 5.

The gate 68 remains disabled until the phase/ frequency difference between signals R, V returns to the active region, i.e., the difference is less than one cycle. This is characterized by a logic "0" signal at the#output of flip flop 22, shown by 79 in Figure 7(6), indicating that input signal R is no longer lagging input signal V. The logic "0" signal developed at thenoutput of flip flop 22 is applied, through line 80, to the reset terminal R of flip flop 64, suitably filtered by a low pass filter R, C. This resets flip flop 64 and enables gate 68 to pass theUoutput of flip flop 20 to difference circuit 34.

In this disclosure, there is shown and described only the preferred embodiment of the invention, but, as aforementioned, it is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.

Claims (9)

1. A digital phase/frequency detector circuit for detecting differences in phase and frequency between an input signal and a reference signal, comprising: means for receiving the input and reference signals; means for generating square waves having a duty ratio corresponding to a phase and frequency difference between said input and reference signals, the duty ratio being repetitive with each cycle of said phase and frequency difference; and means for latching said duty ratio to a maximum duty ratio when said phase and frequency difference is greater than one cycle thereof.
2. The circuit of claim 1, including means for integrating said square waves to obtain a sawtooth having a slope corresponding to the duty ratio of said square waves; and wherein an output of said latching means is constant at the peak magnitude of said sawtooth.
3. The circuit of claim 1, wherein said reference signal has a constant frequency and phase.
4. The circuit of claim 1, wherein said square waves generating means comprise flip flops.
5. A digital phase locked loop, comprising phase detector means responsive to an input signal and a reference signal for generating an error signal as a function of a phase and frequency difference between said input and reference signals, means for filtering said error signal to obtain a filtered error signal and oscillator means responsive to said filtered error signal for generating an output signal applied to said phase detector means as said reference signal, said phase detector means comprising: means for generating square waves having a duty ratio corresponding to a phase and frequency difference between said input and reference signals, said duty ratio being repetitive with each cycle of said phase and frequency difference; means for integrating said square waves to obtain a sawtooth having a slope corresponding to the duty ratio of said square waves; and latching means for developing a constant output signal having the peak magnitude of the sawtooth when said phase and frequency difference is greater than one cycle thereof.
6. A digital phase/frequency detector circuit for detecting differences in phase and frequency between an input signal and a reference signal, comprising means for receiving the input and reference signals; first and second bistable devices having inputs connected to receive respectively said input and reference signals and further connected to a fixed voltage source; a logic gate; said first and second bistable devices having outputs connected respectively to inputs of said logic gate and having additional inputs responsive to an output of said logic gate, said bistable devices generating a square wave having a duty ratio corresponding to phase and frequency difference between said input and reference signals, the duty ratio being repetitive with each cycle of said phase and frequency difference;; means for integrating outputs of said first and second bistable devices to provide a sawtooth; and means for latching outputs of said first and second bistable devices when said phase and frequency difference is greater than one cycle thereof.
7. In a digital phase/frequency detector for comparing the frequency and phase of an input signal with the frequency and phase of a reference signal, the detector being of a type comprising first and second bistable circuit means responsive respectively to said input and reference signals for generating a square wave having a duty ratio corresponding to a phase and frequency difference between the input and reference signals, the duty ratio being repetitive with each cycle of said phase and frequency difference, and means for integrating an output of said bistable circuit means to develop a sawtooth, the improvement comprising: means for latching the bistable circuit output to a maximum duty ratio when said phase and frequency difference is greater than one cycle thereof.
8. In a digital phase/frequency detector for comparing the frequency and phase of an input signal with the frequency and phase of a reference signal, the detector being of a type comprising first and second bistable circuit means responsive respectively to said input and reference signals for generating a square wave having a duty ratio corresponding to a phase and frequency difference between the input and reference signals, the duty ratio being repetitive with each cycle of said phase and frequency difference, and means for integrating an output of said bistable circuit means to develop a sawtooth, method of increasing the maximum average output signal of said detector comprising the step of latching the bistable circuit output to a maximum duty ratio when said phase and frequency difference is greater than one cycle thereof.
9. A digital phase/frequency detector circuit substantially as hereinbefore described with reference to Figures 5 to 7 of the accompanying drawings.
GB08512666A 1984-07-10 1985-05-20 Digital phase/frequency detector having output latch Withdrawn GB2161660A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2587498A1 (en) * 1985-04-29 1987-03-20 Fluke Mfg Co John Detector of digital phase and/or frequency over a wide range
EP0283160A2 (en) * 1987-03-18 1988-09-21 Marconi Instruments Limited Phase comparators
EP0316543A2 (en) * 1987-11-20 1989-05-24 Motorola Inc. Frequency synthesizer having digital phase detector with optimal steering and level-type lock indication
US4884035A (en) * 1987-08-17 1989-11-28 John Fluke Mfg. Co. Inc. Wide range digital phase/frequency detector
EP0991193A1 (en) * 1998-09-29 2000-04-05 Philips Electronics N.V. Radio apparatus comprising a frequency synthesiser and phase discriminator for such an apparatus
WO2002019527A1 (en) * 2000-08-30 2002-03-07 Telefonaktiebolaget Lm Ericsson Direction sensitive and phase-inversion free phase detectors
WO2014196890A1 (en) * 2013-06-06 2014-12-11 Freescale Semiconductor Inc. Phase detector and phase-locked loop

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3634751A1 (en) * 1986-10-11 1988-04-14 Thomson Brandt Gmbh Phase discriminator, especially for a PLL circuit
JPH05275992A (en) * 1992-02-27 1993-10-22 Nec Corp Phase difference measuring circuit system
JP5590867B2 (en) * 2008-12-01 2014-09-17 三星電子株式会社Samsung Electronics Co.,Ltd. Time / digital converter and digital phase-locked loop

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1534233A (en) * 1976-03-02 1978-11-29 Bendix Corp Frequency/phase comparator
US4267514A (en) * 1979-02-16 1981-05-12 The United States Of America As Represented By The Secretary Of The Air Force Digital phase-frequency detector
US4277754A (en) * 1979-10-23 1981-07-07 Matsushita Electric Industrial Co., Ltd. Digital frequency-phase comparator
WO1982001289A1 (en) * 1980-09-29 1982-04-15 Steinlin W Generator circuit of a regulation voltage function of a differential frequency or phase and utilization of such circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4316154A (en) * 1980-04-07 1982-02-16 International Telephone And Telegraph Corporation Automatic sweep and acquisition circuit for a phase locked loop
US4360788A (en) * 1980-07-14 1982-11-23 John Fluke Mfg. Co., Inc. Phase-locked loop frequency synthesizer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1534233A (en) * 1976-03-02 1978-11-29 Bendix Corp Frequency/phase comparator
US4267514A (en) * 1979-02-16 1981-05-12 The United States Of America As Represented By The Secretary Of The Air Force Digital phase-frequency detector
US4277754A (en) * 1979-10-23 1981-07-07 Matsushita Electric Industrial Co., Ltd. Digital frequency-phase comparator
WO1982001289A1 (en) * 1980-09-29 1982-04-15 Steinlin W Generator circuit of a regulation voltage function of a differential frequency or phase and utilization of such circuit

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2587498A1 (en) * 1985-04-29 1987-03-20 Fluke Mfg Co John Detector of digital phase and/or frequency over a wide range
EP0283160A2 (en) * 1987-03-18 1988-09-21 Marconi Instruments Limited Phase comparators
EP0283160A3 (en) * 1987-03-18 1990-03-07 Marconi Instruments Limited Phase comparators
US4884035A (en) * 1987-08-17 1989-11-28 John Fluke Mfg. Co. Inc. Wide range digital phase/frequency detector
EP0316543A2 (en) * 1987-11-20 1989-05-24 Motorola Inc. Frequency synthesizer having digital phase detector with optimal steering and level-type lock indication
EP0316543A3 (en) * 1987-11-20 1989-10-11 Motorola Inc. Frequency synthesizer having digital phase detector with optimal steering and level-type lock indication
EP0991193A1 (en) * 1998-09-29 2000-04-05 Philips Electronics N.V. Radio apparatus comprising a frequency synthesiser and phase discriminator for such an apparatus
US6329847B1 (en) 1998-09-29 2001-12-11 U.S. Phillips Corporation Radio device including a frequency synthesizer and phase discriminator for such a device
WO2002019527A1 (en) * 2000-08-30 2002-03-07 Telefonaktiebolaget Lm Ericsson Direction sensitive and phase-inversion free phase detectors
US6836154B2 (en) 2000-08-30 2004-12-28 Telefonaktiebolaget Lm Ericsson (Publ) Direction sensitive and phase-inversion free phase detectors
WO2014196890A1 (en) * 2013-06-06 2014-12-11 Freescale Semiconductor Inc. Phase detector and phase-locked loop
US9444471B2 (en) 2013-06-06 2016-09-13 Freescale Semiconductor, Inc. Phase detector and phase-locked loop

Also Published As

Publication number Publication date
DE3523787C2 (en) 1989-04-27
GB8512666D0 (en) 1985-06-26
JPS6130814A (en) 1986-02-13
FR2567698B1 (en) 1988-12-23
DE3523787A1 (en) 1986-01-16
FR2567698A1 (en) 1986-01-17

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